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Conv TTL Blocking
Commit 930b94ac authored by gilsoriano's avatar gilsoriano
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Adding the temporal rtl files.

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hdl/m25p32/rtl/m25p32_core.vhd 0 → 100755
View file @ 930b94ac
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 23:57:51 06/10/2012
-- Design Name: m25p32 wishbone access
-- Module Name: m25p32_core - Behavioral
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the logic that governs the access to the m25p32 Non
-- volatile Flash memory
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity m25p32_core is
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
prom_mosi_o : out STD_LOGIC;
prom_cclk_o : out STD_LOGIC;
prom_cso_b_n_o : out STD_LOGIC;
prom_din_o : out STD_LOGIC;
CTR0_i : in STD_LOGIC;
CTR1_i : in STD_LOGIC;
STATUS_i : in STD_LOGIC
);
end m25p32_core;
architecture Behavioral of m25p32_core is
-------------------------------------------------------------------------------
-- WRite ENable bit
---------------------------------------
-- It must be set alwayd before the following instructions:
-- PP_inst Page Program
-- SE_inst Sector Erase
-- BE_inst Bulk Erase
-- WRSR_inst WRite Status Register
---------------------------------------
-- It works by placing:
-- 1.- Chip Select Low
-- 2.- Send instruction
-- 3.- Chip Select High
-------------------------------------------------------------------------------
constant WREN_addr : STD_LOGIC_VECTOR(7 downto 0) := X"06";
------------------------------------------------------------------------------
-- WRite DIsable bit
---------------------------------------
-- It works by placing:
-- 1.- Chip Select Low
-- 2.- Send instruction
-- 3.- Chip Select High
-------------------------------------------------------------------------------
constant WRDI_addr : STD_LOGIC_VECTOR(7 downto 0) := X"04";
------------------------------------------------------------------------------
-- ReaD Status Register
---------------------------------------
--
---------------------------------------
-- It works by placing:
-- 1.- Chip Select Low
-- 2.- Send instruction
-- 3.- Read for the following 8 clocks the serial line
-- NOTE: the RDSR register is sent twice in the serial interface, so it can
-- read the same value of the register twice.
-- 4.- Chip Select High
------------------------------------------------------------------------------
constant RDSR_addr : STD_LOGIC_VECTOR(7 downto 0) := X"05";
------------------------------------------------------------------------------
-- WRite Status Register
---------------------------------------
-- It works by placing:
-- 1.- Chip Select Low
-- 2.- Send instruction
-- 3.- Send the WRSR value
-- 4.- Chip Select High
------------------------------------------------------------------------------
constant WRSR_addr : STD_LOGIC_VECTOR(7 downto 0) := X"01";
constant READ_addr : STD_LOGIC_VECTOR(7 downto 0) := X"03";
constant FAST_READ_addr : STD_LOGIC_VECTOR(7 downto 0) := X"0B";
constant PP_addr : STD_LOGIC_VECTOR(7 downto 0) := X"02";
constant SE_addr : STD_LOGIC_VECTOR(7 downto 0) := X"D8";
constant BE_addr : STD_LOGIC_VECTOR(7 downto 0) := X"C7";
constant DP_addr : STD_LOGIC_VECTOR(7 downto 0) := X"B9";
constant RES_addr : STD_LOGIC_VECTOR(7 downto 0) := X"AB";
begin
comb_proc: process
begin
end process;
reg_proc: process (wb_clk)
begin
if rising_edge(wb_clk) then
if wb_rst_i = '1' then
else
end if;
else
end if;
end process;
end Behavioral;
hdl/m25p32/rtl/m25p32_regs.vhd 0 → 100755
View file @ 930b94ac
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 23:55:10 06/10/2012
-- Design Name: m25p32 wishbone access
-- Module Name: m25p32_regs - Behavioral
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is a wishbone slave able to access m25p32 Non volatile
-- Flash devices and manage the write and read to the memory.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity m25p32_regs is
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
CTR0_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR1_i : in STD_LOGIC_VECTOR (31 downto 0);
STATUS_o : out STD_LOGIC_VECTOR (31 downto 0)
);
end m25p32_regs;
architecture Behavioral of m25p32_regs is
constant CTR0_addr : STD_LOGIC_VECTOR (3 downto 0) := X"0";
constant CTR1_addr : STD_LOGIC_VECTOR (3 downto 0) := X"1";
constant STATUS_addr : STD_LOGIC_VECTOR (3 downto 0) := X"2";
signal s_CTR0 : STD_LOGIC_VECTOR (31 downto 0);
signal s_CTR1 : STD_LOGIC_VECTOR (31 downto 0);
signal s_STATUS : STD_LOGIC_VECTOR (31 downto 0);
signal s_wb_ack_o : STD_LOGIC;
signal s_wb_rty_o : STD_LOGIC;
signal s_wb_err_o : STD_LOGIC;
begin
wbslave_proc: process (wb_clk)
begin
if rising_edge(wb_clk) then
if wb_rst_i = '1' then
s_CTR0 <= (others => '0');
s_CTR1 <= (others => '0');
s_STATUS <= (others => '0');
elsif (wb_stb_i = '1' and wb_cyc_i = '1') then
if (s_wb_ack_o or s_wb_rty_o or s_wb_err_o) = '1' then
s_wb_ack_o <= '0';
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
else
case wb_we_i is
when '1' =>
case wb_addr_i is
when CTR0_addr =>
s_CTR0 <= wb_data_i;
s_wb_ack_o <= '1';
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
when CTR1_addr =>
s_CTR1 <= wb_data_i;
s_wb_ack_o <= '1';
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
when STATUS_addr =>
s_STATUS <= wb_data_i;
s_wb_ack_o <= '1';
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
when others =>
s_wb_ack_o <= '0';
s_wb_rty_o <= '0';
s_wb_err_o <= '1';
end case;
when others =>
case wb_addr_i is
when CTR0_addr =>
wb_data_o <= s_CTR0;
s_wb_ack_o <= '1';
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
when CTR1_addr =>
wb_data_o <= s_CTR1;
s_wb_ack_o <= '1';
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
when STATUS_addr =>
wb_data_o <= s_STATUS;
s_wb_ack_o <= '1';
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
when others =>
s_wb_ack_o <= '0';
s_wb_rty_o <= '0';
s_wb_err_o <= '1';
end case;
end case;
end if;
end if;
else
end if;
end process;
end Behavioral;
hdl/m25p32/rtl/m25p32_top.vhd 0 → 100755
View file @ 930b94ac
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 01:22:27 06/11/2012
-- Design Name: m25p32 top level
-- Module Name: m25p32_top - Behavioral
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity m25p32_top is
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_data_i : out STD_LOGIC_VECTOR(31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
prom_mosi_o : out STD_LOGIC;
prom_cclk_o : out STD_LOGIC;
prom_cs0_b_n_o : out STD_LOGIC;
prom_din_o : out STD_LOGIC
);
end m25p32_top;
architecture Behavioral of m25p32_top is
begin
end Behavioral;
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