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Conv TTL Blocking
Commit 938631db authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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doc/test-log/test-log.tex
View file @ 938631db
......@@ -12,7 +12,7 @@
\title{
\textbf{
Conv-TTL-Blo \\
CONV-TTL-BLO \\
Test Log \\
}
}
......@@ -52,7 +52,7 @@ BE-CO-HT\\
\label{sec:chain-test-1}
The setup for this test is as shown in Fig.~\ref{fig:dct1-setup}. A CTRV board
is used to generate TTL pulses to the Conv-TTL-Blo after which this pulse is
is used to generate TTL pulses to the CONV-TTL-BLO after which this pulse is
daisy-chained as shown in the figure. Both TTL and blocking pulses are generated
in the daisy-chain; Fig.~\ref{fig:dct1-setup} highlights the channel where a
switch from TTL to blocking or viceversa is made.
......@@ -65,20 +65,11 @@ switch from TTL to blocking or viceversa is made.
Three counters in the CTRV are used; the first is the one which generates the
pulses to be sent through the daisy-chain. The output of the first counter is
used as the start signal itself and as the clock for the second-channel counter.
The second channel counter is used as the start signal for the third-channel counter.
The settings for all of the channels are shown in Table~\ref{tbl:ctrv-counters}.
Each CTRV counter generates a pulse signal on the output either when the counter
reaches 0 or when there is a rising edge on the start input. Thus, the configuration
in Table~\ref{tbl:ctrv-counters} yields 1~$\mu$s pulses generated at a frequency of
100~kHz and passed through the daisy-chain. Since the channel 2 counter is configured
with a max. value of two, if any pulse is missed through the daisy-chain, its output
goes high and this causes the channel three counter to trigger an interrupt.
The CTRV is monitored for interrupts using the \textit{ctrvtest} program; any missed
pulses (any interrupts) are time-tagged by the program, thus showing when a pulse was
missed.
used as the start signal for itself and as the clock for the second-channel counter.
The second channel counter is setup to output a DC-level signal (pulse width twice
greatner than the frequency); this signal is used as the start signal for the
third-channel counter. The settings for all of the channels are shown in
Table~\ref{tbl:ctrv-counters}.
\begin{table}[h]
\caption{CTRV counter settings}
......@@ -89,14 +80,26 @@ missed.
\hline
\textbf{Chan} & \textbf{Pulse width} & \textbf{Freq} & \textbf{Max val} \\
\hline
1 & 1~$\mu$s & 100~kHz & 100 \\
2 & -- & -- & 2 \\
3 & -- & -- & 1 \\
1 & 1~$\mu$s & 100~kHz & 100 \\
2 & 20~$\mu$s (DC) & 100~kHz & 2 \\
3 & -- & -- & 1 \\
\hline
\end{tabular}
}
\end{table}
Each CTRV counter generates a pulse signal on the output when the counter reaches 0;
the start signal causes the value of the counter to be reset and the counter to start
counting down. Thus, the configuration in Table~\ref{tbl:ctrv-counters} yields 1~$\mu$s
pulses generated at a frequency of 100~kHz and passed through the daisy-chain. Since the
channel 2 counter is configured with a max. value of two, a start pulse from the channel 1
counter starts the counting down and an arriving pulse from the CONV-TTL-BLO restarts the
counter. If any pulse is missed by the CONV-TTL-BLO through the daisy-chain, the output
of channel 2 counter goes high and this causes the channel three counter to trigger an
interrupt. The CTRV is monitored for interrupts using the \textit{ctrvtest}
program; any missed pulses (any interrupts) are time-tagged by the program, thus showing
when a pulse was missed.
......
doc/ug/ug-conv-ttl-blo.tex
View file @ 938631db
......@@ -138,7 +138,7 @@ be followed in order to test the board.
\item If you intend to use the board with TTL pulses, remove the foliage from the switches. Otherwise, in case only INV-TTL pulses are to arrive
on the front panel connectors, skip this step;
\begin{itemize}
\item If TTL pulses are expected on the TTL channels, set the TTL switch \textcolor{red}{REF TO SWITCHES} to its \textbf{ON} position;
\item If TTL pulses are expected on the TTL channels, set the TTL switch (see Sec.~\ref{sec:switches} to its \textbf{ON} position;
\item Set the pulse type switch in the appropriate position: \textbf{ON} - Glitch-sensitive, no pulse jitter; \textbf{OFF} - Glitch-insensitive, pulse
jitter
\end{itemize}
......@@ -234,7 +234,7 @@ If an optic fibre cable is connected to this socket, White Rabbit precise
time-stamping can be added to CONV-TTL-BLO. Four status LEDs above the connector are provisioned to
show the status of the White Rabbit link.
White Rabbit is currently not supported in the CONV-TTL-BLO firmware.
White Rabbit is currently not supported by the firmware.
\subsubsection{TTL triggers}
One side of the dual LEMO 00 (type EPY) connector on the CONV-TTL-BLO boards
......@@ -251,7 +251,7 @@ pulse received at the rear panel, or of the trigger signal arrived on the front
The pulse width of this output is similar to the pulse output in the rear panel;
the rise time and top pulse level are however different from the blocking output.
Note that the TTL outputs always contain TTL signals (see Sec.~\ref{sec:pulse-def}.
Note that the TTL outputs always contain TTL signals (see Sec.~\ref{sec:pulse-def}).
When the pulse is output, the LED of the corresponding channel blinks for 96~ms.
......@@ -260,7 +260,7 @@ TTL output lines are not internally terminated.
\subsubsection{General-purpose}
Four dedicated inverted-TTL connectors can be found in the lower part of the front panel.
The inputs can be either TTL, or INV-TTL, as selected by the TTL selection switch.
The outputs of these connectors are always INV-TTL level (see Sec.~\ref{sec:pulse-def}.
The outputs of these connectors are always INV-TTL level (see Sec.~\ref{sec:pulse-def}).
INV-TTL inputs are internally terminated with 50$\Omega$ resistors.
......@@ -345,42 +345,38 @@ used by the current version of the FPGA firmware, as shown in Table~\ref{tbl:swi
\begin{table}[h]
\caption{Switches on CONV-TTL-BLO}
\label{tbl:switches}
\begin{tabular}{l p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Switch}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
SW1 & Selects the type of pulse generated at the output \newline
\textbf{ON} -- Glitch-sensitive, without output jitter \newline
\textbf{OFF} -- Glitch-filtered, with output jitter \\
SW8 & TTL/INV-TTL input selection switch \newline
\textbf{ON} -- TTL pulses arrive on TTL and INV-TTL inputs \newline
\textbf{OFF} -- INV-TTL pulses arrive on TTL and INV-TTL inputs \newline
\textit{Note:} This switch applies the selection to the whole board, i.e.,
only TTL or INV-TTL pulses may be input on all channels of the board, not
both \\
\hline
\end{tabular}
\centerline
{
\begin{tabular}{l p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Switch}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
SW1.1 & Selects the type of pulse generated at the output \newline
\textbf{ON} -- Glitch-sensitive, without output jitter \newline
\textbf{OFF} -- Glitch-filtered, with output jitter \\
SW2.4 & TTL/INV-TTL input selection switch \newline
\textbf{ON} -- TTL pulses arrive on TTL and INV-TTL inputs \newline
\textbf{OFF} -- INV-TTL pulses arrive on TTL and INV-TTL inputs \newline
\textit{Note:} This switch applies the selection to the whole board, i.e.,
only TTL or INV-TTL pulses may be input on all channels of the board, not
both \\
\hline
\end{tabular}
}
\end{table}
The switches are shown in Fig.~\ref{fig:switches}. SW1 is used to select whether the
pulse generated at the output should have jitter or not. Based on application and the
environment in which the boards are used, the pulse generated can be one of two types.
\textit{Type 1} pulses have no output jitter, but can be sensitive to glitches, i.e.,
a glitch at the input may trigger the generation of a pulse. \textit{Type 2} pulses
are sensitive to glitches up to 40~ns long, but there is jitter at the output.
\begin{figure}[h]
\centerline{\includegraphics[width=.5\textwidth]{fig/switches}}
\caption{Switches on CONV-TTL-BLO}
\label{fig:switches}
\end{figure}
SW1.1 is used to select whether the pulse generated at the output should have jitter
or not. Based on application and the environment in which the boards are used, the
pulse generated can be one of two types. \textit{Type 1} pulses have no output jitter,
but can be sensitive to glitches, i.e., a glitch at the input may trigger the
generation of a pulse. \textit{Type 2} pulses are sensitive to glitches up to 40~ns
long, but there is jitter at the output.
SW8 is used to select the type of signal that would arrive on the TTL and INV-TTL inputs.
SW2.4 is used to select the type of signal that would arrive on the TTL and INV-TTL inputs.
The switch is valid board-wide, i.e., if it is set for TTL inputs (\textbf{ON}), TTL
signals should be input on both TTL and INV-TTL inputs. Inputting INV-TTL signals on a
channel while the TTL/INV-TTL selection switch is set to TTL invalidates the operation
guaranteed by SW1 and introduces a delay on the generated pulse.
guaranteed by SW1.1 and introduces a delay on the generated pulse.
%======================================================================================
......
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