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Commit 9a04b242 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Starting rewrite of i2c_bit FSM

parent 6924ae51
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hdl/i2c_slave_wb_master/.gitignore deleted 100644 → 0
View file @ 6924ae51
#Ignore LaTeX trash
doc/.*
doc/.*_*
doc/*.*
doc/.*.*.swp
doc/.*.*.swp
doc/Figures/*.eps
!doc/*.tex
!doc/*.pdf
#Ignore autotrash from ISE
project/*
project/*/
!project/project.gise
!project/project.xise
!project/waveform/
#Ignore swap files at rtl/ and test/ folders
rtl/.*.*.swo
rtl/.*.*.swp
test/.*.*.swo
test/.*.*.swp
hdl/i2c_slave_wb_master/project/project.gise deleted 100644 → 0
View file @ 6924ae51
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="project.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="i2c_slave_top_tb.fdo"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1360229226" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1360229226">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1360229226" xil_pn:in_ck="1742451764713501079" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1360229226">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/FIFO_stack.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_counter.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_ff.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/test/wishbone_driver.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/test/wishbone_driver_pkg.vhd"/>
<outfile xil_pn:name="../rtl/i2c_bit.vhd"/>
<outfile xil_pn:name="../rtl/i2c_debounce.vhd"/>
<outfile xil_pn:name="../rtl/i2c_regs.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_core.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_pkg.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_top.vhd"/>
<outfile xil_pn:name="../test/i2c_bit_tb.vhd"/>
<outfile xil_pn:name="../test/i2c_master_driver.vhd"/>
<outfile xil_pn:name="../test/i2c_slave_top_tb.vhd"/>
<outfile xil_pn:name="../test/i2c_tb_pkg.vhd"/>
</transform>
<transform xil_pn:end_ts="1360229226" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-9002096945947998699" xil_pn:start_ts="1360229226">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1360229226" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-4325641994361838445" xil_pn:start_ts="1360229226">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1360229226" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="5962221678014933934" xil_pn:start_ts="1360229226">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1360229226" xil_pn:in_ck="1742451764713501079" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1360229226">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/FIFO_stack.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_counter.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_ff.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/test/wishbone_driver.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/test/wishbone_driver_pkg.vhd"/>
<outfile xil_pn:name="../rtl/i2c_bit.vhd"/>
<outfile xil_pn:name="../rtl/i2c_debounce.vhd"/>
<outfile xil_pn:name="../rtl/i2c_regs.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_core.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_pkg.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_top.vhd"/>
<outfile xil_pn:name="../test/i2c_bit_tb.vhd"/>
<outfile xil_pn:name="../test/i2c_master_driver.vhd"/>
<outfile xil_pn:name="../test/i2c_slave_top_tb.vhd"/>
<outfile xil_pn:name="../test/i2c_tb_pkg.vhd"/>
</transform>
<transform xil_pn:end_ts="1360229228" xil_pn:in_ck="1742451764713501079" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="-3286620494048968334" xil_pn:start_ts="1360229226">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="i2c_slave_top_tb.fdo"/>
</transform>
</transforms>
</generated_project>
hdl/i2c_slave_wb_master/project/waveform/i2c_slave_top_wv.wcfg deleted 100644 → 0
View file @ 6924ae51
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="1.wdb" id="1" type="auto">
<top_modules>
<top_module name="i2c_slave_top_tb" />
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="textio" />
<top_module name="vcomponents" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="19" />
<wvobject fp_name="/i2c_slave_top_tb/uut/sda_oen" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sda_oen</obj_property>
<obj_property name="ObjectShortName">sda_oen</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sda_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sda_i</obj_property>
<obj_property name="ObjectShortName">sda_i</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sda_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sda_o</obj_property>
<obj_property name="ObjectShortName">sda_o</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/scl_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">scl_i</obj_property>
<obj_property name="ObjectShortName">scl_i</obj_property>
</wvobject>
<wvobject fp_name="group42" type="group">
<obj_property name="label">wb</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/i2c_slave_top_tb/uut/wb_clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_clk</obj_property>
<obj_property name="ObjectShortName">wb_clk</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/wb_rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_rst_i</obj_property>
<obj_property name="ObjectShortName">wb_rst_i</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/wb_stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_stb_i</obj_property>
<obj_property name="ObjectShortName">wb_stb_i</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/wb_cyc_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_cyc_i</obj_property>
<obj_property name="ObjectShortName">wb_cyc_i</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/wb_sel_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_sel_i</obj_property>
<obj_property name="ObjectShortName">wb_sel_i</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/wb_we_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_we_i</obj_property>
<obj_property name="ObjectShortName">wb_we_i</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/wb_data_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_data_i[31:0]</obj_property>
<obj_property name="ObjectShortName">wb_data_i[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/wb_data_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_data_o[31:0]</obj_property>
<obj_property name="ObjectShortName">wb_data_o[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/wb_addr_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_addr_i[3:0]</obj_property>
<obj_property name="ObjectShortName">wb_addr_i[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/wb_ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_ack_o</obj_property>
<obj_property name="ObjectShortName">wb_ack_o</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/wb_rty_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_rty_o</obj_property>
<obj_property name="ObjectShortName">wb_rty_o</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/wb_err_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_err_o</obj_property>
<obj_property name="ObjectShortName">wb_err_o</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ind_wb_addr" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ind_wb_addr</obj_property>
<obj_property name="ObjectShortName">ind_wb_addr</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/inst_rd" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">inst_rd</obj_property>
<obj_property name="ObjectShortName">inst_rd</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/inst_wr" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">inst_wr</obj_property>
<obj_property name="ObjectShortName">inst_wr</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/drx0_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">drx0_s[7:0]</obj_property>
<obj_property name="ObjectShortName">drx0_s[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/drx1_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">drx1_s[7:0]</obj_property>
<obj_property name="ObjectShortName">drx1_s[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/drx2_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">drx2_s[7:0]</obj_property>
<obj_property name="ObjectShortName">drx2_s[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/drx3_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">drx3_s[7:0]</obj_property>
<obj_property name="ObjectShortName">drx3_s[7:0]</obj_property>
</wvobject>
<wvobject fp_name="vbus41" type="vbus" db_ref_id="1">
<obj_property name="label">STA</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="vbus75" type="vbus" db_ref_id="1">
<obj_property name="label">i2c_sla_fsm</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[15]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[15]</obj_property>
<obj_property name="ObjectShortName">sta_s[15]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[14]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[14]</obj_property>
<obj_property name="ObjectShortName">sta_s[14]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[13]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[13]</obj_property>
<obj_property name="ObjectShortName">sta_s[13]</obj_property>
<obj_property name="label">sta_s[13]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[12]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[12]</obj_property>
<obj_property name="ObjectShortName">sta_s[12]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[11]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[11]</obj_property>
<obj_property name="ObjectShortName">sta_s[11]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[10]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[10]</obj_property>
<obj_property name="ObjectShortName">sta_s[10]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[9]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[9]</obj_property>
<obj_property name="ObjectShortName">sta_s[9]</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[8]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[8]</obj_property>
<obj_property name="ObjectShortName">sta_s[8]</obj_property>
<obj_property name="label">xxx</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[7]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[7]</obj_property>
<obj_property name="ObjectShortName">sta_s[7]</obj_property>
<obj_property name="label">xxx</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[6]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[6]</obj_property>
<obj_property name="ObjectShortName">sta_s[6]</obj_property>
<obj_property name="label">xxx</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[5]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[5]</obj_property>
<obj_property name="ObjectShortName">sta_s[5]</obj_property>
<obj_property name="label">xxx</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[4]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[4]</obj_property>
<obj_property name="ObjectShortName">sta_s[4]</obj_property>
<obj_property name="label">A_TX</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[3]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">sta_s[3]</obj_property>
<obj_property name="label">A_RX</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[2]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">sta_s[2]</obj_property>
<obj_property name="label">RD_WRN</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[1]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">sta_s[1]</obj_property>
<obj_property name="label">RST</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/sta_s[0]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">sta_s[0]</obj_property>
<obj_property name="label">EN</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="vbus38" type="vbus" db_ref_id="1">
<obj_property name="label">PRE</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/i2c_slave_top_tb/uut/pre_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">pre_s[15:0]</obj_property>
<obj_property name="ObjectShortName">pre_s[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="vbus76" type="vbus" db_ref_id="1">
<obj_property name="label">CTR0</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="vbus93" type="vbus" db_ref_id="1">
<obj_property name="label">A</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[14]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[14]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[14]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[13]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[13]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[13]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[12]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[12]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[12]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[11]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[11]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[11]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[10]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[10]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[10]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[9]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[9]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[9]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[8]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[8]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[8]</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[15]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[15]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[15]</obj_property>
<obj_property name="label">xxx</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[7]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[7]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[7]</obj_property>
<obj_property name="label">BIA[1]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[6]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[6]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[6]</obj_property>
<obj_property name="label">BIA[0]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[5]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[5]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[5]</obj_property>
<obj_property name="label">xxx</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[4]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[4]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[4]</obj_property>
<obj_property name="label">xxx</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[3]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[3]</obj_property>
<obj_property name="label">xxx</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[2]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[2]</obj_property>
<obj_property name="label">PEN</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[1]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[1]</obj_property>
<obj_property name="label">RST</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr0_s[0]" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">ctr0_s[0]</obj_property>
<obj_property name="label">EN</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="vbus94" type="vbus" db_ref_id="1">
<obj_property name="label">CTR1</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="vbus121" type="vbus" db_ref_id="1">
<obj_property name="label">WDS</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[15]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[15]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[15]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[14]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[14]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[14]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[13]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[13]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[13]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[12]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[12]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[12]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[11]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[11]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[11]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[10]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[10]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[10]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[9]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[9]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[9]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[8]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[8]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[8]</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="vbus96" type="vbus" db_ref_id="1">
<obj_property name="label">RDS</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[7]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[7]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[7]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[6]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[6]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[6]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[5]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[5]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[5]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[4]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[4]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[4]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[3]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[3]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[2]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[2]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[1]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[1]</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/ctr1_s[0]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">ctr1_s[0]</obj_property>
</wvobject>
</wvobject>
</wvobject>
<wvobject fp_name="vbus25" type="vbus" db_ref_id="1">
<obj_property name="label">DRXA</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/i2c_slave_top_tb/uut/drx0_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">drx0_s[7:0]</obj_property>
<obj_property name="ObjectShortName">drx0_s[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/drx1_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">drx1_s[7:0]</obj_property>
<obj_property name="ObjectShortName">drx1_s[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/drx2_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">drx2_s[7:0]</obj_property>
<obj_property name="ObjectShortName">drx2_s[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/drx3_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">drx3_s[7:0]</obj_property>
<obj_property name="ObjectShortName">drx3_s[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="vbus26" type="vbus" db_ref_id="1">
<obj_property name="label">DRXB</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/i2c_slave_top_tb/uut/drx4_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">drx4_s[7:0]</obj_property>
<obj_property name="ObjectShortName">drx4_s[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/drx5_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">drx5_s[7:0]</obj_property>
<obj_property name="ObjectShortName">drx5_s[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="vbus33" type="vbus" db_ref_id="1">
<obj_property name="label">DTX</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/i2c_slave_top_tb/uut/dtx0_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dtx0_s[7:0]</obj_property>
<obj_property name="ObjectShortName">dtx0_s[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/dtx1_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dtx1_s[7:0]</obj_property>
<obj_property name="ObjectShortName">dtx1_s[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/dtx2_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dtx2_s[7:0]</obj_property>
<obj_property name="ObjectShortName">dtx2_s[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/i2c_slave_top_tb/uut/dtx3_s" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dtx3_s[7:0]</obj_property>
<obj_property name="ObjectShortName">dtx3_s[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wvobject>
</wave_config>
hdl/i2c_slave_wb_master/project/waveform/wave.do deleted 100644 → 0
View file @ 6924ae51
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group {I2C interface} /i2c_slave_top_tb/uut/scl_i
add wave -noupdate -expand -group {I2C interface} /i2c_slave_top_tb/uut/scl_o
add wave -noupdate -expand -group {I2C interface} /i2c_slave_top_tb/uut/scl_oen
add wave -noupdate -expand -group {I2C interface} /i2c_slave_top_tb/uut/sda_i
add wave -noupdate -expand -group {I2C interface} /i2c_slave_top_tb/uut/sda_o
add wave -noupdate -expand -group {I2C interface} /i2c_slave_top_tb/uut/sda_oen
add wave -noupdate -expand -group {I2C interface} -radix unsigned /i2c_slave_top_tb/uut/i2c_addr_i
add wave -noupdate /i2c_slave_top_tb/uut/wb_clk
add wave -noupdate /i2c_slave_top_tb/uut/wb_rst_i
add wave -noupdate -expand -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_stb_i
add wave -noupdate -expand -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_cyc_i
add wave -noupdate -expand -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_we_i
add wave -noupdate -expand -group {Wishbone Slave} -radix hexadecimal /i2c_slave_top_tb/uut/wb_slave_sel_i
add wave -noupdate -expand -group {Wishbone Slave} -radix hexadecimal /i2c_slave_top_tb/uut/wb_slave_addr_i
add wave -noupdate -expand -group {Wishbone Slave} -radix hexadecimal /i2c_slave_top_tb/uut/wb_slave_data_o
add wave -noupdate -expand -group {Wishbone Slave} -radix hexadecimal /i2c_slave_top_tb/uut/wb_slave_data_i
add wave -noupdate -expand -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_ack_o
add wave -noupdate -expand -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_err_o
add wave -noupdate -expand -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_rty_o
add wave -noupdate -expand -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_stb_o
add wave -noupdate -expand -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_cyc_o
add wave -noupdate -expand -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_we_o
add wave -noupdate -expand -group {Wishbone Master} -radix hexadecimal /i2c_slave_top_tb/uut/wb_master_sel_o
add wave -noupdate -expand -group {Wishbone Master} -radix hexadecimal /i2c_slave_top_tb/uut/wb_master_addr_o
add wave -noupdate -expand -group {Wishbone Master} -radix hexadecimal /i2c_slave_top_tb/uut/wb_master_data_i
add wave -noupdate -expand -group {Wishbone Master} -radix hexadecimal /i2c_slave_top_tb/uut/wb_master_data_o
add wave -noupdate -expand -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_ack_i
add wave -noupdate -expand -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_err_i
add wave -noupdate -expand -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_rty_i
add wave -noupdate -expand -group {Wishbone Master} /i2c_slave_top_tb/uut/inst_i2c_regs/i2c_master_WB_BASIC_fsm
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/i2c_SLA_fsm
add wave -noupdate -divider Registers
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/s_CTR0
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_LT
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/s_DRXA
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/s_DRXB
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/s_DTX
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/s_pf_wb_data
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/i2c_master_WB_BASIC_fsm
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/CTR0_o
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/DTX_o
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/load_TX
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/DRXA_i
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/DRXB_i
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/wb_clk
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/wb_rst_i
add wave -noupdate -group i2c_regs -group {WB master} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_master_addr_o
add wave -noupdate -group i2c_regs -group {WB master} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_master_cyc_o
add wave -noupdate -group i2c_regs -group {WB master} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_master_data_o
add wave -noupdate -group i2c_regs -group {WB master} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_master_sel_o
add wave -noupdate -group i2c_regs -group {WB master} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_master_stb_o
add wave -noupdate -group i2c_regs -group {WB master} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_master_we_o
add wave -noupdate -group i2c_regs -group {WB master} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_master_ack_i
add wave -noupdate -group i2c_regs -group {WB master} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_master_data_i
add wave -noupdate -group i2c_regs -group {WB master} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_master_err_i
add wave -noupdate -group i2c_regs -group {WB master} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_master_rty_i
add wave -noupdate -group i2c_regs -group {WB slave} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_slave_addr_i
add wave -noupdate -group i2c_regs -group {WB slave} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_slave_cyc_i
add wave -noupdate -group i2c_regs -group {WB slave} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_slave_data_i
add wave -noupdate -group i2c_regs -group {WB slave} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_slave_sel_i
add wave -noupdate -group i2c_regs -group {WB slave} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_slave_stb_i
add wave -noupdate -group i2c_regs -group {WB slave} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_slave_we_i
add wave -noupdate -group i2c_regs -group {WB slave} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_slave_ack_o
add wave -noupdate -group i2c_regs -group {WB slave} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_slave_data_o
add wave -noupdate -group i2c_regs -group {WB slave} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_slave_err_o
add wave -noupdate -group i2c_regs -group {WB slave} /i2c_slave_top_tb/uut/inst_i2c_regs/wb_slave_rty_o
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/i2c_addr_i
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/pf_wb_addr_i
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/rd_done_i
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/wr_done_i
add wave -noupdate -expand -group bit_counter /i2c_slave_top_tb/i2c_driver/s_scl_clk
add wave -noupdate -expand -group bit_counter /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_bit_cnt
add wave -noupdate -expand -group bit_counter /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/clk_i
add wave -noupdate -expand -group bit_counter -radix unsigned /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/cnt_o
add wave -noupdate -expand -group bit_counter /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/en_i
add wave -noupdate -expand -group bit_counter /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/rst_i
add wave -noupdate -expand -group byte_counter /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/clk_i
add wave -noupdate -expand -group byte_counter /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/rst_i
add wave -noupdate -expand -group byte_counter /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/en_i
add wave -noupdate -expand -group byte_counter -radix unsigned /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/cnt_o
add wave -noupdate -group watchdog /i2c_slave_top_tb/uut/inst_i2c_slave_core/watchdog_counter_8/clk_i
add wave -noupdate -group watchdog /i2c_slave_top_tb/uut/inst_i2c_slave_core/watchdog_counter_8/rst_i
add wave -noupdate -group watchdog /i2c_slave_top_tb/uut/inst_i2c_slave_core/watchdog_counter_8/en_i
add wave -noupdate -group watchdog /i2c_slave_top_tb/uut/inst_i2c_slave_core/watchdog_counter_8/cnt_o
add wave -noupdate -divider {MCU signals}
add wave -noupdate /i2c_slave_top_tb/uut/pf_wb_addr_o
add wave -noupdate /i2c_slave_top_tb/uut/wr_done_o
add wave -noupdate /i2c_slave_top_tb/uut/rd_done_o
add wave -noupdate -divider {I2C driver}
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/tb_clk
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/scl_master_o
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/sda_master_i
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/sda_master_o
add wave -noupdate -group i2c_driver -radix hexadecimal /i2c_slave_top_tb/i2c_driver/wishbone_addr_i
add wave -noupdate -group i2c_driver -radix hexadecimal /i2c_slave_top_tb/i2c_driver/wr_data_i
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/start_i
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/write_i
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/read_i
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/start_done_o
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/write_done_o
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/read_done_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_regs/s_CTR0
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_DRX_slv
add wave -noupdate /i2c_slave_top_tb/wb_driver/wb_data_i
add wave -noupdate /i2c_slave_top_tb/wb_driver/wb_data_o
add wave -noupdate /i2c_slave_top_tb/wb_driver/data_o
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_addr_o
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_clk_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_rst_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_stb_o
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_cyc_o
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_sel_o
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_we_o
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_ack_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_rty_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_err_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/data_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/addr_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/write_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/write_done_o
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/read_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/read_done_o
add wave -noupdate /i2c_slave_top_tb/s_feedback_wb_bus
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1030400000 ps} 0}
configure wave -namecolwidth 325
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {765068158 ps} {1416341376 ps}
hdl/i2c_to_wb_bridge/rtl/Manifest.py 0 → 100644
View file @ 9a04b242
files = [
"i2c_slave_pkg.vhd",
"i2c_debounce.vhd",
"i2c_bit.vhd",
"bridge_regs.vhd",
"bridge.vhd",
"i2c_to_wb_bridge.vhd"
]
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd → hdl/i2c_to_wb_bridge/rtl/bridge.vhd
View file @ 9a04b242
......@@ -5,7 +5,7 @@
--
-- Create Date: 11:29:56 10/25/2011
-- Design Name: I2C Slave to Wishbone bridge
-- Module Name: i2c_slave_core - Behavioral
-- Module Name: bridge - behav
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
......@@ -56,9 +56,8 @@ library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
entity i2c_slave_core is
entity bridge is
generic
(
g_WB_CLK_PERIOD : time := 50 ns
......@@ -76,10 +75,10 @@ entity i2c_slave_core is
scl_o : out std_logic;
-- Registers
CTR0_i : in std_logic_vector (r_CTR0'a_length - 1 downto 0);
LT_o : out std_logic_vector (r_LT'a_length - 1 downto 0);
DRXA_o : out std_logic_vector (r_DRX'a_length - 1 downto 0);
DRXB_o : out std_logic_vector (r_DRX'a_length - 1 downto 0);
ctr0_i : in std_logic_vector(31 downto 0);
lt_o : out std_logic_vector(31 downto 0);
drxa_o : out std_logic_vector(31 downto 0);
drxb_o : out std_logic_vector(31 downto 0);
-- Alarms for controlling the i2c states
pf_wb_addr_o : out std_logic;
......@@ -87,11 +86,11 @@ entity i2c_slave_core is
rd_done_o : out std_logic;
wr_done_o : out std_logic
);
end i2c_slave_core;
end entity bridge;
architecture Behavioral of i2c_slave_core is
architecture behav of bridge is
type t_state is (
R0_RESET,
......@@ -116,6 +115,37 @@ architecture Behavioral of i2c_slave_core is
S7_PAUSE_DETECT
);
component i2c_bit is
port
(
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
sda_i : in STD_LOGIC;
scl_i : in STD_LOGIC;
start_o : out STD_LOGIC;
pause_o : out STD_LOGIC;
rcved_o : out STD_LOGIC;
done_o : out STD_LOGIC
);
end component i2c_bit;
component gc_counter is
generic
(
g_DATA_WIDTH: NATURAL
);
port
(
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0)
);
end component gc_counter;
-------------------------------------------------------------------------------
-- FSM signals for the I2C module
-------------------------------------------------------------------------------
......@@ -125,20 +155,20 @@ architecture Behavioral of i2c_slave_core is
-- signal coming from i2c_bit.vhd
-- Every time a deglitched falling edge of the SCL line is detected in the
-- aforementioned i2c_bit.vhd, the signals done, start_o, pause_o, rcved_o are
-- considered valid to be studied in i2c_slave_core.vhd processes.
-- considered valid to be studied in bridge.vhd processes.
--
-------------------------------------------------------------------------------
constant c_WATCHDOG_END_VALUE : NATURAL := c_WATCHDOG_DEADLINE/g_WB_CLK_PERIOD;
constant c_WATCHDOG_END_VALUE : NATURAL := 10**9; -- 8sec reset period
signal state : t_state := R0_RESET;
signal state_d0 : t_state := R0_RESET;
signal s_DRXA_slv : std_logic_vector(r_DRX'a_length - 1 downto 0) := (others => '0');
signal s_DRXB_slv : std_logic_vector(r_DRX'a_length - 1 downto 0) := (others => '0');
signal s_DRX_slv : std_logic_vector(r_DRX'a_length*2 - 1 downto 0) := (others => '0');
signal s_DTX_slv : std_logic_vector(r_DTX'a_length - 1 downto 0);
signal s_DRXA_slv : std_logic_vector(31 downto 0) := (others => '0');
signal s_DRXB_slv : std_logic_vector(31 downto 0) := (others => '0');
signal s_DRX_slv : std_logic_vector(63 downto 0) := (others => '0');
signal s_DTX_slv : std_logic_vector(31 downto 0);
signal s_CTR0 : r_CTR0;
signal s_LT : r_LT := c_LT_default;
......@@ -181,15 +211,15 @@ architecture Behavioral of i2c_slave_core is
begin
s_CTR0 <= f_CTR0(CTR0_i);
LT_o <= f_STD_LOGIC_VECTOR(s_LT);
s_CTR0 <= f_CTR0(ctr0_i);
lt_o <= f_STD_LOGIC_VECTOR(s_LT);
s_pf_wb_data <= pf_wb_data_i;
cmp_i2c_bit: i2c_bit
port map
(
rst_i => rst_i,
wb_clk_i => clk_i,
clk_i => clk_i,
sda_i => sda_i,
scl_i => scl_i,
start_o => s_start_o,
......@@ -376,8 +406,8 @@ begin
end if;
end process;
DRXA_o <= s_DRXA_slv;
DRXB_o <= s_DRXB_slv;
drxa_o <= s_DRXA_slv;
drxb_o <= s_DRXB_slv;
-- Process to update the signals that drive bit_counter_8
p_bit_counter_comb : process(state, state_d0, s_byte_cnt)
......@@ -729,4 +759,4 @@ begin
end if;
end process p_fsm;
end Behavioral;
end behav;
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd → hdl/i2c_to_wb_bridge/rtl/bridge_regs.vhd
View file @ 9a04b242
......@@ -4,7 +4,7 @@
--
-- Create Date: 11:56:55 10/25/2011
-- Design Name: I2C slave register HDL
-- Module Name: i2c_regs - Behavioral
-- Module Name: bridge_regs - behav
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
......@@ -24,63 +24,63 @@
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
entity i2c_regs is
entity bridge_regs is
port
(
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_we_o : out STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_master_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_adr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_master_we_o : out std_logic;
wb_master_stb_o : out std_logic;
wb_master_cyc_o : out std_logic;
wb_master_sel_o : out std_logic_vector(3 downto 0);
wb_master_dat_i : in std_logic_vector(31 downto 0);
wb_master_dat_o : out std_logic_vector(31 downto 0);
wb_master_adr_o : out std_logic_vector(15 downto 0);
wb_master_ack_i : in std_logic;
wb_master_rty_i : in std_logic;
wb_master_err_i : in std_logic;
-- These are the registers offers to others modules of the FPGA
wb_slave_we_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_slave_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_slave_adr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
wb_slave_we_i : in std_logic;
wb_slave_stb_i : in std_logic;
wb_slave_cyc_i : in std_logic;
wb_slave_sel_i : in std_logic_vector(3 downto 0);
wb_slave_dat_i : in std_logic_vector(31 downto 0);
wb_slave_dat_o : out std_logic_vector(31 downto 0);
wb_slave_adr_i : in std_logic_vector(3 downto 0);
wb_slave_ack_o : out std_logic;
wb_slave_rty_o : out std_logic;
wb_slave_err_o : out std_logic;
-- These are the registers that are offered to the i2c slave core
CTR0_o : out STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
LT_i : in STD_LOGIC_VECTOR (r_LT'a_length -1 downto 0);
DRXA_i : in STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
DRXB_i : in STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
pf_wb_addr_i : in STD_LOGIC;
pf_wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
rd_done_i : in STD_LOGIC;
wr_done_i : in STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
ctr0_o : out std_logic_vector(31 downto 0);
lt_i : in std_logic_vector(31 downto 0);
drxa_i : in std_logic_vector(31 downto 0);
drxb_i : in std_logic_vector(31 downto 0);
pf_wb_addr_i : in std_logic;
pf_wb_data_o : out std_logic_vector(31 downto 0);
rd_done_i : in std_logic;
wr_done_i : in std_logic;
i2c_addr_i : in std_logic_vector(6 downto 0)
);
end i2c_regs;
end entity bridge_regs;
architecture Behavioral of i2c_regs is
architecture behav of bridge_regs is
type t_wb_state is (
R0_RESET,
S0_IDLE,
S1P_WB_RD_RQT, --! Prefetch
S1P_WB_RD_RQT, -- Prefetch
S1_WB_RD_RQT,
S1N_WB_NOOP,
S1_PF_WB_DATA_OUT,
S2P_WB_WR_RQT, --! Prefetch
S2P_WB_WR_RQT, -- Prefetch
S2_WB_WR_RQT,
S2N_WB_NOOP,
S3_WB_ACK
......@@ -88,33 +88,33 @@ architecture Behavioral of i2c_regs is
signal wb_state : t_wb_state := R0_RESET;
signal s_wb_slave_addr : UNSIGNED(3 downto 0);
signal s_wb_slave_ack : STD_LOGIC := '0';
signal s_wb_slave_rty : STD_LOGIC := '0';
signal s_wb_slave_err : STD_LOGIC := '0';
signal s_wb_slave_addr : unsigned(3 downto 0);
signal s_wb_slave_ack : std_logic := '0';
signal s_wb_slave_rty : std_logic := '0';
signal s_wb_slave_err : std_logic := '0';
signal s_CTR0_slv : STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
signal s_CTR0_slv : std_logic_vector (r_CTR0'a_length - 1 downto 0);
signal s_CTR0 : r_CTR0 := c_CTR0_default;
signal s_LT : r_LT;
signal s_DTX : STD_LOGIC_VECTOR (r_DTX'a_length - 1 downto 0);
signal s_DTX : std_logic_vector (r_DTX'a_length - 1 downto 0);
signal s_wb_master_we_o : STD_LOGIC;
signal mst_we : std_logic;
signal s_wb_master_ack_retries : STD_LOGIC_VECTOR(c_RETRY_LENGTH - 1 downto 0) := (others => '0');
signal s_wb_addr_rd : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal s_wb_master_ack_retries : std_logic_vector(c_RETRY_LENGTH - 1 downto 0) := (others => '0');
signal s_wb_addr_rd : std_logic_vector(15 downto 0) := (others => '0');
begin
wb_master_we_o <= s_wb_master_we_o;
wb_master_we_o <= mst_we;
s_wb_slave_addr <= UNSIGNED(wb_slave_adr_i);
s_CTR0_slv <= f_STD_LOGIC_VECTOR(s_CTR0);
s_LT <= f_LT(LT_i);
s_CTR0_slv <= f_std_logic_vector(s_CTR0);
s_LT <= f_LT(lt_i);
wb_slave_ack_o <= s_wb_slave_ack;
wb_slave_rty_o <= s_wb_slave_rty;
wb_slave_err_o <= s_wb_slave_err;
CTR0_o <= s_CTR0_slv;
ctr0_o <= s_CTR0_slv;
pf_wb_data_o <= s_DTX;
--! @brief Process that controls the retries of the wishbone interface
......@@ -133,80 +133,6 @@ begin
end if;
end process;
-- Process that outputs the wishbone
-- master interface. It should be noted
-- that we double-buffer the received data
-- to assure consistency of the data to be
-- read/written when repetitions of the
-- wishbone master interface happen.
p_wb_master: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
s_wb_master_we_o <= '0';
wb_master_stb_o <= '0';
wb_master_cyc_o <= '0';
wb_master_sel_o <= (others => '0');
wb_master_dat_o <= (others => '0');
wb_master_adr_o <= (others => '0');
s_dtx <= (others => '0');
else
case wb_state is
when R0_RESET =>
null;
when S0_IDLE =>
null;
when S1P_WB_RD_RQT =>
s_wb_addr_rd <= DRXA_i(23 downto 8);
when S1_WB_RD_RQT =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
wb_master_sel_o <= X"F";
wb_master_adr_o <= s_wb_addr_rd;
when S1N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
wb_master_sel_o <= X"F";
wb_master_adr_o <= s_wb_addr_rd;
when S1_PF_WB_DATA_OUT =>
s_DTX <= wb_master_dat_i;
when S2P_WB_WR_RQT =>
null;
when S2_WB_WR_RQT =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F";
wb_master_dat_o <= f_ch_endian(DRXA_i);
wb_master_adr_o <= DRXB_i(15 downto 0);
when S2N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F";
wb_master_dat_o <= f_ch_endian(DRXA_i);
wb_master_adr_o <= DRXB_i(15 downto 0);
when S3_WB_ACK =>
-- null;
wb_master_cyc_o <= '0';
wb_master_stb_o <= '0';
s_wb_master_we_o <= '0';
when others =>
null;
end case;
end if;
end if;
end process p_wb_master;
-- Process to rule slave wishbone outputs
p_wb_slave: process (wb_clk_i)
begin
......@@ -238,19 +164,19 @@ begin
s_wb_slave_ack <= '1';
case s_wb_slave_addr is
when c_CTR0_addr =>
wb_slave_dat_o <= f_STD_LOGIC_VECTOR(s_CTR0);
wb_slave_dat_o <= f_std_logic_vector(s_CTR0);
when c_LT_addr =>
wb_slave_dat_o <= f_STD_LOGIC_VECTOR(s_LT);
wb_slave_dat_o <= f_std_logic_vector(s_LT);
when c_DTX_addr =>
wb_slave_dat_o <= s_DTX;
when c_DRXA_addr =>
wb_slave_dat_o <= DRXA_i;
wb_slave_dat_o <= drxa_i;
when c_DRXB_addr =>
wb_slave_dat_o <= DRXB_i;
wb_slave_dat_o <= drxb_i;
when others =>
s_wb_slave_ack <= '0';
......@@ -263,15 +189,87 @@ begin
end process;
-- Process that outputs the wishbone
-- master interface. It should be noted
-- that we double-buffer the received data
-- to assure consistency of the data to be
-- read/written when repetitions of the
-- wishbone master interface happen.
p_wb_master: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
mst_we <= '0';
wb_master_stb_o <= '0';
wb_master_cyc_o <= '0';
wb_master_sel_o <= (others => '0');
wb_master_dat_o <= (others => '0');
wb_master_adr_o <= (others => '0');
s_dtx <= (others => '0');
else
case wb_state is
when R0_RESET =>
null;
when S0_IDLE =>
null;
when S1P_WB_RD_RQT =>
s_wb_addr_rd <= drxa_i(23 downto 8);
when S1_WB_RD_RQT =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
wb_master_sel_o <= X"F";
wb_master_adr_o <= s_wb_addr_rd;
when S1N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
wb_master_sel_o <= X"F";
wb_master_adr_o <= s_wb_addr_rd;
when S1_PF_WB_DATA_OUT =>
s_DTX <= wb_master_dat_i;
when S2P_WB_WR_RQT =>
null;
when S2_WB_WR_RQT =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
mst_we <= '1';
wb_master_sel_o <= X"F";
wb_master_dat_o <= f_ch_endian(drxa_i);
wb_master_adr_o <= drxb_i(15 downto 0);
when S2N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
mst_we <= '1';
wb_master_sel_o <= X"F";
wb_master_dat_o <= f_ch_endian(drxa_i);
wb_master_adr_o <= drxb_i(15 downto 0);
when S3_WB_ACK =>
-- null;
wb_master_cyc_o <= '0';
wb_master_stb_o <= '0';
mst_we <= '0';
when others =>
null;
end case;
end if;
end if;
end process p_wb_master;
-- This is the process that controls the wishbone master interface
-- which bridges the i2c interface with the wishbone interface.
p_master_fsm: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
-- Here is the part in which we propagate the reset, let one-clock
-- for it.
wb_state <= R0_RESET;
wb_state <= R0_RESET;
else
case wb_state is
when R0_RESET =>
......@@ -306,7 +304,7 @@ begin
-- We stop retrying to not block the core
wb_state <= R0_RESET;
else
if s_wb_master_we_o = '1' then
if mst_we = '1' then
wb_state <= S1_WB_RD_RQT;
else
wb_state <= S2_WB_WR_RQT;
......@@ -322,4 +320,4 @@ begin
end if;
end process p_master_fsm;
end Behavioral;
end behav;
hdl/i2c_slave_wb_master/rtl/i2c_bit.vhd → hdl/i2c_to_wb_bridge/rtl/i2c_bit.vhd
View file @ 9a04b242
......@@ -4,7 +4,7 @@
--
-- Create Date: 00:47:34 10/26/2011
-- Design Name: i2c bit recognition fsm
-- Module Name: i2c_bit - Behavioral
-- Module Name: i2c_bit - behav
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
......@@ -25,14 +25,12 @@ library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
entity i2c_bit is
port
(
rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
sda_i : in STD_LOGIC;
scl_i : in STD_LOGIC;
......@@ -44,7 +42,23 @@ entity i2c_bit is
);
end i2c_bit;
architecture Behavioral of i2c_bit is
architecture behav of i2c_bit is
component i2c_debouncer is
generic
(
g_LENGTH : NATURAL := 6
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0)
);
end component i2c_debouncer;
type t_state is (
R0_RESET,
......@@ -60,22 +74,22 @@ architecture Behavioral of i2c_bit is
);
-- It specifies the maximum number of stages that will be employed for
-- deglitching. Clocked with wb_clk_i
-- deglitching. Clocked with clk_i
constant c_MAX_GLITCH_DELAY : NATURAL := 6;
-- Three delay stages out of six
constant c_GLITCH_MASK : STD_LOGIC_VECTOR (5 downto 0) := "000111";
signal s_sda_deglitched : STD_LOGIC;
signal s_sda_deglitched_d1 : STD_LOGIC;
signal sda_deglitched : STD_LOGIC;
signal sda_deglitched_d1 : STD_LOGIC;
signal s_scl_deglitched : STD_LOGIC;
signal s_scl_deglitched_d1 : STD_LOGIC;
signal scl_deglitched : STD_LOGIC;
signal scl_deglitched_d1 : STD_LOGIC;
signal state : t_state;
signal s_scl_rising : STD_LOGIC;
signal s_scl_falling : STD_LOGIC;
signal scl_rising : STD_LOGIC;
signal scl_falling : STD_LOGIC;
begin
......@@ -87,27 +101,13 @@ begin
port map
(
rst => rst_i,
clk => wb_clk_i,
clk => clk_i,
input => scl_i,
output => s_scl_deglitched,
output => scl_deglitched,
glitch_mask => c_GLITCH_MASK
);
-- Probably safer operation if we add one extra delay to the scl line.
-- However, we increase the glitch time while placing an ACK.
-- We have not implemented a counter to foresee the glitch due to the
-- strange behaviour in Renesas I2C which rescales dinamically (that
-- means in the middle of an I2C transaction) the scl line.
-- Due to the variability of the scl period when an I2C transaction is
cmp_scl_ff: gc_ff
port map
(
Q => s_scl_deglitched_d1,
C => wb_clk_i,
CLR => rst_i,
D => s_scl_deglitched
);
cmp_sda_debounce: i2c_debouncer
generic map
(
......@@ -116,41 +116,46 @@ begin
port map
(
rst => rst_i,
clk => wb_clk_i,
clk => clk_i,
input => sda_i,
output => s_sda_deglitched,
output => sda_deglitched,
glitch_mask => c_GLITCH_MASK
);
cmp_sda_ff: gc_ff
port map
(
Q => s_sda_deglitched_d1,
C => wb_clk_i,
CLR => rst_i,
D => s_sda_deglitched
);
process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
sda_deglitched_d1 <= '0';
scl_deglitched_d1 <= '0';
else
sda_deglitched_d1 <= sda_deglitched;
scl_deglitched_d1 <= scl_deglitched;
end if;
end if;
end process;
-- This is the process that samples the scl for detecting
-- rise and falling edges
reg_proc: process (wb_clk_i)
reg_proc: process (clk_i)
begin
if rising_edge(wb_clk_i) then
if (s_scl_deglitched xor s_scl_deglitched_d1) = '1' then
if s_scl_deglitched = '0' then
s_scl_falling <= '1';
else
s_scl_rising <= '1';
end if;
if rising_edge(clk_i) then
if (rst_i = '1') then
scl_falling <= '0';
scl_rising <= '0';
elsif (scl_deglitched = '0') and (scl_deglitched_d1 = '1') then
scl_falling <= '1';
elsif (scl_deglitched = '1') and (scl_deglitched_d1 = '0') then
scl_rising <= '1';
else
s_scl_rising <= '0';
s_scl_falling <= '0';
scl_falling <= '0';
scl_rising <= '0';
end if;
end if;
end process;
-- Combinatorial process to update the outputs.
-- Combinatorial process to update the outputs.
p_comb_output: process(state)
begin
start_o <= '0';
......@@ -194,13 +199,12 @@ begin
-- The fsm of this module, later on the sda sampled line is
-- validated in the falling edge of scl.
p_fsm: process(wb_clk_i)
p_fsm: process(clk_i)
begin
if rising_edge(wb_clk_i) then
if rising_edge(clk_i) then
if (rst_i = '1') then
state <= R0_RESET;
elsif (s_scl_falling = '1') then
state <= R0_RESET;
elsif scl_falling = '1' then
-- After a detection of a falling edge we update the
-- detection of a '0', a '1' and a start condition.
case state is
......@@ -217,10 +221,10 @@ begin
state <= S0_IDLE;
end case;
elsif (s_scl_rising = '1') then
elsif (scl_rising = '1') then
-- When a rising edge is detected we annotate the first value
-- in SDA: either a temporary '0' or '1'
if (s_sda_deglitched_d1 = '1') then
if (sda_deglitched_d1 = '1') then
state <= S1A_HIGH_TMP;
else
state <= S1B_LOW_TMP;
......@@ -229,32 +233,32 @@ begin
else
-- When we are in high level of a scl cycle, we keep on updating
-- the FSM
if (s_scl_deglitched = '1') then
if (scl_deglitched = '1') then
case state is
-- Just for random bit swapped coverage.
when S0_IDLE =>
if (s_sda_deglitched = '1') then
if (sda_deglitched = '1') then
state <= S1A_HIGH_TMP;
else
state <= S1B_LOW_TMP;
end if;
when S1A_HIGH_TMP =>
if s_sda_deglitched = '0' then
if sda_deglitched = '0' then
-- The detection of the start condition will be reported
-- in the next SCL rising edge.
state <= S2A_START_TMP;
end if;
when S1B_LOW_TMP =>
if s_sda_deglitched = '1' then
if sda_deglitched = '1' then
-- The detection of the pause condition MUST be
-- reported immediately.
state <= S2B_STOP_DETECT;
end if;
when S2A_START_TMP =>
if (s_sda_deglitched = '1') then
if (sda_deglitched = '1') then
--! This happens if the deglitching is not enough
state <= Q1_ERROR;
end if;
......@@ -263,7 +267,7 @@ begin
state <= S0_IDLE;
end case;
else
if (s_scl_deglitched_d1 = '0') then
if (scl_deglitched_d1 = '0') then
state <= S0_IDLE;
end if;
end if;
......@@ -271,4 +275,4 @@ begin
end if;
end process p_fsm;
end Behavioral;
end behav;
hdl/i2c_slave_wb_master/rtl/i2c_debounce.vhd → hdl/i2c_to_wb_bridge/rtl/i2c_debounce.vhd
View file @ 9a04b242
......@@ -26,13 +26,11 @@ library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
entity i2c_debouncer is
generic
(
g_LENGTH : NATURAL := c_DEBOUNCE_LENGTH
g_LENGTH : NATURAL := 6
);
port
(
......@@ -46,40 +44,25 @@ end i2c_debouncer;
architecture Behavioral of i2c_debouncer is
signal s_input_d0 : STD_LOGIC;
signal input_d0 : STD_LOGIC;
-- The first of this signal is already stable (ff'ed two times at [0])
signal s_delay : STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0);
signal delay : STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0);
begin
cmp_ff1: gc_ff
port map
(
Q => s_input_d0,
C => clk,
CLR => rst,
D => input
);
cmp_ff2: gc_ff
port map
(
Q => s_delay(0),
C => clk,
CLR => rst,
D => s_input_d0
);
gen_sync_delay_line: for i in 1 to g_LENGTH - 1 generate
cmp_ff: gc_ff
port map
(
Q => s_delay(i),
C => clk,
CLR => rst,
D => s_delay(i-1)
);
end generate gen_sync_delay_line;
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
input_d0 <= '0';
delay <= (others => '0');
else
input_d0 <= input;
delay(0) <= input_d0;
delay(g_length-1 downto 1) <= delay(g_length-2 downto 0);
end if;
end if;
end process;
p_output: process (clk)
begin
......@@ -88,9 +71,9 @@ begin
output <= '1';
else
-- We can deglitch either zeros or ones
if ( (s_delay and glitch_mask) = glitch_mask
or (not(s_delay) and glitch_mask) = glitch_mask) then
output <= s_delay(0);
if ( (delay and glitch_mask) = glitch_mask
or (not(delay) and glitch_mask) = glitch_mask) then
output <= delay(0);
else
-- Internall pull-up of the pin
output <= '1';
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd → hdl/i2c_to_wb_bridge/rtl/i2c_to_wb_bridge.vhd
View file @ 9a04b242
......@@ -4,7 +4,7 @@
--
-- Create Date: 18:15:56 11/09/2011
-- Design Name: A I2C slave with wishbone slave output and interrupt for MCU
-- Module Name: i2c_slave_top - Behavioral
-- Module Name: i2c_to_wb_bridge - behav
-- Project Name: CTDAH
-- Target Devices:
-- Tool versions:
......@@ -22,71 +22,137 @@ library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
use work.i2c_slave_pkg.all;
entity i2c_slave_top is
generic
(
g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD -- Specify in ns
);
entity i2c_to_wb_bridge is
port
(
sda_en_o : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_en_o : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_master_we_o : out STD_LOGIC;
wb_master_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_adr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_we_i : in STD_LOGIC;
wb_slave_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_adr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
pf_wb_addr_o : out STD_LOGIC;
rd_done_o : out STD_LOGIC;
wr_done_o : out STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
clk_i : in std_logic;
rst_i : in std_logic;
wb_master_stb_o : out std_logic;
wb_master_cyc_o : out std_logic;
wb_master_sel_o : out std_logic_vector(3 downto 0);
wb_master_we_o : out std_logic;
wb_master_dat_i : in std_logic_vector(31 downto 0);
wb_master_dat_o : out std_logic_vector(31 downto 0);
wb_master_adr_o : out std_logic_vector(15 downto 0);
wb_master_ack_i : in std_logic;
wb_master_rty_i : in std_logic;
wb_master_err_i : in std_logic;
wb_slave_stb_i : in std_logic;
wb_slave_cyc_i : in std_logic;
wb_slave_sel_i : in std_logic_vector(3 downto 0);
wb_slave_we_i : in std_logic;
wb_slave_dat_i : in std_logic_vector(31 downto 0);
wb_slave_dat_o : out std_logic_vector(31 downto 0);
wb_slave_adr_i : in std_logic_vector(3 downto 0);
wb_slave_ack_o : out std_logic;
wb_slave_rty_o : out std_logic;
wb_slave_err_o : out std_logic;
pf_wb_addr_o : out std_logic;
rd_done_o : out std_logic;
wr_done_o : out std_logic;
i2c_addr_i : in std_logic_vector(6 downto 0)
);
end i2c_slave_top;
architecture Behavioral of i2c_slave_top is
signal ctr0 : STD_LOGIC_VECTOR(r_CTR0'a_length - 1 downto 0);
signal lt : STD_LOGIC_VECTOR(r_LT'a_length - 1 downto 0);
signal drxa : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal drxb : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal pf_wb_addr : STD_LOGIC;
signal pf_wb_data : STD_LOGIC_VECTOR(31 downto 0);
signal rd_done : STD_LOGIC;
signal wr_done : STD_LOGIC;
signal s_clk_i2c : STD_LOGIC;
signal rst_i2c : STD_LOGIC;
signal reset_extender: STD_LOGIC_VECTOR(2**c_RST_EXTENSOR - 1 downto 0) := (others => '1');
end i2c_to_wb_bridge;
architecture behav of i2c_to_wb_bridge is
component bridge is
generic
(
g_WB_CLK_PERIOD : time := 50 ns
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
-- I2C pins
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
-- Registers
CTR0_i : in std_logic_vector (r_CTR0'a_length - 1 downto 0);
LT_o : out std_logic_vector (r_LT'a_length - 1 downto 0);
DRXA_o : out std_logic_vector (r_DRX'a_length - 1 downto 0);
DRXB_o : out std_logic_vector (r_DRX'a_length - 1 downto 0);
-- Alarms for controlling the i2c states
pf_wb_addr_o : out std_logic;
pf_wb_data_i : in std_logic_vector(31 downto 0);
rd_done_o : out std_logic;
wr_done_o : out std_logic
);
end component bridge;
component bridge_regs is
port
(
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_we_o : out STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_master_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_adr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
-- These are the registers offers to others modules of the FPGA
wb_slave_we_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_slave_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_slave_adr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
-- These are the registers that are offered to the i2c slave core
ctr0_o : out STD_LOGIC_VECTOR (31 downto 0);
lt_i : in STD_LOGIC_VECTOR (31 downto 0);
drxa_i : in STD_LOGIC_VECTOR (31 downto 0);
drxb_i : in STD_LOGIC_VECTOR (31 downto 0);
pf_wb_addr_i : in STD_LOGIC;
pf_wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
rd_done_i : in STD_LOGIC;
wr_done_i : in STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
);
end component bridge_regs;
signal ctr0 : std_logic_vector(r_CTR0'a_length - 1 downto 0);
signal lt : std_logic_vector(r_LT'a_length - 1 downto 0);
signal drxa : std_logic_vector(r_DRX'a_length - 1 downto 0);
signal drxb : std_logic_vector(r_DRX'a_length - 1 downto 0);
signal pf_wb_addr : std_logic;
signal pf_wb_data : std_logic_vector(31 downto 0);
signal rd_done : std_logic;
signal wr_done : std_logic;
begin
......@@ -94,11 +160,15 @@ begin
rd_done_o <= rd_done;
wr_done_o <= wr_done;
cmp_i2c_slave_core: i2c_slave_core
cmp_bridge: bridge
generic map
(
g_wb_clk_period => 8 ns
)
port map
(
clk_i => wb_clk_i,
rst_i => wb_rst_i,
clk_i => clk_i,
rst_i => rst_i,
sda_en_o => sda_en_o,
sda_i => sda_i,
......@@ -118,7 +188,7 @@ begin
wr_done_o => wr_done
);
cmp_i2c_regs: i2c_regs
cmp_bridge_regs: bridge_regs
port map
(
pf_wb_addr_i => pf_wb_addr,
......@@ -126,8 +196,8 @@ begin
rd_done_i => rd_done,
wr_done_i => wr_done,
wb_rst_i => wb_rst_i,
wb_clk_i => wb_clk_i,
wb_rst_i => rst_i,
wb_clk_i => clk_i,
wb_master_we_o => wb_master_we_o,
wb_master_stb_o => wb_master_stb_o,
......@@ -151,28 +221,11 @@ begin
wb_slave_rty_o => wb_slave_rty_o,
wb_slave_err_o => wb_slave_err_o,
CTR0_o => ctr0,
LT_i => lt,
DRXA_i => drxa,
DRXB_i => drxb,
ctr0_o => ctr0,
lt_i => lt,
drxa_i => drxa,
drxb_i => drxb,
i2c_addr_i => i2c_addr_i
);
rst_i2c <= reset_extender(2**c_RST_EXTENSOR - 1);
--! A shift with reset, consumes just a few SLICEX in Spartan6.
p_rst_extender : process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
reset_extender <= (others => '1');
else
reset_extender(0) <= '0';
for i in 1 to 2**c_RST_EXTENSOR -1 loop
reset_extender(i) <= reset_extender(i-1);
end loop;
end if;
end if;
end process;
end Behavioral;
end behav;
hdl/i2c_to_wb_bridge/syn/Makefile 0 → 100644
View file @ 9a04b242
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := conv_ttl_blo_v2.xise
ISE_CRAP := *.b conv_ttl_blo_v2_summary.html *.tcl conv_ttl_blo_v2.bld conv_ttl_blo_v2.cmd_log *.drc conv_ttl_blo_v2.lso *.ncd conv_ttl_blo_v2.ngc conv_ttl_blo_v2.ngd conv_ttl_blo_v2.ngr conv_ttl_blo_v2.pad conv_ttl_blo_v2.par conv_ttl_blo_v2.pcf conv_ttl_blo_v2.prj conv_ttl_blo_v2.ptwx conv_ttl_blo_v2.stx conv_ttl_blo_v2.syr conv_ttl_blo_v2.twr conv_ttl_blo_v2.twx conv_ttl_blo_v2.gise conv_ttl_blo_v2.unroutes conv_ttl_blo_v2.ut conv_ttl_blo_v2.xpi conv_ttl_blo_v2.xst conv_ttl_blo_v2_bitgen.xwbt conv_ttl_blo_v2_envsettings.html conv_ttl_blo_v2_guide.ncd conv_ttl_blo_v2_map.map conv_ttl_blo_v2_map.mrp conv_ttl_blo_v2_map.ncd conv_ttl_blo_v2_map.ngm conv_ttl_blo_v2_map.xrpt conv_ttl_blo_v2_ngdbuild.xrpt conv_ttl_blo_v2_pad.csv conv_ttl_blo_v2_pad.txt conv_ttl_blo_v2_par.xrpt conv_ttl_blo_v2_summary.xml conv_ttl_blo_v2_usage.xml conv_ttl_blo_v2_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=conv_ttl_blo_v2
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../top/conv_ttl_blo_v2.ucf \
../top/conv_ttl_blo_v2.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../rtl/i2c_slave_pkg.vhd \
../rtl/i2c_debounce.vhd \
../rtl/i2c_bit.vhd \
../rtl/bridge_regs.vhd \
../rtl/bridge.vhd \
../rtl/i2c_to_wb_bridge.vhd \
../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd \
../../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd \
../../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../../../ip_cores/general-cores/modules/common/gc_clk_div.vhd \
../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
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../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
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../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
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../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
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../../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
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../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
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../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
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../../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
run.tcl \
conv_ttl_blo_v2.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
hdl/i2c_to_wb_bridge/syn/Manifest.py 0 → 100644
View file @ 9a04b242
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo_v2"
syn_project = "conv_ttl_blo_v2.xise"
modules = {
"local" : [
"../top"
]
}
hdl/i2c_to_wb_bridge/syn/conv_ttl_blo_v2.gise 0 → 100644
View file @ 9a04b242
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<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1363022181" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1363022163">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bgn"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bit"/>
<outfile xil_pn:name="conv_ttl_blo_v2.drc"/>
<outfile xil_pn:name="conv_ttl_blo_v2.ut"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1363022182" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1363022181">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impact.cmd"/>
<outfile xil_pn:name="_impact.log"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1363022163" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1363022156">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.twr"/>
<outfile xil_pn:name="conv_ttl_blo_v2.twx"/>
</transform>
</transforms>
</generated_project>
hdl/i2c_slave_wb_master/project/project.xise → hdl/i2c_to_wb_bridge/syn/conv_ttl_blo_v2.xise
View file @ 9a04b242
......@@ -12,86 +12,14 @@
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../rtl/i2c_bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../rtl/i2c_debounce.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../rtl/i2c_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../rtl/i2c_slave_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../rtl/i2c_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../test/i2c_slave_top_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/ctdah_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/FIFO_dispatcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/FIFO_stack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_clk_divider.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_ff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../ctdah_lib/test/wishbone_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../test/i2c_master_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../test/i2c_tb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../ctdah_lib/test/wishbone_driver_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../test/i2c_bit_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="18"/>
</file>
</files>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -105,7 +33,7 @@
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -113,7 +41,6 @@
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
......@@ -124,15 +51,8 @@
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -144,12 +64,8 @@
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="waveform/i2c_slave_top_wv.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
......@@ -164,9 +80,9 @@
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -185,9 +101,9 @@
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -202,12 +118,10 @@
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -215,20 +129,18 @@
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|i2c_slave_top|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../rtl/i2c_slave_top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/i2c_slave_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|conv_ttl_blo_v2|behav" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../top/conv_ttl_blo_v2.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/conv_ttl_blo_v2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
......@@ -242,13 +154,7 @@
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
......@@ -256,8 +162,6 @@
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
......@@ -266,23 +170,16 @@
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -295,13 +192,10 @@
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="i2c_slave_top" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="conv_ttl_blo_v2" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -312,23 +206,20 @@
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="i2c_slave_top_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="i2c_slave_top_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="i2c_slave_top_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="i2c_slave_top_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="conv_ttl_blo_v2_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="conv_ttl_blo_v2_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="conv_ttl_blo_v2_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="conv_ttl_blo_v2_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......@@ -344,7 +235,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="i2c_slave_top" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -358,7 +249,6 @@
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -366,8 +256,7 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/i2c_slave_top_tb/uut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.i2c_slave_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -377,32 +266,23 @@
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.i2c_slave_top" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
......@@ -410,13 +290,7 @@
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -425,12 +299,11 @@
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -441,50 +314,103 @@
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Waveform Database Filename Behavioral" xil_pn:value="" xil_pn:valueState="non-default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="impact.ipf" xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|i2c_slave_top_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="project" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="conv_ttl_blo_v2" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-02-08T12:42:09" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1545AC9C48EF31058C451965AD869DBB" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-11T14:36:38" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A9429981388E98626D5BFE9AED5E1A83" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<files>
<file xil_pn:name="../top/conv_ttl_blo_v2.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../rtl/i2c_debounce.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../rtl/i2c_bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../rtl/bridge_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../rtl/bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../rtl/i2c_to_wb_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
</project>
hdl/i2c_to_wb_bridge/syn/run.tcl 0 → 100644
View file @ 9a04b242
project open conv_ttl_blo_v2.xise
process run {Generate Programming File} -force rerun_all
hdl/i2c_to_wb_bridge/top/Manifest.py 0 → 100644
View file @ 9a04b242
files = [
"conv_ttl_blo_v2.ucf",
"conv_ttl_blo_v2.vhd"
]
modules = {
"local" : [
"../../../../ip_cores/general-cores",
"../../reset_gen",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../rtl",
]
}
hdl/i2c_to_wb_bridge/top/conv_ttl_blo_v2.ucf 0 → 100644
View file @ 9a04b242
##---------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##----------------------------------------
#NET "RST" LOC = N20;
#NET "RST" IOSTANDARD = LVTTL;
#NET "FPGA_SYSRESET_N" LOC = L20;
NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = LVTTL;
#NET "CLK20_VCXO" LOC = E16;
#TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50 %;
NET "FPGA_CLK_P" LOC = H12;
NET "FPGA_CLK_N" LOC = G11;
##======================================
##-- FRONT PANEL TTLs
##======================================
##-------------------
##-- LEDs
##-------------------
NET "LED_CTRL0" LOC = M18;
NET "LED_CTRL0" IOSTANDARD = LVTTL;
NET "LED_CTRL0_OEN" LOC = T20;
NET "LED_CTRL0_OEN" IOSTANDARD = LVTTL;
NET "LED_CTRL1" LOC = M17;
NET "LED_CTRL1" IOSTANDARD = LVTTL;
NET "LED_CTRL1_OEN" LOC = U19;
NET "LED_CTRL1_OEN" IOSTANDARD = LVTTL;
NET "LED_MULTICAST_2_0" LOC = P16;
NET "LED_MULTICAST_2_0" IOSTANDARD = LVTTL;
NET "LED_MULTICAST_3_1" LOC = P17;
NET "LED_MULTICAST_3_1" IOSTANDARD = LVTTL;
NET "LED_WR_GMT_TTL_TTLN" LOC = N16;
NET "LED_WR_GMT_TTL_TTLN" IOSTANDARD = LVTTL;
NET "LED_WR_LINK_SYSERROR" LOC = R15;
NET "LED_WR_LINK_SYSERROR" IOSTANDARD = LVTTL;
NET "LED_WR_OK_SYSPW" LOC = R16;
NET "LED_WR_OK_SYSPW" IOSTANDARD = LVTTL;
NET "LED_WR_OWNADDR_I2C" LOC = N15;
NET "LED_WR_OWNADDR_I2C" IOSTANDARD = LVTTL;
##-------------------
##-- Front channel LEDs
##-------------------
#NET "PULSE_FRONT_LED_N[1]" LOC = H5;
#NET "PULSE_FRONT_LED_N[1]" IOSTANDARD = LVCMOS33;
#NET "PULSE_FRONT_LED_N[1]" DRIVE = 4;
#NET "PULSE_FRONT_LED_N[1]" SLEW = QUIETIO;
#NET "PULSE_FRONT_LED_N[2]" LOC = J6;
#NET "PULSE_FRONT_LED_N[2]" IOSTANDARD = LVCMOS33;
#NET "PULSE_FRONT_LED_N[2]" DRIVE = 4;
#NET "PULSE_FRONT_LED_N[2]" SLEW = QUIETIO;
#NET "PULSE_FRONT_LED_N[3]" LOC = K6;
#NET "PULSE_FRONT_LED_N[3]" IOSTANDARD = LVCMOS33;
#NET "PULSE_FRONT_LED_N[3]" DRIVE = 4;
#NET "PULSE_FRONT_LED_N[3]" SLEW = QUIETIO;
#NET "PULSE_FRONT_LED_N[4]" LOC = K5;
#NET "PULSE_FRONT_LED_N[4]" IOSTANDARD = LVCMOS33;
#NET "PULSE_FRONT_LED_N[4]" DRIVE = 4;
#NET "PULSE_FRONT_LED_N[4]" SLEW = QUIETIO;
#NET "PULSE_FRONT_LED_N[5]" LOC = M7;
#NET "PULSE_FRONT_LED_N[5]" IOSTANDARD = LVCMOS33;
#NET "PULSE_FRONT_LED_N[5]" DRIVE = 4;
#NET "PULSE_FRONT_LED_N[5]" SLEW = QUIETIO;
#NET "PULSE_FRONT_LED_N[6]" LOC = M6;
#NET "PULSE_FRONT_LED_N[6]" IOSTANDARD = LVCMOS33;
#NET "PULSE_FRONT_LED_N[6]" DRIVE = 4;
#NET "PULSE_FRONT_LED_N[6]" SLEW = QUIETIO;
##-------------------
##-- Rear LEDs
##-------------------
#NET "PULSE_REAR_LED_N[1]" LOC = AB17;
#NET "PULSE_REAR_LED_N[1]" IOSTANDARD = LVCMOS33;
#NET "PULSE_REAR_LED_N[1]" DRIVE = 4;
#NET "PULSE_REAR_LED_N[1]" SLEW = QUIETIO;
#NET "PULSE_REAR_LED_N[2]" LOC = AB19;
#NET "PULSE_REAR_LED_N[2]" IOSTANDARD = LVCMOS33;
#NET "PULSE_REAR_LED_N[2]" DRIVE = 4;
#NET "PULSE_REAR_LED_N[2]" SLEW = QUIETIO;
#NET "PULSE_REAR_LED_N[3]" LOC = AA16;
#NET "PULSE_REAR_LED_N[3]" IOSTANDARD = LVCMOS33;
#NET "PULSE_REAR_LED_N[3]" DRIVE = 4;
#NET "PULSE_REAR_LED_N[3]" SLEW = QUIETIO;
#NET "PULSE_REAR_LED_N[4]" LOC = AA18;
#NET "PULSE_REAR_LED_N[4]" IOSTANDARD = LVCMOS33;
#NET "PULSE_REAR_LED_N[4]" DRIVE = 4;
#NET "PULSE_REAR_LED_N[4]" SLEW = QUIETIO;
#NET "PULSE_REAR_LED_N[5]" LOC = AB16;
#NET "PULSE_REAR_LED_N[5]" IOSTANDARD = LVCMOS33;
#NET "PULSE_REAR_LED_N[5]" DRIVE = 4;
#NET "PULSE_REAR_LED_N[5]" SLEW = QUIETIO;
#NET "PULSE_REAR_LED_N[6]" LOC = AB18;
#NET "PULSE_REAR_LED_N[6]" IOSTANDARD = LVCMOS33;
#NET "PULSE_REAR_LED_N[6]" DRIVE = 4;
#NET "PULSE_REAR_LED_N[6]" SLEW = QUIETIO;
###-------------------
###-- TTL trigger I/O
###-------------------
#NET "FPGA_INPUT_TTL_N[1]" LOC = T2;
#NET "FPGA_INPUT_TTL_N[1]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[2]" LOC = U3;
#NET "FPGA_INPUT_TTL_N[2]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[3]" LOC = V5;
#NET "FPGA_INPUT_TTL_N[3]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[4]" LOC = W4;
#NET "FPGA_INPUT_TTL_N[4]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[5]" LOC = T6;
#NET "FPGA_INPUT_TTL_N[5]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[6]" LOC = T3;
#NET "FPGA_INPUT_TTL_N[6]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[1]" LOC = C1;
#NET "FPGA_OUT_TTL[1]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[2]" LOC = F2;
#NET "FPGA_OUT_TTL[2]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[3]" LOC = F5;
#NET "FPGA_OUT_TTL[3]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[4]" LOC = H4;
#NET "FPGA_OUT_TTL[4]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[5]" LOC = J4;
#NET "FPGA_OUT_TTL[5]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[6]" LOC = H2;
#NET "FPGA_OUT_TTL[6]" IOSTANDARD = LVCMOS33;
##-------------------
##-- Inverted TTL I/O
##--
##-- Schematics name: INV_IN_*
##---- renamed to INV_IN[*]
##-------------------
#NET "INV_IN_N[1]" LOC = V2;
#NET "INV_IN_N[1]" IOSTANDARD = LVCMOS33;
#NET "INV_IN_N[2]" LOC = W3;
#NET "INV_IN_N[2]" IOSTANDARD = LVCMOS33;
#NET "INV_IN_N[3]" LOC = Y2;
#NET "INV_IN_N[3]" IOSTANDARD = LVCMOS33;
#NET "INV_IN_N[4]" LOC = AA2;
#NET "INV_IN_N[4]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[1]" LOC = J3;
#NET "INV_OUT[1]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[2]" LOC = L3;
#NET "INV_OUT[2]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[3]" LOC = M3;
#NET "INV_OUT[3]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[4]" LOC = P2;
#NET "INV_OUT[4]" IOSTANDARD = LVCMOS33;
##======================================
##-- RTM signals
##======================================
##-- Blocking I/O
##
##-- Schematics name: FPGA_BLO_IN_*
##---- renamed to FPGA_BLO_IN[*]
##-------------------
#NET "FPGA_BLO_IN[1]" LOC = Y9;
#NET "FPGA_BLO_IN[1]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[2]" LOC = AA10;
#NET "FPGA_BLO_IN[2]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[3]" LOC = W12;
#NET "FPGA_BLO_IN[3]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[4]" LOC = AA6;
#NET "FPGA_BLO_IN[4]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[5]" LOC = Y7;
#NET "FPGA_BLO_IN[5]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[6]" LOC = AA8;
#NET "FPGA_BLO_IN[6]" IOSTANDARD = LVCMOS33;
#
#NET "FPGA_TRIG_BLO[1]" LOC = W9;
#NET "FPGA_TRIG_BLO[1]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[2]" LOC = T10;
#NET "FPGA_TRIG_BLO[2]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[3]" LOC = V7;
#NET "FPGA_TRIG_BLO[3]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[4]" LOC = U9;
#NET "FPGA_TRIG_BLO[4]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[5]" LOC = T8;
#NET "FPGA_TRIG_BLO[5]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[6]" LOC = R9;
#NET "FPGA_TRIG_BLO[6]" IOSTANDARD = LVCMOS33;
###======================================
###-- VME CONNECTOR SIGNALS
###======================================
###-------------------
###-- I2C lines
###-------------------
NET "SCL_I" LOC = F19;
NET "SCL_I" IOSTANDARD = LVTTL;
NET "SCL_O" LOC = E20;
NET "SCL_O" IOSTANDARD = LVTTL;
NET "SCL_O" DRIVE = 4;
NET "SCL_OE" LOC = H18;
NET "SCL_OE" IOSTANDARD = LVTTL;
NET "SCL_OE" DRIVE = 4;
# NET "SCL_OE" PULLDOWN;
NET "SDA_I" LOC = G20;
NET "SDA_I" IOSTANDARD = LVTTL;
NET "SDA_O" LOC = F20;
NET "SDA_O" IOSTANDARD = LVTTL;
NET "SDA_O" SLEW = FAST;
NET "SDA_O" DRIVE = 4;
# NET "SDA_O" PULLUP;
NET "SDA_OE" LOC = J19;
NET "SDA_OE" IOSTANDARD = LVTTL;
NET "SDA_OE" SLEW = FAST;
NET "SDA_OE" DRIVE = 4;
# NET "SDA_OE" PULLDOWN;
###-------------------
###-- Geographical Address
###-------------------
NET "FPGA_GA[0]" LOC = H20;
NET "FPGA_GA[0]" IOSTANDARD = LVTTL;
NET "FPGA_GA[1]" LOC = J20;
NET "FPGA_GA[1]" IOSTANDARD = LVTTL;
NET "FPGA_GA[2]" LOC = K19;
NET "FPGA_GA[2]" IOSTANDARD = LVTTL;
NET "FPGA_GA[3]" LOC = K20;
NET "FPGA_GA[3]" IOSTANDARD = LVTTL;
NET "FPGA_GA[4]" LOC = L19;
NET "FPGA_GA[4]" IOSTANDARD = LVTTL;
NET "FPGA_GAP" LOC = H19;
NET "FPGA_GAP" IOSTANDARD = LVTTL;
###-------------------
###-- ROM memory
###-------------------
#NET "FPGA_PROM_CCLK" LOC = Y20;
#NET "FPGA_PROM_CCLK" IOSTANDARD = LVTTL;
#NET "FPGA_PROM_CSO_B_N" LOC = AA3;
#NET "FPGA_PROM_CSO_B_N" IOSTANDARD = LVTTL;
#NET "FPGA_PROM_DIN" LOC = AA20;
#NET "FPGA_PROM_DIN" IOSTANDARD = LVTTL;
#NET "FPGA_PROM_MOSI" LOC = AB20;
#NET "FPGA_PROM_MOSI" IOSTANDARD = LVTTL;
#
#
####======================================
####-- WHITE RABBIT
####======================================
####-------------------
####-- Thermo for UID
####-------------------
##NET "THERMOMETER" LOC = B1;
## NET "THERMOMETER" IOSTANDARD = "LVCMOS25";
####-------------------
####-- DACs control
####--
####-- + CMOS 3.3V input
####-------------------
##NET "FPGA_PLLDAC1_DIN" LOC = AB14;
## NET "FPGA_PLLDAC1_DIN" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC1_SCLK" LOC = AA14;
## NET "FPGA_PLLDAC1_SCLK" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC1_SYNC_N" LOC = AB15;
## NET "FPGA_PLLDAC1_SYNC_N" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC2_DIN" LOC = W14;
## NET "FPGA_PLLDAC2_DIN" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC2_SCLK" LOC = Y14;
## NET "FPGA_PLLDAC2_SCLK" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC2_SYNC_N" LOC = W13;
## NET "FPGA_PLLDAC2_SYNC_N" IOSTANDARD = "LVCMOS25";
####-------------------
####-- SFP connection
####-------------------
##NET "FPGA_SFP_LOS" LOC = G3;
## NET "FPGA_SFP_LOS" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_MOD_DEF0" LOC = K8;
## NET "FPGA_SFP_MOD_DEF0" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_RATE_SELECT" LOC = C4;
## NET "FPGA_SFP_RATE_SELECT" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_MOD_DEF1" LOC = G4;
## NET "FPGA_SFP_MOD_DEF1" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_MOD_DEF2" LOC = F3;
## NET "FPGA_SFP_MOD_DEF2" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_TX_DISABLE" LOC = E4;
## NET "FPGA_SFP_TX_DISABLE" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_TX_FAULT" LOC = D2;
## NET "FPGA_SFP_TX_FAULT" IOSTANDARD = "LVCMOS33";
####-------------------
####-- FPGA MGT lines
####-------------------
##NET "FPGAMGTCLK0_P" LOC = A10;
## NET "FPGAMGTCLK0_P" IOSTANDARD = "LVDS_12";
##NET "FPGAMGTCLK0_N" LOC = B10;
## NET "FPGAMGTCLK0_N" IOSTANDARD = "LVDS_12";
##NET "MGTSFPRX0_P" LOC = D7;
## NET "MGTSFPRX0_P" IOSTANDARD = "LVDS_12";
##NET "MGTSFPRX0_N" LOC = C7;
## NET "MGTSFPRX0_N" IOSTANDARD = "LVDS_12";
##NET "MGTSFPTX0_P" LOC = B6;
## NET "MGTSFPTX0_P" IOSTANDARD = "LVDS_12";
##NET "MGTSFPTX0_N" LOC = A6;
## NET "MGTSFPTX0_N" IOSTANDARD = "LVDS_12";
#
#
###======================================
###-- ADDITIONAL PINS
###======================================
NET "FPGA_OE" LOC = R3;
NET "FPGA_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_OE" DRIVE = 4;
NET "FPGA_OE" SLEW = QUIETIO;
NET "FPGA_BLO_OE" LOC = P5;
NET "FPGA_BLO_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_BLO_OE" DRIVE = 4;
NET "FPGA_BLO_OE" SLEW = QUIETIO;
NET "FPGA_TRIG_TTL_OE" LOC = N3;
NET "FPGA_TRIG_TTL_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_TRIG_TTL_OE" DRIVE = 4;
NET "FPGA_TRIG_TTL_OE" SLEW = QUIETIO;
NET "FPGA_INV_OE" LOC = P6;
NET "FPGA_INV_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_INV_OE" DRIVE = 4;
NET "FPGA_INV_OE" SLEW = QUIETIO;
###-------------------
###-- Configuration Switches
###
###-- Schematics name EXTRA_SWITCH_*
###---- renamed to EXTRA_SWITCH[*]
###-------------------
#NET "EXTRA_SWITCH[1]" LOC = F22;
#NET "EXTRA_SWITCH[1]" IOSTANDARD = LVCMOS33;
## NET "EXTRA_SWITCH[2]" LOC = G22;
## NET "EXTRA_SWITCH[2]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[3]" LOC = H21;
## NET "EXTRA_SWITCH[3]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[4]" LOC = H22;
## NET "EXTRA_SWITCH[4]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[5]" LOC = J22;
## NET "EXTRA_SWITCH[5]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[6]" LOC = K21;
## NET "EXTRA_SWITCH[6]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[7]" LOC = K22;
## NET "EXTRA_SWITCH[7]" IOSTANDARD = "LVCMOS33";
NET "LEVEL" LOC = L22;
NET "LEVEL" IOSTANDARD = LVCMOS33;
##-------------------
##-- Motherboard and piggyback IDs
##-------------------
NET "FPGA_RTMM_N[0]" LOC = V21;
NET "FPGA_RTMM_N[0]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[1]" LOC = V22;
NET "FPGA_RTMM_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[2]" LOC = U22;
NET "FPGA_RTMM_N[2]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[0]" LOC = W22;
NET "FPGA_RTMP_N[0]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[1]" LOC = Y22;
NET "FPGA_RTMP_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[2]" LOC = Y21;
NET "FPGA_RTMP_N[2]" IOSTANDARD = LVCMOS33;
####-------------------
####-- General purpose
####-------------------
## NET "FPGA_HEADER_OUT_N[1]" LOC = F15;
## NET "FPGA_HEADER_OUT_N[1]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[2]" LOC = F16;
## NET "FPGA_HEADER_OUT_N[2]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[3]" LOC = F17;
## NET "FPGA_HEADER_OUT_N[3]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[4]" LOC = F14;
## NET "FPGA_HEADER_OUT_N[4]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[5]" LOC = H14;
## NET "FPGA_HEADER_OUT_N[5]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[6]" LOC = H13;
## NET "FPGA_HEADER_OUT_N[6]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[1]" LOC = A17;
## NET "FPGA_HEADER_IN_N[1]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[2]" LOC = A18;
## NET "FPGA_HEADER_IN_N[2]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[3]" LOC = B18;
## NET "FPGA_HEADER_IN_N[3]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[4]" LOC = A19;
## NET "FPGA_HEADER_IN_N[4]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[5]" LOC = A20;
## NET "FPGA_HEADER_IN_N[5]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[6]" LOC = B20;
## NET "FPGA_HEADER_IN_N[6]" IOSTANDARD = "LVCMOS33";
hdl/i2c_to_wb_bridge/top/conv_ttl_blo_v2.vhd 0 → 100644
View file @ 9a04b242
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- http://www.ohwr.org/projects/conv-trig-blo
--------------------------------------------------------------------------------
--
-- unit name: conv_ttl_blo_v2.vhd
--
-- author: Theodor-Adrian Stana (t.stana@cern.ch)
-- Carlos Gil Soriano (gilsoriano@gmail.com)
--
-- version: 1.0
--
-- description: Top entity of CONV-TTL-BLO V1
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library IEEE;
library unisim;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VCOMPONENTS.ALL;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
entity conv_ttl_blo_v2 is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4
);
port
(
-- RST : in std_logic;
-- CLK20_VCXO : in std_logic;
FPGA_CLK_P : in std_logic; --Using the 125MHz clock
FPGA_CLK_N : in std_logic;
-- LEDs
LED_CTRL0 : out std_logic;
LED_CTRL0_OEN : out std_logic;
LED_CTRL1 : out std_logic;
LED_CTRL1_OEN : out std_logic;
LED_MULTICAST_2_0 : out std_logic;
LED_MULTICAST_3_1 : out std_logic;
LED_WR_GMT_TTL_TTLN : out std_logic;
LED_WR_LINK_SYSERROR : out std_logic;
LED_WR_OK_SYSPW : out std_logic;
LED_WR_OWNADDR_I2C : out std_logic;
-- I/Os for pulses
-- PULSE_FRONT_LED_N : out std_logic_vector(g_nr_ttl_chan downto 1);
-- PULSE_REAR_LED_N : out std_logic_vector(g_nr_ttl_chan downto 1);
-- FPGA_INPUT_TTL_N : in std_logic_vector(g_nr_ttl_chan downto 1);
-- FPGA_OUT_TTL : out std_logic_vector(g_nr_ttl_chan downto 1);
-- FPGA_BLO_IN : in std_logic_vector(g_nr_ttl_chan downto 1);
-- FPGA_TRIG_BLO : out std_logic_vector(g_nr_ttl_chan downto 1);
-- INV_IN_N : in std_logic_vector(g_nr_inv_chan downto 1);
-- INV_OUT : out std_logic_vector(g_nr_inv_chan downto 1);
-- Lines for the i2c_slave
SCL_I : in std_logic;
SCL_O : out std_logic;
SCL_OE : out std_logic;
SDA_I : in std_logic;
SDA_O : out std_logic;
SDA_OE : out std_logic;
FPGA_GA : in std_logic_vector(4 downto 0);
FPGA_GAP : in std_logic;
--
-- -- Pins of the SPI interface to write into the Flash memory
-- FPGA_PROM_CCLK : out std_logic;
-- FPGA_PROM_CSO_B_N : out std_logic;
-- FPGA_PROM_DIN : in std_logic;
-- FPGA_PROM_MOSI : out std_logic;
--
FPGA_OE : out std_logic;
FPGA_BLO_OE : out std_logic;
FPGA_TRIG_TTL_OE : out std_logic;
FPGA_INV_OE : out std_logic;
-- TTL/INV_TTL_N
LEVEL : in std_logic;
-- EXTRA_SWITCH : in std_logic_vector(7 downto 1);
-- It allows power sequencing of the
-- 24V rail after a security given delay
MR_N : out std_logic;
-- RTM identifiers, should match with the expected values
-- TODO: add matching
FPGA_RTMM_N : in std_logic_vector(2 downto 0);
FPGA_RTMP_N : in std_logic_vector(2 downto 0)
);
end conv_ttl_blo_v2;
architecture behav of conv_ttl_blo_v2 is
--============================================================================
-- Constant declarations
--============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : NATURAL := 1;
constant c_nr_slaves : NATURAL := 1;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word aligned
-----------------------------------------
-- M25P32 [0200-03FF]
-- MULTIBOOT [0080-00CF]
-- I2C_SLAVE [0040-007F]
-- SR [0000-003F]
-----------------------------------------
-- base address definitions
constant c_addr_i2c_bridge : t_wishbone_address := X"00000040";
constant c_addr_multiboot : t_wishbone_address := X"00000080";
constant c_addr_m25p32 : t_wishbone_address := X"00000200";
-- address mask definitions
-- 64 words per page: 6 + 1 bits
constant c_mask_i2c_bridge : t_wishbone_address := X"FFFFFFC0";
constant c_mask_multiboot : t_wishbone_address := X"FFFFFFC0";
constant c_mask_m25p32 : t_wishbone_address := X"FFFFFE00";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves - 1 downto 0)
:= (--c_addr_m25p32,
--c_addr_multiboot,
(others => c_addr_i2c_bridge)
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves - 1 downto 0)
:= (--c_mask_m25p32,
-- c_mask_multiboot,
(others => c_mask_i2c_bridge)
);
--============================================================================
-- Component declarations
--============================================================================
-- Reset generator component
-- (use: global reset generation, output reset generation)
component reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 5_000_000
);
port
(
clk_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
-- RTM detector component
-- (use: detect the presence of an RTM/P module)
component rtm_detector is
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end component rtm_detector;
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
component i2c_to_wb_bridge is
port
(
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
clk_i : in std_logic;
rst_i : in std_logic;
wb_master_stb_o : out std_logic;
wb_master_cyc_o : out std_logic;
wb_master_sel_o : out std_logic_vector(3 downto 0);
wb_master_we_o : out std_logic;
wb_master_dat_i : in std_logic_vector(31 downto 0);
wb_master_dat_o : out std_logic_vector(31 downto 0);
wb_master_adr_o : out std_logic_vector(15 downto 0);
wb_master_ack_i : in std_logic;
wb_master_rty_i : in std_logic;
wb_master_err_i : in std_logic;
wb_slave_stb_i : in std_logic;
wb_slave_cyc_i : in std_logic;
wb_slave_sel_i : in std_logic_vector(3 downto 0);
wb_slave_we_i : in std_logic;
wb_slave_dat_i : in std_logic_vector(31 downto 0);
wb_slave_dat_o : out std_logic_vector(31 downto 0);
wb_slave_adr_i : in std_logic_vector(3 downto 0);
wb_slave_ack_o : out std_logic;
wb_slave_rty_o : out std_logic;
wb_slave_err_o : out std_logic;
pf_wb_addr_o : out std_logic;
rd_done_o : out std_logic;
wr_done_o : out std_logic;
i2c_addr_i : in std_logic_vector(6 downto 0)
);
end component i2c_to_wb_bridge;
--============================================================================
-- Signal declarations
--============================================================================
-- Clock signals
signal clk_125 : std_logic;
-- Reset signals
signal rst_n, rst : std_logic;
-- RTM detection signals
signal rtmm, rtmp : std_logic_vector(2 downto 0);
signal rtmm_ok, rtmp_ok : std_logic;
-- Signals for pulse generation triggers
signal trig : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_inv : std_logic_vector(g_nr_inv_chan downto 1);
signal trig_ttl, trig_blo : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for blocking and TTL pulse outputs
signal pulse_outputs : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for inverted-TTL pulse outputs
signal inv_outputs : std_logic_vector(g_nr_inv_chan downto 1);
-- Pulse status LED signals
signal front_led_en : std_logic_vector(g_nr_ttl_chan downto 1);
signal rear_led_en : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_leds : std_logic_vector(g_nr_ttl_chan downto 1);
-- Output enable signals
signal oe, ttl_oe, blo_oe, inv_oe : std_logic;
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array (c_nr_slaves - 1 downto 0);
-- I2C bridge signals
signal i2c_rd_done, i2c_wr_done : std_logic;
signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
begin
--============================================================================
-- Generate 125 MHz global signal from differential lines
--============================================================================
cmp_125_diff_buf: IBUFGDS
generic map
(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE
)
port map
(
I => FPGA_CLK_P,
IB => FPGA_CLK_N,
O => clk_125
);
--============================================================================
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for 96ms power-on reset
cmp_reset_gen: reset_gen
generic map
(
-- Reset time: 12 * 8ns * (10**6) = 96 ms
g_reset_time => 12*(10**6)
)
port map
(
clk_i => clk_125,
rst_n_o => rst_n
);
rst <= not rst_n;
MR_N <= rst_n;
--============================================================================
-- Output enable logic
--============================================================================
-- The general output enable is set first and the blocking, TTL
-- and INV output enable signals are set one clock cycle later.
p_oe: process(clk_125)
begin
if rising_edge(clk_125) then
if (rst_n = '0') then
oe <= '0';
blo_oe <= '0';
ttl_oe <= '0';
inv_oe <= '0';
else
oe <= '0';
if (oe = '1') then
blo_oe <= '1';
ttl_oe <= '1';
inv_oe <= '1';
end if;
end if;
end if;
end process p_oe;
FPGA_OE <= oe;
FPGA_BLO_OE <= blo_oe;
FPGA_TRIG_TTL_OE <= ttl_oe;
FPGA_INV_OE <= inv_oe;
--============================================================================
-- I2C bridge logic
--============================================================================
i2c_addr <= "10" & FPGA_GA;
cmp_bridge: i2c_to_wb_bridge
port map
(
sda_en_o => SDA_OE,
sda_i => SDA_I,
sda_o => SDA_O,
scl_en_o => SCL_OE,
scl_i => SCL_I,
scl_o => SCL_O,
clk_i => clk_125,
rst_i => rst,
wb_master_stb_o => xbar_slave_in(0).stb,
wb_master_cyc_o => xbar_slave_in(0).cyc,
wb_master_sel_o => xbar_slave_in(0).sel,
wb_master_we_o => xbar_slave_in(0).we,
wb_master_dat_i => xbar_slave_out(0).dat,
wb_master_dat_o => xbar_slave_in(0).dat,
wb_master_adr_o => xbar_slave_in(0).adr(15 downto 0),
wb_master_ack_i => xbar_slave_out(0).ack,
wb_master_rty_i => xbar_slave_out(0).rty,
wb_master_err_i => xbar_slave_out(0).err,
wb_slave_stb_i => xbar_master_out(0).stb,
wb_slave_cyc_i => xbar_master_out(0).cyc,
wb_slave_sel_i => xbar_master_out(0).sel,
wb_slave_we_i => xbar_master_out(0).we,
wb_slave_dat_i => xbar_master_out(0).dat,
wb_slave_dat_o => xbar_master_in(0).dat,
wb_slave_adr_i => xbar_master_out(0).adr(5 downto 2),
wb_slave_ack_o => xbar_master_in(0).ack,
wb_slave_rty_o => xbar_master_in(0).rty,
wb_slave_err_o => xbar_master_in(0).err,
pf_wb_addr_o => open,
rd_done_o => i2c_rd_done,
wr_done_o => i2c_wr_done,
i2c_addr_i => i2c_addr
);
xbar_slave_in(0).adr(31 downto 16) <= (others => '0');
-- Process to set the I2C_UP signal for display on the front panel
-- of the front module. The I2C_UP signal is permanently set once an
-- I2C transfer has successfully completed, as signaled by the RD_DONE
-- and WR_DONE outputs of the I2C slave.
p_i2c_up: process (clk_125) is
begin
if rising_edge(clk_125) then
if (rst_n = '0') then
i2c_up <= '0';
elsif (i2c_rd_done = '1') or (i2c_wr_done = '1') then
i2c_up <= '1';
end if;
end if;
end process p_i2c_up;
--============================================================================
-- Instantiation and connection of a Wishbone crossbar module
--============================================================================
xbar_master_in(0).stall <= '0';
xbar_master_in(0).int <= '0';
cmp_wb_crossbar: xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
-- Address of the slaves connected
-- It should be noted that the default address length is 32
-- In our project only 16 bits are addressable
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk_125,
rst_n_i => rst_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit.
-- WR address
bicolor_led_state( 1 downto 0) <= c_LED_OFF;
-- WR GMT
bicolor_led_state( 3 downto 2) <= c_LED_OFF;
-- WR link
bicolor_led_state( 5 downto 4) <= c_LED_OFF;
-- WR OK
bicolor_led_state( 7 downto 6) <= c_LED_OFF;
-- MULTICAST 0
bicolor_led_state( 9 downto 8) <= c_LED_OFF;
-- MULTICAST 1
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C valid
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (i2c_up = '1') else
c_LED_RED;
-- State of TTL/TTL_N switch
bicolor_led_state(15 downto 14) <= c_LED_GREEN when (LEVEL = '1') else
c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_RED when (rtmm_ok = '0') and (rtmp_ok = '0') else
c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
cmp_bicolor_led_ctrl: bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
g_NB_LINE => 2,
g_clk_freq => 125000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk_125,
rst_n_i => rst_n,
led_intensity_i => "0011111",
led_state_i => bicolor_led_state,
column_o(0) => LED_WR_OWNADDR_I2C,
column_o(1) => LED_WR_GMT_TTL_TTLN,
column_o(2) => LED_WR_LINK_SYSERROR,
column_o(3) => LED_WR_OK_SYSPW,
column_o(4) => LED_MULTICAST_2_0,
column_o(5) => LED_MULTICAST_3_1,
line_o(0) => LED_CTRL0,
line_o(1) => LED_CTRL1,
line_oen_o(0) => LED_CTRL0_OEN,
line_oen_o(1) => LED_CTRL1_OEN
);
--============================================================================
-- RTM detection logic
--============================================================================
rtmm <= not FPGA_RTMM_N;
rtmp <= not FPGA_RTMP_N;
cmp_rtm_detector: rtm_detector
port map
(
rtmm_i => rtmm,
rtmp_i => rtmp,
rtmm_ok_o => rtmm_ok,
rtmp_ok_o => rtmp_ok
);
end behav;
hdl/release/syn/Makefile
View file @ 9a04b242
......@@ -36,10 +36,10 @@ endif
CWD := $(shell pwd)
FILES := ../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../top/conv_ttl_blo_v2.ucf \
FILES := ../top/conv_ttl_blo_v2.ucf \
../top/conv_ttl_blo_v2.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../pulse_generator/rtl/pulse_generator.vhd \
../../rtm_detector/rtl/rtm_detector.vhd \
......
hdl/release/syn/Manifest.py
View file @ 9a04b242
......@@ -8,10 +8,6 @@ syn_project = "conv_ttl_blo_v2.xise"
modules = {
"local" : [
"../../reset_gen",
"../../pulse_generator",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../top"
"../top"
]
}
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ 9a04b242
......@@ -22,6 +22,8 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="conv_ttl_blo_v2.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_CMD" xil_pn:name="_impact.cmd"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impact.log"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impactbatch.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -53,7 +55,6 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo_v2.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="conv_ttl_blo_v2.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo_v2.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_v2_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_v2_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_v2_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_v2_map.mrp" xil_pn:subbranch="Map"/>
......@@ -76,35 +77,34 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1362648727">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1362648727">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1362648727">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1362648727">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1362648727">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1362648727">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1362648727">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363002038" xil_pn:in_ck="-4590833482063591864" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1363002026">
<transform xil_pn:end_ts="1363009896" xil_pn:in_ck="-1985142147321250132" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
......@@ -121,11 +121,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1362651935" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1362651935">
<transform xil_pn:end_ts="1363009896" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1363009896">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363002044" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1363002038">
<transform xil_pn:end_ts="1363009903" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1363009896">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -134,7 +134,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1363002072" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1363002044">
<transform xil_pn:end_ts="1363009934" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1363009903">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
......@@ -149,7 +149,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1363002100" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1363002072">
<transform xil_pn:end_ts="1363009963" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1363009934">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -163,7 +163,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1363002118" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1363002100">
<transform xil_pn:end_ts="1363009981" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1363009963">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -174,25 +174,17 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1362751327" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="-4173336264699367391" xil_pn:start_ts="1362751327">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1363002119" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1363002118">
<transform xil_pn:end_ts="1363009981" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1363009981">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impact.cmd"/>
<outfile xil_pn:name="_impact.log"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1363002100" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1363002093">
<transform xil_pn:end_ts="1363009963" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1363009955">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/syn/conv_ttl_blo_v2.xise
View file @ 9a04b242
......@@ -342,15 +342,15 @@
<file xil_pn:name="../top/conv_ttl_blo_v2.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
......@@ -360,10 +360,6 @@
<file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../old_rep_test/rtl/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<bindings/>
......
hdl/release/top/Manifest.py
View file @ 9a04b242
......@@ -2,3 +2,12 @@ files = [
"conv_ttl_blo_v2.ucf",
"conv_ttl_blo_v2.vhd"
]
modules = {
"local" : [
"../../reset_gen",
"../../pulse_generator",
"../../rtm_detector",
"../../bicolor_led_ctrl",
]
}
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