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Commit 9a04b242 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Starting rewrite of i2c_bit FSM

parent 6924ae51
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hdl/i2c_slave_wb_master/.gitignore deleted 100644 → 0
View file @ 6924ae51
#Ignore LaTeX trash
doc/.*
doc/.*_*
doc/*.*
doc/.*.*.swp
doc/.*.*.swp
doc/Figures/*.eps
!doc/*.tex
!doc/*.pdf
#Ignore autotrash from ISE
project/*
project/*/
!project/project.gise
!project/project.xise
!project/waveform/
#Ignore swap files at rtl/ and test/ folders
rtl/.*.*.swo
rtl/.*.*.swp
test/.*.*.swo
test/.*.*.swp
hdl/i2c_slave_wb_master/project/project.gise deleted 100644 → 0
View file @ 6924ae51
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="project.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="i2c_slave_top_tb.fdo"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1360229226" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1360229226">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1360229226" xil_pn:in_ck="1742451764713501079" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1360229226">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/FIFO_stack.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_counter.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_ff.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/test/wishbone_driver.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/test/wishbone_driver_pkg.vhd"/>
<outfile xil_pn:name="../rtl/i2c_bit.vhd"/>
<outfile xil_pn:name="../rtl/i2c_debounce.vhd"/>
<outfile xil_pn:name="../rtl/i2c_regs.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_core.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_pkg.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_top.vhd"/>
<outfile xil_pn:name="../test/i2c_bit_tb.vhd"/>
<outfile xil_pn:name="../test/i2c_master_driver.vhd"/>
<outfile xil_pn:name="../test/i2c_slave_top_tb.vhd"/>
<outfile xil_pn:name="../test/i2c_tb_pkg.vhd"/>
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<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1360229226" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="5962221678014933934" xil_pn:start_ts="1360229226">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1360229226" xil_pn:in_ck="1742451764713501079" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1360229226">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/FIFO_stack.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_counter.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/rtl/gc_ff.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/test/wishbone_driver.vhd"/>
<outfile xil_pn:name="../../ctdah_lib/test/wishbone_driver_pkg.vhd"/>
<outfile xil_pn:name="../rtl/i2c_bit.vhd"/>
<outfile xil_pn:name="../rtl/i2c_debounce.vhd"/>
<outfile xil_pn:name="../rtl/i2c_regs.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_core.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_pkg.vhd"/>
<outfile xil_pn:name="../rtl/i2c_slave_top.vhd"/>
<outfile xil_pn:name="../test/i2c_bit_tb.vhd"/>
<outfile xil_pn:name="../test/i2c_master_driver.vhd"/>
<outfile xil_pn:name="../test/i2c_slave_top_tb.vhd"/>
<outfile xil_pn:name="../test/i2c_tb_pkg.vhd"/>
</transform>
<transform xil_pn:end_ts="1360229228" xil_pn:in_ck="1742451764713501079" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="-3286620494048968334" xil_pn:start_ts="1360229226">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="i2c_slave_top_tb.fdo"/>
</transform>
</transforms>
</generated_project>
hdl/i2c_slave_wb_master/project/waveform/wave.do deleted 100644 → 0
View file @ 6924ae51
This diff is collapsed.
hdl/i2c_to_wb_bridge/rtl/Manifest.py 0 → 100644
View file @ 9a04b242
files = [
"i2c_slave_pkg.vhd",
"i2c_debounce.vhd",
"i2c_bit.vhd",
"bridge_regs.vhd",
"bridge.vhd",
"i2c_to_wb_bridge.vhd"
]
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd → hdl/i2c_to_wb_bridge/rtl/bridge.vhd
View file @ 9a04b242
......@@ -5,7 +5,7 @@
--
-- Create Date: 11:29:56 10/25/2011
-- Design Name: I2C Slave to Wishbone bridge
-- Module Name: i2c_slave_core - Behavioral
-- Module Name: bridge - behav
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
......@@ -56,9 +56,8 @@ library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
entity i2c_slave_core is
entity bridge is
generic
(
g_WB_CLK_PERIOD : time := 50 ns
......@@ -76,10 +75,10 @@ entity i2c_slave_core is
scl_o : out std_logic;
-- Registers
CTR0_i : in std_logic_vector (r_CTR0'a_length - 1 downto 0);
LT_o : out std_logic_vector (r_LT'a_length - 1 downto 0);
DRXA_o : out std_logic_vector (r_DRX'a_length - 1 downto 0);
DRXB_o : out std_logic_vector (r_DRX'a_length - 1 downto 0);
ctr0_i : in std_logic_vector(31 downto 0);
lt_o : out std_logic_vector(31 downto 0);
drxa_o : out std_logic_vector(31 downto 0);
drxb_o : out std_logic_vector(31 downto 0);
-- Alarms for controlling the i2c states
pf_wb_addr_o : out std_logic;
......@@ -87,11 +86,11 @@ entity i2c_slave_core is
rd_done_o : out std_logic;
wr_done_o : out std_logic
);
end i2c_slave_core;
end entity bridge;
architecture Behavioral of i2c_slave_core is
architecture behav of bridge is
type t_state is (
R0_RESET,
......@@ -116,6 +115,37 @@ architecture Behavioral of i2c_slave_core is
S7_PAUSE_DETECT
);
component i2c_bit is
port
(
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
sda_i : in STD_LOGIC;
scl_i : in STD_LOGIC;
start_o : out STD_LOGIC;
pause_o : out STD_LOGIC;
rcved_o : out STD_LOGIC;
done_o : out STD_LOGIC
);
end component i2c_bit;
component gc_counter is
generic
(
g_DATA_WIDTH: NATURAL
);
port
(
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0)
);
end component gc_counter;
-------------------------------------------------------------------------------
-- FSM signals for the I2C module
-------------------------------------------------------------------------------
......@@ -125,20 +155,20 @@ architecture Behavioral of i2c_slave_core is
-- signal coming from i2c_bit.vhd
-- Every time a deglitched falling edge of the SCL line is detected in the
-- aforementioned i2c_bit.vhd, the signals done, start_o, pause_o, rcved_o are
-- considered valid to be studied in i2c_slave_core.vhd processes.
-- considered valid to be studied in bridge.vhd processes.
--
-------------------------------------------------------------------------------
constant c_WATCHDOG_END_VALUE : NATURAL := c_WATCHDOG_DEADLINE/g_WB_CLK_PERIOD;
constant c_WATCHDOG_END_VALUE : NATURAL := 10**9; -- 8sec reset period
signal state : t_state := R0_RESET;
signal state_d0 : t_state := R0_RESET;
signal s_DRXA_slv : std_logic_vector(r_DRX'a_length - 1 downto 0) := (others => '0');
signal s_DRXB_slv : std_logic_vector(r_DRX'a_length - 1 downto 0) := (others => '0');
signal s_DRX_slv : std_logic_vector(r_DRX'a_length*2 - 1 downto 0) := (others => '0');
signal s_DTX_slv : std_logic_vector(r_DTX'a_length - 1 downto 0);
signal s_DRXA_slv : std_logic_vector(31 downto 0) := (others => '0');
signal s_DRXB_slv : std_logic_vector(31 downto 0) := (others => '0');
signal s_DRX_slv : std_logic_vector(63 downto 0) := (others => '0');
signal s_DTX_slv : std_logic_vector(31 downto 0);
signal s_CTR0 : r_CTR0;
signal s_LT : r_LT := c_LT_default;
......@@ -181,15 +211,15 @@ architecture Behavioral of i2c_slave_core is
begin
s_CTR0 <= f_CTR0(CTR0_i);
LT_o <= f_STD_LOGIC_VECTOR(s_LT);
s_CTR0 <= f_CTR0(ctr0_i);
lt_o <= f_STD_LOGIC_VECTOR(s_LT);
s_pf_wb_data <= pf_wb_data_i;
cmp_i2c_bit: i2c_bit
port map
(
rst_i => rst_i,
wb_clk_i => clk_i,
clk_i => clk_i,
sda_i => sda_i,
scl_i => scl_i,
start_o => s_start_o,
......@@ -376,8 +406,8 @@ begin
end if;
end process;
DRXA_o <= s_DRXA_slv;
DRXB_o <= s_DRXB_slv;
drxa_o <= s_DRXA_slv;
drxb_o <= s_DRXB_slv;
-- Process to update the signals that drive bit_counter_8
p_bit_counter_comb : process(state, state_d0, s_byte_cnt)
......@@ -729,4 +759,4 @@ begin
end if;
end process p_fsm;
end Behavioral;
end behav;
hdl/i2c_slave_wb_master/rtl/i2c_bit.vhd → hdl/i2c_to_wb_bridge/rtl/i2c_bit.vhd
View file @ 9a04b242
......@@ -4,7 +4,7 @@
--
-- Create Date: 00:47:34 10/26/2011
-- Design Name: i2c bit recognition fsm
-- Module Name: i2c_bit - Behavioral
-- Module Name: i2c_bit - behav
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
......@@ -25,14 +25,12 @@ library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
entity i2c_bit is
port
(
rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
sda_i : in STD_LOGIC;
scl_i : in STD_LOGIC;
......@@ -44,7 +42,23 @@ entity i2c_bit is
);
end i2c_bit;
architecture Behavioral of i2c_bit is
architecture behav of i2c_bit is
component i2c_debouncer is
generic
(
g_LENGTH : NATURAL := 6
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0)
);
end component i2c_debouncer;
type t_state is (
R0_RESET,
......@@ -60,22 +74,22 @@ architecture Behavioral of i2c_bit is
);
-- It specifies the maximum number of stages that will be employed for
-- deglitching. Clocked with wb_clk_i
-- deglitching. Clocked with clk_i
constant c_MAX_GLITCH_DELAY : NATURAL := 6;
-- Three delay stages out of six
constant c_GLITCH_MASK : STD_LOGIC_VECTOR (5 downto 0) := "000111";
signal s_sda_deglitched : STD_LOGIC;
signal s_sda_deglitched_d1 : STD_LOGIC;
signal sda_deglitched : STD_LOGIC;
signal sda_deglitched_d1 : STD_LOGIC;
signal s_scl_deglitched : STD_LOGIC;
signal s_scl_deglitched_d1 : STD_LOGIC;
signal scl_deglitched : STD_LOGIC;
signal scl_deglitched_d1 : STD_LOGIC;
signal state : t_state;
signal s_scl_rising : STD_LOGIC;
signal s_scl_falling : STD_LOGIC;
signal scl_rising : STD_LOGIC;
signal scl_falling : STD_LOGIC;
begin
......@@ -87,26 +101,12 @@ begin
port map
(
rst => rst_i,
clk => wb_clk_i,
clk => clk_i,
input => scl_i,
output => s_scl_deglitched,
output => scl_deglitched,
glitch_mask => c_GLITCH_MASK
);
-- Probably safer operation if we add one extra delay to the scl line.
-- However, we increase the glitch time while placing an ACK.
-- We have not implemented a counter to foresee the glitch due to the
-- strange behaviour in Renesas I2C which rescales dinamically (that
-- means in the middle of an I2C transaction) the scl line.
-- Due to the variability of the scl period when an I2C transaction is
cmp_scl_ff: gc_ff
port map
(
Q => s_scl_deglitched_d1,
C => wb_clk_i,
CLR => rst_i,
D => s_scl_deglitched
);
cmp_sda_debounce: i2c_debouncer
generic map
......@@ -116,35 +116,40 @@ begin
port map
(
rst => rst_i,
clk => wb_clk_i,
clk => clk_i,
input => sda_i,
output => s_sda_deglitched,
output => sda_deglitched,
glitch_mask => c_GLITCH_MASK
);
cmp_sda_ff: gc_ff
port map
(
Q => s_sda_deglitched_d1,
C => wb_clk_i,
CLR => rst_i,
D => s_sda_deglitched
);
process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
sda_deglitched_d1 <= '0';
scl_deglitched_d1 <= '0';
else
sda_deglitched_d1 <= sda_deglitched;
scl_deglitched_d1 <= scl_deglitched;
end if;
end if;
end process;
-- This is the process that samples the scl for detecting
-- rise and falling edges
reg_proc: process (wb_clk_i)
reg_proc: process (clk_i)
begin
if rising_edge(wb_clk_i) then
if (s_scl_deglitched xor s_scl_deglitched_d1) = '1' then
if s_scl_deglitched = '0' then
s_scl_falling <= '1';
else
s_scl_rising <= '1';
end if;
if rising_edge(clk_i) then
if (rst_i = '1') then
scl_falling <= '0';
scl_rising <= '0';
elsif (scl_deglitched = '0') and (scl_deglitched_d1 = '1') then
scl_falling <= '1';
elsif (scl_deglitched = '1') and (scl_deglitched_d1 = '0') then
scl_rising <= '1';
else
s_scl_rising <= '0';
s_scl_falling <= '0';
scl_falling <= '0';
scl_rising <= '0';
end if;
end if;
end process;
......@@ -194,13 +199,12 @@ begin
-- The fsm of this module, later on the sda sampled line is
-- validated in the falling edge of scl.
p_fsm: process(wb_clk_i)
p_fsm: process(clk_i)
begin
if rising_edge(wb_clk_i) then
if rising_edge(clk_i) then
if (rst_i = '1') then
state <= R0_RESET;
elsif (s_scl_falling = '1') then
elsif scl_falling = '1' then
-- After a detection of a falling edge we update the
-- detection of a '0', a '1' and a start condition.
case state is
......@@ -217,10 +221,10 @@ begin
state <= S0_IDLE;
end case;
elsif (s_scl_rising = '1') then
elsif (scl_rising = '1') then
-- When a rising edge is detected we annotate the first value
-- in SDA: either a temporary '0' or '1'
if (s_sda_deglitched_d1 = '1') then
if (sda_deglitched_d1 = '1') then
state <= S1A_HIGH_TMP;
else
state <= S1B_LOW_TMP;
......@@ -229,32 +233,32 @@ begin
else
-- When we are in high level of a scl cycle, we keep on updating
-- the FSM
if (s_scl_deglitched = '1') then
if (scl_deglitched = '1') then
case state is
-- Just for random bit swapped coverage.
when S0_IDLE =>
if (s_sda_deglitched = '1') then
if (sda_deglitched = '1') then
state <= S1A_HIGH_TMP;
else
state <= S1B_LOW_TMP;
end if;
when S1A_HIGH_TMP =>
if s_sda_deglitched = '0' then
if sda_deglitched = '0' then
-- The detection of the start condition will be reported
-- in the next SCL rising edge.
state <= S2A_START_TMP;
end if;
when S1B_LOW_TMP =>
if s_sda_deglitched = '1' then
if sda_deglitched = '1' then
-- The detection of the pause condition MUST be
-- reported immediately.
state <= S2B_STOP_DETECT;
end if;
when S2A_START_TMP =>
if (s_sda_deglitched = '1') then
if (sda_deglitched = '1') then
--! This happens if the deglitching is not enough
state <= Q1_ERROR;
end if;
......@@ -263,7 +267,7 @@ begin
state <= S0_IDLE;
end case;
else
if (s_scl_deglitched_d1 = '0') then
if (scl_deglitched_d1 = '0') then
state <= S0_IDLE;
end if;
end if;
......@@ -271,4 +275,4 @@ begin
end if;
end process p_fsm;
end Behavioral;
end behav;
hdl/i2c_slave_wb_master/rtl/i2c_debounce.vhd → hdl/i2c_to_wb_bridge/rtl/i2c_debounce.vhd
View file @ 9a04b242
......@@ -26,13 +26,11 @@ library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
entity i2c_debouncer is
generic
(
g_LENGTH : NATURAL := c_DEBOUNCE_LENGTH
g_LENGTH : NATURAL := 6
);
port
(
......@@ -46,40 +44,25 @@ end i2c_debouncer;
architecture Behavioral of i2c_debouncer is
signal s_input_d0 : STD_LOGIC;
signal input_d0 : STD_LOGIC;
-- The first of this signal is already stable (ff'ed two times at [0])
signal s_delay : STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0);
signal delay : STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0);
begin
cmp_ff1: gc_ff
port map
(
Q => s_input_d0,
C => clk,
CLR => rst,
D => input
);
cmp_ff2: gc_ff
port map
(
Q => s_delay(0),
C => clk,
CLR => rst,
D => s_input_d0
);
gen_sync_delay_line: for i in 1 to g_LENGTH - 1 generate
cmp_ff: gc_ff
port map
(
Q => s_delay(i),
C => clk,
CLR => rst,
D => s_delay(i-1)
);
end generate gen_sync_delay_line;
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
input_d0 <= '0';
delay <= (others => '0');
else
input_d0 <= input;
delay(0) <= input_d0;
delay(g_length-1 downto 1) <= delay(g_length-2 downto 0);
end if;
end if;
end process;
p_output: process (clk)
begin
......@@ -88,9 +71,9 @@ begin
output <= '1';
else
-- We can deglitch either zeros or ones
if ( (s_delay and glitch_mask) = glitch_mask
or (not(s_delay) and glitch_mask) = glitch_mask) then
output <= s_delay(0);
if ( (delay and glitch_mask) = glitch_mask
or (not(delay) and glitch_mask) = glitch_mask) then
output <= delay(0);
else
-- Internall pull-up of the pin
output <= '1';
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd → hdl/i2c_to_wb_bridge/rtl/i2c_to_wb_bridge.vhd
View file @ 9a04b242
......@@ -4,7 +4,7 @@
--
-- Create Date: 18:15:56 11/09/2011
-- Design Name: A I2C slave with wishbone slave output and interrupt for MCU
-- Module Name: i2c_slave_top - Behavioral
-- Module Name: i2c_to_wb_bridge - behav
-- Project Name: CTDAH
-- Target Devices:
-- Tool versions:
......@@ -22,71 +22,137 @@ library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
use work.i2c_slave_pkg.all;
entity i2c_slave_top is
entity i2c_to_wb_bridge is
port
(
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
clk_i : in std_logic;
rst_i : in std_logic;
wb_master_stb_o : out std_logic;
wb_master_cyc_o : out std_logic;
wb_master_sel_o : out std_logic_vector(3 downto 0);
wb_master_we_o : out std_logic;
wb_master_dat_i : in std_logic_vector(31 downto 0);
wb_master_dat_o : out std_logic_vector(31 downto 0);
wb_master_adr_o : out std_logic_vector(15 downto 0);
wb_master_ack_i : in std_logic;
wb_master_rty_i : in std_logic;
wb_master_err_i : in std_logic;
wb_slave_stb_i : in std_logic;
wb_slave_cyc_i : in std_logic;
wb_slave_sel_i : in std_logic_vector(3 downto 0);
wb_slave_we_i : in std_logic;
wb_slave_dat_i : in std_logic_vector(31 downto 0);
wb_slave_dat_o : out std_logic_vector(31 downto 0);
wb_slave_adr_i : in std_logic_vector(3 downto 0);
wb_slave_ack_o : out std_logic;
wb_slave_rty_o : out std_logic;
wb_slave_err_o : out std_logic;
pf_wb_addr_o : out std_logic;
rd_done_o : out std_logic;
wr_done_o : out std_logic;
i2c_addr_i : in std_logic_vector(6 downto 0)
);
end i2c_to_wb_bridge;
architecture behav of i2c_to_wb_bridge is
component bridge is
generic
(
g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD -- Specify in ns
g_WB_CLK_PERIOD : time := 50 ns
);
port
(
sda_en_o : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_en_o : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
clk_i : in std_logic;
rst_i : in std_logic;
-- I2C pins
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
-- Registers
CTR0_i : in std_logic_vector (r_CTR0'a_length - 1 downto 0);
LT_o : out std_logic_vector (r_LT'a_length - 1 downto 0);
DRXA_o : out std_logic_vector (r_DRX'a_length - 1 downto 0);
DRXB_o : out std_logic_vector (r_DRX'a_length - 1 downto 0);
-- Alarms for controlling the i2c states
pf_wb_addr_o : out std_logic;
pf_wb_data_i : in std_logic_vector(31 downto 0);
rd_done_o : out std_logic;
wr_done_o : out std_logic
);
end component bridge;
component bridge_regs is
port
(
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_we_o : out STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_master_we_o : out STD_LOGIC;
wb_master_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_adr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_master_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_adr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
-- These are the registers offers to others modules of the FPGA
wb_slave_we_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_we_i : in STD_LOGIC;
wb_slave_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_adr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_slave_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_slave_adr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
pf_wb_addr_o : out STD_LOGIC;
rd_done_o : out STD_LOGIC;
wr_done_o : out STD_LOGIC;
-- These are the registers that are offered to the i2c slave core
ctr0_o : out STD_LOGIC_VECTOR (31 downto 0);
lt_i : in STD_LOGIC_VECTOR (31 downto 0);
drxa_i : in STD_LOGIC_VECTOR (31 downto 0);
drxb_i : in STD_LOGIC_VECTOR (31 downto 0);
pf_wb_addr_i : in STD_LOGIC;
pf_wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
rd_done_i : in STD_LOGIC;
wr_done_i : in STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
);
end i2c_slave_top;
architecture Behavioral of i2c_slave_top is
end component bridge_regs;
signal ctr0 : STD_LOGIC_VECTOR(r_CTR0'a_length - 1 downto 0);
signal lt : STD_LOGIC_VECTOR(r_LT'a_length - 1 downto 0);
signal drxa : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal drxb : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal ctr0 : std_logic_vector(r_CTR0'a_length - 1 downto 0);
signal lt : std_logic_vector(r_LT'a_length - 1 downto 0);
signal pf_wb_addr : STD_LOGIC;
signal pf_wb_data : STD_LOGIC_VECTOR(31 downto 0);
signal rd_done : STD_LOGIC;
signal wr_done : STD_LOGIC;
signal drxa : std_logic_vector(r_DRX'a_length - 1 downto 0);
signal drxb : std_logic_vector(r_DRX'a_length - 1 downto 0);
signal s_clk_i2c : STD_LOGIC;
signal rst_i2c : STD_LOGIC;
signal reset_extender: STD_LOGIC_VECTOR(2**c_RST_EXTENSOR - 1 downto 0) := (others => '1');
signal pf_wb_addr : std_logic;
signal pf_wb_data : std_logic_vector(31 downto 0);
signal rd_done : std_logic;
signal wr_done : std_logic;
begin
......@@ -94,11 +160,15 @@ begin
rd_done_o <= rd_done;
wr_done_o <= wr_done;
cmp_i2c_slave_core: i2c_slave_core
cmp_bridge: bridge
generic map
(
g_wb_clk_period => 8 ns
)
port map
(
clk_i => wb_clk_i,
rst_i => wb_rst_i,
clk_i => clk_i,
rst_i => rst_i,
sda_en_o => sda_en_o,
sda_i => sda_i,
......@@ -118,7 +188,7 @@ begin
wr_done_o => wr_done
);
cmp_i2c_regs: i2c_regs
cmp_bridge_regs: bridge_regs
port map
(
pf_wb_addr_i => pf_wb_addr,
......@@ -126,8 +196,8 @@ begin
rd_done_i => rd_done,
wr_done_i => wr_done,
wb_rst_i => wb_rst_i,
wb_clk_i => wb_clk_i,
wb_rst_i => rst_i,
wb_clk_i => clk_i,
wb_master_we_o => wb_master_we_o,
wb_master_stb_o => wb_master_stb_o,
......@@ -151,28 +221,11 @@ begin
wb_slave_rty_o => wb_slave_rty_o,
wb_slave_err_o => wb_slave_err_o,
CTR0_o => ctr0,
LT_i => lt,
DRXA_i => drxa,
DRXB_i => drxb,
ctr0_o => ctr0,
lt_i => lt,
drxa_i => drxa,
drxb_i => drxb,
i2c_addr_i => i2c_addr_i
);
rst_i2c <= reset_extender(2**c_RST_EXTENSOR - 1);
--! A shift with reset, consumes just a few SLICEX in Spartan6.
p_rst_extender : process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
reset_extender <= (others => '1');
else
reset_extender(0) <= '0';
for i in 1 to 2**c_RST_EXTENSOR -1 loop
reset_extender(i) <= reset_extender(i-1);
end loop;
end if;
end if;
end process;
end Behavioral;
end behav;
hdl/i2c_to_wb_bridge/syn/Makefile 0 → 100644
View file @ 9a04b242
This diff is collapsed.
hdl/i2c_to_wb_bridge/syn/Manifest.py 0 → 100644
View file @ 9a04b242
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo_v2"
syn_project = "conv_ttl_blo_v2.xise"
modules = {
"local" : [
"../top"
]
}
hdl/i2c_to_wb_bridge/syn/conv_ttl_blo_v2.gise 0 → 100644
View file @ 9a04b242
This diff is collapsed.
hdl/i2c_to_wb_bridge/syn/run.tcl 0 → 100644
View file @ 9a04b242
project open conv_ttl_blo_v2.xise
process run {Generate Programming File} -force rerun_all
hdl/i2c_to_wb_bridge/top/Manifest.py 0 → 100644
View file @ 9a04b242
files = [
"conv_ttl_blo_v2.ucf",
"conv_ttl_blo_v2.vhd"
]
modules = {
"local" : [
"../../../../ip_cores/general-cores",
"../../reset_gen",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../rtl",
]
}
hdl/i2c_to_wb_bridge/top/conv_ttl_blo_v2.ucf 0 → 100644
View file @ 9a04b242
This diff is collapsed.
hdl/i2c_to_wb_bridge/top/conv_ttl_blo_v2.vhd 0 → 100644
View file @ 9a04b242
This diff is collapsed.
hdl/release/syn/Makefile
View file @ 9a04b242
......@@ -36,10 +36,10 @@ endif
CWD := $(shell pwd)
FILES := ../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../top/conv_ttl_blo_v2.ucf \
FILES := ../top/conv_ttl_blo_v2.ucf \
../top/conv_ttl_blo_v2.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../pulse_generator/rtl/pulse_generator.vhd \
../../rtm_detector/rtl/rtm_detector.vhd \
......
hdl/release/syn/Manifest.py
View file @ 9a04b242
......@@ -8,10 +8,6 @@ syn_project = "conv_ttl_blo_v2.xise"
modules = {
"local" : [
"../../reset_gen",
"../../pulse_generator",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../top"
]
}
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ 9a04b242
......@@ -22,6 +22,8 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="conv_ttl_blo_v2.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_CMD" xil_pn:name="_impact.cmd"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impact.log"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impactbatch.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -53,7 +55,6 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo_v2.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="conv_ttl_blo_v2.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo_v2.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_v2_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_v2_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_v2_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_v2_map.mrp" xil_pn:subbranch="Map"/>
......@@ -76,35 +77,34 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1362648727">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1362648727">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1362648727">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1362648727">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1362648727">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1362648727">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362648727" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1362648727">
<transform xil_pn:end_ts="1363009882" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363002038" xil_pn:in_ck="-4590833482063591864" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1363002026">
<transform xil_pn:end_ts="1363009896" xil_pn:in_ck="-1985142147321250132" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1363009882">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
......@@ -121,11 +121,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1362651935" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1362651935">
<transform xil_pn:end_ts="1363009896" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1363009896">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363002044" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1363002038">
<transform xil_pn:end_ts="1363009903" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1363009896">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -134,7 +134,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1363002072" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1363002044">
<transform xil_pn:end_ts="1363009934" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1363009903">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
......@@ -149,7 +149,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1363002100" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1363002072">
<transform xil_pn:end_ts="1363009963" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1363009934">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -163,7 +163,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1363002118" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1363002100">
<transform xil_pn:end_ts="1363009981" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1363009963">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -174,25 +174,17 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1362751327" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="-4173336264699367391" xil_pn:start_ts="1362751327">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1363002119" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1363002118">
<transform xil_pn:end_ts="1363009981" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1363009981">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impact.cmd"/>
<outfile xil_pn:name="_impact.log"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1363002100" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1363002093">
<transform xil_pn:end_ts="1363009963" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1363009955">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/syn/conv_ttl_blo_v2.xise
View file @ 9a04b242
......@@ -342,15 +342,15 @@
<file xil_pn:name="../top/conv_ttl_blo_v2.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
......@@ -360,10 +360,6 @@
<file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../old_rep_test/rtl/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<bindings/>
......
hdl/release/top/Manifest.py
View file @ 9a04b242
......@@ -2,3 +2,12 @@ files = [
"conv_ttl_blo_v2.ucf",
"conv_ttl_blo_v2.vhd"
]
modules = {
"local" : [
"../../reset_gen",
"../../pulse_generator",
"../../rtm_detector",
"../../bicolor_led_ctrl",
]
}
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