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Conv TTL Blocking
Commit 9c48eb1b authored by gilsoriano's avatar gilsoriano
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Basic repetitor committed to repo.

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<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="basic_trigger_top_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="basic_trigger_top_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="basic_trigger_top_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="basic_trigger_top_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="basic_trigger_top" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/trigger_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.trigger_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Up" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|trigger_top_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="basic_trigger" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-10-08T16:26:30" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="EF41633B9B530BE50A9AA6E385725EA0" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
hdl/basic_trigger/constraints/FPGAbank.ucf 0 → 100755
View file @ 9c48eb1b
##---------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##----------------------------------------
#
#
NET "clk_i" LOC = E16;
NET "clk_i" IOSTANDARD = "LVCMOS33";
NET "clk_i" TNM_NET = "clk_i";
TIMESPEC TS_clk_i = PERIOD "clk_i" 20 MHz HIGH 50%;
#
#NET "FPGA_CLK_N" LOC = G11;
# NET "FPGA_CLK_N" IOSTANDARD = "LVDS_25";
#NET "FPGA_CLK_P" LOC = H12;
# NET "FPGA_CLK_P" IOSTANDARD = "LVDS_25";
#
#NET "FPGA_SYSRESET_N" LOC = L20;
NET "manual_rst_n_o" LOC = T22;
NET "manual_rst_n_o" IOSTANDARD = "LVCMOS33";
#
##======================================
##-- FRONT PANEL TTLS
##======================================
##-- LEDs
##--
##-- + ACT: CMOS 3.3V input
##-------------------
NET "led_pw_o" LOC = F10;
NET "led_pw_o" IOSTANDARD = "LVCMOS33";
NET "led_pw_o" DRIVE = "4";
NET "led_pw_o" SLEW = "QUIETIO";
NET "led_err_o" LOC = F9;
NET "led_err_o" IOSTANDARD = "LVCMOS33";
NET "led_err_o" DRIVE = "4";
NET "led_err_o" SLEW = "QUIETIO";
NET "led_ttl_o" LOC = F8;
NET "led_ttl_o" IOSTANDARD = "LVCMOS33";
NET "led_ttl_o" DRIVE = "4";
NET "led_ttl_o" SLEW = "QUIETIO";
NET "led_o_front[1]" LOC = H3;
NET "led_o_front[1]" IOSTANDARD = "LVCMOS33";
NET "led_o_front[1]" DRIVE = "4";
NET "led_o_front[1]" SLEW = "QUIETIO";
NET "led_o_front[2]" LOC = J4;
NET "led_o_front[2]" IOSTANDARD = "LVCMOS33";
NET "led_o_front[2]" DRIVE = "4";
NET "led_o_front[2]" SLEW = "QUIETIO";
NET "led_o_front[3]" LOC = J3;
NET "led_o_front[3]" IOSTANDARD = "LVCMOS33";
NET "led_o_front[3]" DRIVE = "4";
NET "led_o_front[3]" SLEW = "QUIETIO";
NET "led_o_front[4]" LOC = K3;
NET "led_o_front[4]" IOSTANDARD = "LVCMOS33";
NET "led_o_front[4]" DRIVE = "4";
NET "led_o_front[4]" SLEW = "QUIETIO";
NET "led_o_front[5]" LOC = L4;
NET "led_o_front[5]" IOSTANDARD = "LVCMOS33";
NET "led_o_front[5]" DRIVE = "4";
NET "led_o_front[5]" SLEW = "QUIETIO";
NET "led_o_front[6]" LOC = L3;
NET "led_o_front[6]" IOSTANDARD = "LVCMOS33";
NET "led_o_front[6]" DRIVE = "4";
NET "led_o_front[6]" SLEW = "QUIETIO";
##-------------------
##-- TTL trigger inputs
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "pulse_i_front[1]" LOC = T3;
NET "pulse_i_front[1]" IOSTANDARD = "LVCMOS33";
NET "pulse_i_front[2]" LOC = U4;
NET "pulse_i_front[2]" IOSTANDARD = "LVCMOS33";
NET "pulse_i_front[3]" LOC = W3;
NET "pulse_i_front[3]" IOSTANDARD = "LVCMOS33";
NET "pulse_i_front[4]" LOC = W4;
NET "pulse_i_front[4]" IOSTANDARD = "LVCMOS33";
NET "pulse_i_front[5]" LOC = V3;
NET "pulse_i_front[5]" IOSTANDARD = "LVCMOS33";
NET "pulse_i_front[6]" LOC = U3;
NET "pulse_i_front[6]" IOSTANDARD = "LVCMOS33";
##-------------------
##-- TTL Blocking pulses outputs
##--
##-- + BCT family (BiCMOS) TTL inputs
##-------------------
NET "pulse_o_front[1]" LOC = D1;
NET "pulse_o_front[1]" IOSTANDARD = "LVTTL";
NET "pulse_o_front[1]" SLEW = "FAST";
NET "pulse_o_front[2]" LOC = E1;
NET "pulse_o_front[2]" IOSTANDARD = "LVTTL";
NET "pulse_o_front[2]" SLEW = "FAST";
NET "pulse_o_front[3]" LOC = F2;
NET "pulse_o_front[3]" IOSTANDARD = "LVTTL";
NET "pulse_o_front[3]" SLEW = "FAST";
NET "pulse_o_front[4]" LOC = F1;
NET "pulse_o_front[4]" IOSTANDARD = "LVTTL";
NET "pulse_o_front[4]" SLEW = "FAST";
NET "pulse_o_front[5]" LOC = G1;
NET "pulse_o_front[5]" IOSTANDARD = "LVTTL";
NET "pulse_o_front[5]" SLEW = "FAST";
NET "pulse_o_front[6]" LOC = H2;
NET "pulse_o_front[6]" IOSTANDARD = "LVTTL";
NET "pulse_o_front[6]" SLEW = "FAST";
##-------------------
##-- Bottom located GPIOs
##--
##-- + IN ACT family: CMOS/TTL 3.3V inputs
##-- + OUT BCT family (BiCMOS): TTL inputs
##
##-- Schematics name: INV_IN_*
##---- renamed to INV_IN[*]
##-------------------
NET "inv_i[1]" LOC = Y1;
NET "inv_i[1]" IOSTANDARD = "LVCMOS33";
NET "inv_i[2]" LOC = Y2;
NET "inv_i[2]" IOSTANDARD = "LVCMOS33";
NET "inv_i[3]" LOC = AA1;
NET "inv_i[3]" IOSTANDARD = "LVCMOS33";
NET "inv_i[4]" LOC = AA2;
NET "inv_i[4]" IOSTANDARD = "LVCMOS33";
NET "inv_o[1]" LOC = J1;
NET "inv_o[1]" IOSTANDARD = "LVTTL";
NET "inv_o[1]" SLEW = "FAST";
NET "inv_o[1]" DRIVE = "4";
NET "inv_o[2]" LOC = K2;
NET "inv_o[2]" IOSTANDARD = "LVTTL";
NET "inv_o[2]" SLEW = "FAST";
NET "inv_o[2]" DRIVE = "4";
NET "inv_o[3]" LOC = K1;
NET "inv_o[3]" IOSTANDARD = "LVTTL";
NET "inv_o[3]" SLEW = "FAST";
NET "inv_o[3]" DRIVE = "4";
NET "inv_o[4]" LOC = L1;
NET "inv_o[4]" IOSTANDARD = "LVTTL";
NET "inv_o[4]" SLEW = "FAST";
NET "inv_o[4]" DRIVE = "4";
##
##
##======================================
##-- RTM signals
##======================================
##-- Blocking input to FPGA
##
##-- Schematics name: FPGA_BLO_IN_*
##---- renamed to FPGA_BLO_IN[*]
##-------------------
NET "pulse_i_rear[1]" LOC = W18;
NET "pulse_i_rear[1]" IOSTANDARD = "LVTTL";
NET "pulse_i_rear[2]" LOC = Y18;
NET "pulse_i_rear[2]" IOSTANDARD = "LVTTL";
NET "pulse_i_rear[3]" LOC = W17;
NET "pulse_i_rear[3]" IOSTANDARD = "LVTTL";
NET "pulse_i_rear[4]" LOC = Y17;
NET "pulse_i_rear[4]" IOSTANDARD = "LVTTL";
NET "pulse_i_rear[5]" LOC = Y16;
NET "pulse_i_rear[5]" IOSTANDARD = "LVTTL";
NET "pulse_i_rear[6]" LOC = Y15;
NET "pulse_i_rear[6]" IOSTANDARD = "LVTTL";
##-------------------
##-- Blocking driver triggers from FPGA
##--
##-- + OUT BCT family (BiCMOS): TTL inputs
##-------------------
NET "pulse_o_rear[1]" LOC = V1;
NET "pulse_o_rear[1]" IOSTANDARD = "LVTTL";
NET "pulse_o_rear[1]" SLEW = "FAST";
NET "pulse_o_rear[2]" LOC = U1;
NET "pulse_o_rear[2]" IOSTANDARD = "LVTTL";
NET "pulse_o_rear[2]" SLEW = "FAST";
NET "pulse_o_rear[3]" LOC = T2;
NET "pulse_o_rear[3]" IOSTANDARD = "LVTTL";
NET "pulse_o_rear[3]" SLEW = "FAST";
NET "pulse_o_rear[4]" LOC = T1;
NET "pulse_o_rear[4]" IOSTANDARD = "LVTTL";
NET "pulse_o_rear[4]" SLEW = "FAST";
NET "pulse_o_rear[5]" LOC = R1;
NET "pulse_o_rear[5]" IOSTANDARD = "LVTTL";
NET "pulse_o_rear[5]" SLEW = "FAST";
NET "pulse_o_rear[6]" LOC = P2;
NET "pulse_o_rear[6]" IOSTANDARD = "LVTTL";
NET "pulse_o_rear[6]" SLEW = "FAST";
##-------------------
##-- Rear LEDs
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "led_o_rear[1]" LOC = AB17;
NET "led_o_rear[1]" IOSTANDARD = "LVCMOS33";
NET "led_o_rear[1]" DRIVE = "4";
NET "led_o_rear[1]" SLEW = "QUIETIO";
NET "led_o_rear[2]" LOC = AB19;
NET "led_o_rear[2]" IOSTANDARD = "LVCMOS33";
NET "led_o_rear[2]" DRIVE = "4";
NET "led_o_rear[2]" SLEW = "QUIETIO";
NET "led_o_rear[3]" LOC = AA16;
NET "led_o_rear[3]" IOSTANDARD = "LVCMOS33";
NET "led_o_rear[3]" DRIVE = "4";
NET "led_o_rear[3]" SLEW = "QUIETIO";
NET "led_o_rear[4]" LOC = AA18;
NET "led_o_rear[4]" IOSTANDARD = "LVCMOS33";
NET "led_o_rear[4]" DRIVE = "4";
NET "led_o_rear[4]" SLEW = "QUIETIO";
NET "led_o_rear[5]" LOC = AB16;
NET "led_o_rear[5]" IOSTANDARD = "LVCMOS33";
NET "led_o_rear[5]" DRIVE = "4";
NET "led_o_rear[5]" SLEW = "QUIETIO";
NET "led_o_rear[6]" LOC = AB18;
NET "led_o_rear[6]" IOSTANDARD = "LVCMOS33";
NET "led_o_rear[6]" DRIVE = "4";
NET "led_o_rear[6]" SLEW = "QUIETIO";
##======================================
##-- VME CONNECTOR SIGNALS
##======================================
##-- I2C lines
##--
##-- + UBT: LVTTL input
##-------------------
## NET "SCL_I" LOC = F19;
## NET "SCL_I" IOSTANDARD = "LVTTL";
## NET "SCL_O" LOC = E20;
## NET "SCL_O" IOSTANDARD = "LVTTL";
## NET "SCL_O" DRIVE = "4";
## NET "SCL_OE" LOC = H18;
## NET "SCL_OE" IOSTANDARD = "LVTTL";
## NET "SCL_OE" DRIVE = "4";
## NET "SCL_OE" PULLDOWN;
## NET "SDA_I" LOC = G20;
## NET "SDA_I" IOSTANDARD = "LVTTL";
## NET "SDA_O" LOC = F20;
## NET "SDA_O" IOSTANDARD = "LVTTL";
## NET "SDA_O" SLEW = "FAST";
## NET "SDA_O" DRIVE = "4";
## NET "SDA_O" PULLUP;
## NET "SDA_OE" LOC = J19;
## NET "SDA_OE" IOSTANDARD = "LVTTL";
## NET "SDA_OE" SLEW = "FAST";
## NET "SDA_OE" DRIVE = "4";
## NET "SDA_OE" PULLDOWN;
##-------------------
##-- Geographical Address
##--
##-- + UBT: LVTTL input
##-------------------
## NET "FPGA_GA[0]" LOC = H20;
## NET "FPGA_GA[0]" IOSTANDARD = "LVTTL";
## NET "FPGA_GA[1]" LOC = J20;
## NET "FPGA_GA[1]" IOSTANDARD = "LVTTL";
## NET "FPGA_GA[2]" LOC = K19;
## NET "FPGA_GA[2]" IOSTANDARD = "LVTTL";
## NET "FPGA_GA[3]" LOC = K20;
## NET "FPGA_GA[3]" IOSTANDARD = "LVTTL";
## NET "FPGA_GA[4]" LOC = L19;
## NET "FPGA_GA[4]" IOSTANDARD = "LVTTL";
## NET "FPGA_GAP" LOC = H19;
## NET "FPGA_GAP" IOSTANDARD = "LVTTL";
##======================================
##-- WHITE RABBIT
##======================================
##-- LEDs
##--
##-- + ACT: CMOS 3.3V input
##-------------------
NET "led_link_up_o" LOC = F7;
NET "led_link_up_o" IOSTANDARD = "LVCMOS33";
NET "led_link_up_o" DRIVE = "4";
NET "led_link_up_o" SLEW = "QUIETIO";
NET "led_pps_o" LOC = E6;
NET "led_pps_o" IOSTANDARD = "LVCMOS33";
NET "led_pps_o" DRIVE = "4";
NET "led_pps_o" SLEW = "QUIETIO";
NET "led_wr_ok_o" LOC = E5;
NET "led_wr_ok_o" IOSTANDARD = "LVCMOS33";
NET "led_wr_ok_o" DRIVE = "4";
NET "led_wr_ok_o" SLEW = "QUIETIO";
##-------------------
##-- Thermo for UID
##-------------------
## NET "THERMOMETER" LOC = B1;
## NET "THERMOMETER" IOSTANDARD = "LVTTL";
##-------------------
##-- DACs control
##--
##-- + CMOS 3.3V input
##-------------------
## NET "FPGA_PLLDAC1_SYNC_N" LOC = AB15;
## NET "FPGA_PLLDAC1_SYNC_N" IOSTANDARD = "LVCMOS33";
## NET "FPGA_PLLDAC2_SYNC_N" LOC = Y14;
## NET "FPGA_PLLDAC2_SYNC_N" IOSTANDARD = "LVCMOS33";
## NET "FPGA_PLLDAC_DIN" LOC = AB14;
## NET "FPGA_PLLDAC_DIN" IOSTANDARD = "LVCMOS33";
## NET "FPGA_PLLDAC_SCLK" LOC = AA14;
## NET "FPGA_PLLDAC_SCLK" IOSTANDARD = "LVCMOS33";
##-------------------
##-- SFP connection
##-------------------
## NET "FPGA_SFP_LOS" LOC = G3;
## NET "FPGA_SFP_PRESENCE" LOC = E3;
## NET "FPGA_SFP_RATE_SELECT" LOC = C4;
## NET "FPGA_SFP_SCL" LOC = F3;
## NET "FPGA_SFP_SDA" LOC = G4;
## NET "SFP_TX_DISABLE" LOC = E4;
## NET "SFP_TX_FAULT" LOC = D2;
##-------------------
##-- FPGA MGT lines
##-------------------
## NET "FPGAMGTCLK0_N" LOC = B10;
## NET "FPGAMGTCLK0_N" IOSTANDARD = "LVDS_12";
## NET "FPGAMGTCLK0_P" LOC = A10;
## NET "FPGAMGTCLK0_P" IOSTANDARD = "LVDS_12";
## NET "MGTSFPRX0_N" LOC = C7;
## NET "MGTSFPRX0_N" IOSTANDARD = "LVDS_12";
## NET "MGTSFPRX0_P" LOC = D7;
## NET "MGTSFPRX0_P" IOSTANDARD = "LVDS_12";
## NET "MGTSFPTX0_N" LOC = A6;
## NET "MGTSFPTX0_N" IOSTANDARD = "LVDS_12";
## NET "MGTSFPTX0_P" LOC = B6;
## NET "MGTSFPTX0_P" IOSTANDARD = "LVDS_12";
##======================================
##-- ADDITIONAL PINS
##======================================
##--
##-- + HC CMOS 3.3V input
##-------------------
NET "fpga_o_en" LOC = N4;
NET "fpga_o_en" IOSTANDARD = "LVCMOS33";
NET "fpga_o_en" DRIVE = "4";
NET "fpga_o_en" SLEW = "QUIETIO";
NET "fpga_o_en" PULLDOWN;
NET "fpga_o_blo_en" LOC = N3;
NET "fpga_o_blo_en" IOSTANDARD = "LVCMOS33";
NET "fpga_o_blo_en" DRIVE = "4";
NET "fpga_o_blo_en" SLEW = "QUIETIO";
NET "fpga_o_blo_en" PULLDOWN;
NET "fpga_o_ttl_en" LOC = M3;
NET "fpga_o_ttl_en" IOSTANDARD = "LVCMOS33";
NET "fpga_o_ttl_en" DRIVE = "4";
NET "fpga_o_ttl_en" SLEW = "QUIETIO";
NET "fpga_o_ttl_en" PULLDOWN;
NET "fpga_o_inv_en" LOC = P3;
NET "fpga_o_inv_en" IOSTANDARD = "LVCMOS33";
NET "fpga_o_inv_en" DRIVE = "4";
NET "fpga_o_inv_en" SLEW = "QUIETIO";
NET "fpga_o_inv_en" PULLDOWN;
##-------------------
##-- Motherboard and piggyback IDs
##--
##-- + ACT: CMOS 3.3V input
##-------------------
# NET "FPGA_RTMM[0]" LOC = V21;
# NET "FPGA_RTMM[0]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_RTMM[1]" LOC = V22;
# NET "FPGA_RTMM[1]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_RTMM[2]" LOC = U22;
# NET "FPGA_RTMM[2]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_RTMP[0]" LOC = W22;
# NET "FPGA_RTMP[0]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_RTMP[1]" LOC = Y22;
# NET "FPGA_RTMP[1]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_RTMP[2]" LOC = Y21;
# NET "FPGA_RTMP[2]" IOSTANDARD = "LVCMOS33";
##-------------------
##-- Configuration Switches
##
##-- Schematics name EXTRA_SWITCH_*
##---- renamed to EXTRA_SWITCH[*]
##-------------------
NET "switch_i" LOC = F22;
NET "switch_i" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[2]" LOC = G22;
# NET "EXTRA_SWITCH[2]" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[3]" LOC = H21;
# NET "EXTRA_SWITCH[3]" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[4]" LOC = H22;
# NET "EXTRA_SWITCH[4]" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[5]" LOC = J22;
# NET "EXTRA_SWITCH[5]" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[6]" LOC = K21;
# NET "EXTRA_SWITCH[6]" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[7]" LOC = K22;
# NET "EXTRA_SWITCH[7]" IOSTANDARD = "LVTTL";
NET "level" LOC = L22;
NET "level" IOSTANDARD = "LVTTL";
##-------------------
##-- ROM memory
##-------------------
# NET "FPGA_PROM_CCLK" LOC = Y20;
# NET "FPGA_PROM_CCLK" IOSTANDARD = "LVCMOS33";
# NET "FPGA_PROM_CSO_B_N" LOC = AA3;
# NET "FPGA_PROM_CSO_B_N" IOSTANDARD = "LVCMOS33";
# NET "FPGA_PROM_DIN" LOC = AA20;
# NET "FPGA_PROM_DIN" IOSTANDARD = "LVCMOS33";
# NET "FPGA_PROM_MOSI" LOC = AB20;
# NET "FPGA_PROM_MOSI" IOSTANDARD = "LVCMOS33";
##-------------------
##-- General purpose
##--
##-- + ACT: CMOS 3.3V input
##-------------------
## NET "FPGA_HEADER_IN[1]" LOC = A17;
## NET "FPGA_HEADER_IN[1]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN[2]" LOC = A18;
## NET "FPGA_HEADER_IN[2]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN[3]" LOC = B18;
## NET "FPGA_HEADER_IN[3]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN[4]" LOC = A19;
## NET "FPGA_HEADER_IN[4]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN[5]" LOC = A20;
## NET "FPGA_HEADER_IN[5]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN[6]" LOC = B20;
## NET "FPGA_HEADER_IN[6]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT[1]" LOC = F15;
## NET "FPGA_HEADER_OUT[1]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT[2]" LOC = F16;
## NET "FPGA_HEADER_OUT[2]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT[3]" LOC = F17;
## NET "FPGA_HEADER_OUT[3]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT[4]" LOC = F14;
## NET "FPGA_HEADER_OUT[4]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT[5]" LOC = H14;
## NET "FPGA_HEADER_OUT[5]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT[6]" LOC = H13;
## NET "FPGA_HEADER_OUT[6]" IOSTANDARD = "LVCMOS33";
hdl/basic_trigger/rtl/basic_trigger_core.vhd 0 → 100755
View file @ 9c48eb1b
---------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 09:58:06 10/12/2011
-- Design Name: HDL trigger
-- Module Name: trigger - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the wishbone trigger which receives a debounced input
-- and outputs a trigger signal for the pulse converter
-- Dependencies: none
--
-- Revision:
-- Revision 0.1
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.ctdah_pkg.ALL;
entity basic_trigger_core is
port (
wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
pulse_n_o : out STD_LOGIC;
led_o : out STD_LOGIC;
level_i : in STD_LOGIC --! 0 here means ttl
);
end basic_trigger_core;
architecture Behavioral of basic_trigger_core is
signal s_pulse : STD_LOGIC;
signal s_deglitched_pulse : STD_LOGIC;
signal s_deglitched_pulse_d0 : STD_LOGIC;
signal s_monostable : STD_LOGIC;
begin
s_pulse <= pulse_i;
inst_debo: gc_debouncer
generic map( g_LENGTH => 2)
port map(rst => wb_rst_i,
clk => wb_clk_i,
input => s_pulse,
output => s_deglitched_pulse,
glitch_mask => "11");
pulse_monostable : gc_simple_monostable
generic map (g_PULSE_LENGTH => 20)
port map (rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => pulse_o,
output_n => pulse_n_o);
led_monostable : gc_simple_monostable
generic map (g_PULSE_LENGTH => 100000000) --! 500ms
port map (
rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => led_o);
--output_n not connected
end Behavioral;
hdl/basic_trigger/rtl/basic_trigger_top.vhd 0 → 100755
View file @ 9c48eb1b
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 09:58:06 10/12/2011
-- Design Name: HDL trigger top
-- Module Name: trigger - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the wishbone trigger which receives a input
-- and outputs a trigger signal for the pulse converter.
-- It internally debounces the inputs and control the output
-- driver.
-- The registers it has can be modified via wishbone access.
-- Dependencies: none
--
-- Revision:
-- Revision 0.1
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity basic_trigger_top is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (
clk_i : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--! WR LEDs not to let them ON
led_link_up_o : out STD_LOGIC;
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1));
end basic_trigger_top;
architecture Behavioral of basic_trigger_top is
signal s_pulse_i : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_i_rear : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_i_front : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_o : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_n_o : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_led : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_level : STD_LOGIC;
signal s_fpga_o_en : STD_LOGIC;
signal s_fpga_o_ttl_en : STD_LOGIC;
signal s_fpga_o_inv_en : STD_LOGIC;
signal s_fpga_o_blo_en : STD_LOGIC;
signal s_rst : STD_LOGIC_VECTOR(7 downto 0) := (others => '1');
component basic_trigger_core is
port (wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
pulse_n_o : out STD_LOGIC;
led_o : out STD_LOGIC;
level_i : in STD_LOGIC);
end component;
begin
s_level <= level;
led_pw_o <= '0';
led_err_o <= '1';
led_ttl_o <= s_level;
led_link_up_o <= '1';
led_pps_o <= '1';
led_wr_ok_o <= '1';
s_pulse_i_front <= pulse_i_front when s_level = '0' else not(pulse_i_front);
s_pulse_i <= s_pulse_i_front or pulse_i_rear;
fpga_o_en <= s_fpga_o_en when switch_i = '1' else '0';
fpga_o_ttl_en <= s_fpga_o_ttl_en;
fpga_o_inv_en <= s_fpga_o_inv_en;
fpga_o_blo_en <= s_fpga_o_blo_en;
led_o_front <= not(s_led);--! No need of accurate sync, hence we place
led_o_rear <= not(s_led);--! some combinatorial here.
inv_o <= inv_i;--! As we have one Schmitt inverter in the input,
--! and a buffer in the output, there's no need
--! of invert here.
i_repetitors: for i in 1 to g_NUMBER_OF_CHANNELS generate
begin
trigger: basic_trigger_core
port map (
wb_rst_i => s_rst(7),
wb_clk_i => clk_i,
pulse_i => s_pulse_i(i),
pulse_o => s_pulse_o(i),
pulse_n_o => s_pulse_n_o(i),
led_o => s_led(i),
level_i => '0');
end generate i_repetitors;
p_reset_chain : process(clk_i) is
begin
if rising_edge(clk_i) then
s_rst(0) <= '0';
for i in 1 to 7 loop
s_rst(i) <= s_rst(i-1);
end loop;
if s_rst(7) = '1' then
--! First we reset the FPGA general output enable
--! Then we let one clock delay for the rest of signals
manual_rst_n_o <= '0';
s_fpga_o_en <= '0';
s_fpga_o_ttl_en <= '0';
s_fpga_o_inv_en <= '0';
s_fpga_o_blo_en <= '0';
else
manual_rst_n_o <= '1';
s_fpga_o_en <= '1';
s_fpga_o_ttl_en <= s_fpga_o_en;
s_fpga_o_inv_en <= s_fpga_o_en;
s_fpga_o_blo_en <= s_fpga_o_en;
end if;
end if;
end process p_reset_chain;
--! We register the outputs for better synchronization of the outputs
p_reg_output : process(clk_i) is
begin
if rising_edge(clk_i) then
if s_rst(7) = '1' then
pulse_o_rear <= (others => '0');
if s_level = '0' then
pulse_o_front <= (others => '0');
else
pulse_o_front <= (others => '1');
end if;
else
pulse_o_rear <= s_pulse_o;
case s_level is
when '0' =>
pulse_o_front <= s_pulse_o;
when others =>
pulse_o_front <= s_pulse_n_o;
end case;
end if;
end if;
end process;
end Behavioral;
hdl/basic_trigger/test/basic_trigger_top_tb.vhd 0 → 100755
View file @ 9c48eb1b
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY trigger_top_tb IS
END trigger_top_tb;
ARCHITECTURE behavior OF trigger_top_tb IS
constant c_NUMBER_OF_CHANNELS : NATURAL := 6;
constant CLK_PERIOD : time := 50 ns;
signal s_clk : STD_LOGIC;
-- signal s_rst : STD_LOGIC;
signal led_pw_o : STD_LOGIC;
signal led_err_o : STD_LOGIC;
signal led_ttl_o : STD_LOGIC;
signal fpga_o_en : STD_LOGIC;
signal fpga_o_ttl_en : STD_LOGIC;
signal fpga_o_inv_en : STD_LOGIC;
signal fpga_o_blo_en : STD_LOGIC;
signal level_i : STD_LOGIC;
signal switch_i : STD_LOGIC;
signal manual_rst_n_o : STD_LOGIC;
signal pulse_i_front : STD_LOGIC_VECTOR(c_NUMBER_OF_CHANNELS - 1 downto 0);
signal pulse_o_front : STD_LOGIC_VECTOR(c_NUMBER_OF_CHANNELS - 1 downto 0);
signal pulse_i_rear : STD_LOGIC_VECTOR(c_NUMBER_OF_CHANNELS - 1 downto 0);
signal pulse_o_rear : STD_LOGIC_VECTOR(c_NUMBER_OF_CHANNELS - 1 downto 0);
signal led_o : STD_LOGIC_VECTOR(c_NUMBER_OF_CHANNELS - 1 downto 0);
signal led_link_up_o : STD_LOGIC;
signal led_pps_o : STD_LOGIC;
signal led_wr_ok_o : STD_LOGIC;
signal inv_i : STD_LOGIC_VECTOR(3 downto 0);
signal inv_o : STD_LOGIC_VECTOR(3 downto 0);
component basic_trigger_top is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (
clk_i : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level_i : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS - 1 downto 0);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS - 1 downto 0);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS - 1 downto 0);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS - 1 downto 0);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS - 1 downto 0);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS - 1 downto 0);
--! WR LEDs not to let them ON
led_link_up_o : out STD_LOGIC;
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
inv_i : in STD_LOGIC_VECTOR(3 downto 0);
inv_o : out STD_LOGIC_VECTOR(3 downto 0));
end component;
begin
uut: basic_trigger_top
port map(
clk_i => s_clk,
-- rst_i => s_rst,
led_pw_o => led_pw_o,
led_err_o => led_err_o,
led_ttl_o => led_ttl_o,
fpga_o_en => fpga_o_en,
fpga_o_ttl_en => fpga_o_ttl_en,
fpga_o_inv_en => fpga_o_inv_en,
fpga_o_blo_en => fpga_o_blo_en,
level_i => level_i,
switch_i => switch_i,
manual_rst_n_o => manual_rst_n_o ,
pulse_i_front => pulse_i_front,
pulse_o_front => pulse_o_front,
pulse_i_rear => pulse_i_rear,
pulse_o_rear => pulse_o_rear,
led_o_front => led_o,
led_o_rear => led_o,
led_link_up_o => led_link_up_o,
led_pps_o => led_pps_o,
led_wr_ok_o => led_wr_ok_o,
inv_i => inv_i,
inv_o => inv_o);
s_clk_process :process
begin
s_clk <= '1';
wait for CLK_PERIOD/2;
s_clk <= '0';
wait for CLK_PERIOD/2;
end process;
tb_proc: process
procedure initial_cond(level : STD_LOGIC) is
begin
-- s_rst <= '1';
switch_i <= '0';
inv_i <= (others => '0');
pulse_i_front <= (others => level);
pulse_i_rear <= (others => '0');
level_i <= level;
wait for CLK_PERIOD*50;
-- s_rst <= '0';
wait for CLK_PERIOD*2;
wait until rising_edge(s_clk);
end;
procedure input_pulse (signal pulse : out
STD_LOGIC_VECTOR(c_NUMBER_OF_CHANNELS - 1 downto 0);
channel: NATURAL;
length : time;
level : STD_LOGIC) is
variable v_pulse : STD_LOGIC := level;
begin
pulse(channel) <= level;
wait until rising_edge(s_clk);
pulse(channel) <= not(level);
wait for length;
pulse(channel) <= level;
wait until rising_edge(s_clk);
end;
procedure input_front_pulse (length : time; channel : NATURAL;
level : STD_LOGIC) is
begin
input_pulse (pulse_i_front, channel, length, level);
end;
procedure input_rear_pulse (length : time; channel : NATURAL) is
begin
input_pulse (pulse_i_rear, channel, length, '0');
end;
procedure input_two_pulses (channel : NATURAL; level : STD_LOGIC;
length1 : time;
length2 : time;
offset : time) is
begin
pulse_i_front(channel) <= level;
pulse_i_rear(channel) <= '0';
wait until rising_edge(s_clk);
pulse_i_rear(channel) <= '1';
wait for offset;
wait until rising_edge(s_clk);
pulse_i_front(channel) <= not(level);
wait for length1 - offset;
wait until rising_edge(s_clk);
pulse_i_rear(channel) <= '0';
wait for length2 - length1;
wait until rising_edge(s_clk);
pulse_i_front(channel) <= level;
wait until rising_edge(s_clk);
end;
begin
-- input_front_pulse (1200 ns, 0, '1');
--! First we put one pulse from the Blocking part, then we wait one-clock
--! and lastly we put another clock from the TTL input
initial_cond('0');
input_rear_pulse (1200 ns, 0);
wait until rising_edge(s_clk);
input_front_pulse (1200 ns, 0, level_i);
wait for 40*CLK_PERIOD;
--! We reboot the machine and change the switch to indicate level_i is
--! TTL_N
initial_cond('1');
input_rear_pulse (1200 ns, 0);
wait until rising_edge(s_clk);
input_front_pulse (1200 ns, 0, level_i);
input_two_pulses(0, '1',
1000 ns,
1000 ns,
212 ns);
wait for 40*CLK_PERIOD;
assert false report "End of test." severity failure;
end process;
end;
hdl/basic_trigger/wave.do 0 → 100755
View file @ 9c48eb1b
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /trigger_top_tb/s_clk
add wave -noupdate -group {Output enable} /trigger_top_tb/fpga_o_blo_en
add wave -noupdate -group {Output enable} /trigger_top_tb/fpga_o_en
add wave -noupdate -group {Output enable} /trigger_top_tb/fpga_o_inv_en
add wave -noupdate -group {Output enable} /trigger_top_tb/fpga_o_ttl_en
add wave -noupdate -group {Output enable} /trigger_top_tb/fpga_o_blo_en
add wave -noupdate -group {Output enable} /trigger_top_tb/fpga_o_en
add wave -noupdate -group {Output enable} /trigger_top_tb/fpga_o_inv_en
add wave -noupdate -group {Output enable} /trigger_top_tb/fpga_o_ttl_en
add wave -noupdate -group LEDs /trigger_top_tb/led_o
add wave -noupdate -group LEDs /trigger_top_tb/led_pw_o
add wave -noupdate -group LEDs /trigger_top_tb/led_err_o
add wave -noupdate -group LEDs /trigger_top_tb/led_ttl_o
add wave -noupdate -group LEDs /trigger_top_tb/led_o
add wave -noupdate -group LEDs /trigger_top_tb/led_pw_o
add wave -noupdate -group LEDs /trigger_top_tb/led_err_o
add wave -noupdate -group LEDs /trigger_top_tb/led_ttl_o
add wave -noupdate /trigger_top_tb/switch_i
add wave -noupdate /trigger_top_tb/level_i
add wave -noupdate /trigger_top_tb/pulse_i_front
add wave -noupdate /trigger_top_tb/pulse_i_rear
add wave -noupdate /trigger_top_tb/pulse_o_front
add wave -noupdate /trigger_top_tb/pulse_o_rear
add wave -noupdate /trigger_top_tb/uut/s_pulse_i
add wave -noupdate /trigger_top_tb/uut/s_pulse_i_rear
add wave -noupdate /trigger_top_tb/uut/s_pulse_i_front
add wave -noupdate /trigger_top_tb/s_clk
add wave -noupdate /trigger_top_tb/switch_i
add wave -noupdate /trigger_top_tb/level_i
add wave -noupdate /trigger_top_tb/pulse_i_front
add wave -noupdate /trigger_top_tb/pulse_i_rear
add wave -noupdate /trigger_top_tb/pulse_o_front
add wave -noupdate /trigger_top_tb/pulse_o_rear
add wave -noupdate /trigger_top_tb/uut/s_pulse_i
add wave -noupdate /trigger_top_tb/uut/s_pulse_i_rear
add wave -noupdate /trigger_top_tb/uut/s_pulse_i_front
add wave -noupdate /trigger_top_tb/uut/s_rst
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {5128424 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {14175 ns}
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