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Conv TTL Blocking
Commit a63e5773 authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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Added all the files merged from i2c_upgrade branch

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hdl/m25p32/project/m25p32.xise 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
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<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
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<file xil_pn:name="../../spi_master_multifield/rtl/spi_master_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ctdah_lib/rtl/FIFO_dispatcher.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../test/m25p32_top_tb.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../spi_master_multifield/test/spi_analyser_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../spi_master_multifield/test/spi_analyser.vhd" xil_pn:type="FILE_VHDL">
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<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
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<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
hdl/multiboot/doc/multiboot.tex 0 → 100644
View file @ a63e5773
%%This is a very basic article template.
%%There is just one section and two subsections.
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\begin{document}
\title{\textbf{CONV-TTL-BLO \\ Multiboot HDL module}}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{February 23, 2012}
\maketitle
\begin{abstract}
The \textit{multiboot module} is in charge of configuring multibooting
capability and assert the reprogramming of the FPGA.
This document shows:
\begin{itemize}
\item Parameters used as \textit{generic}
\item The registers to control the module.
\item Step-by-step instructions for proper use.
\end{itemize}
\end{abstract}
\vspace{2cm}
\begin{center}
\begin{tabular}{|p{2.5cm}|p{3.5cm}|p{3cm}|}
\hline
\multicolumn{3}{|c|}{\textbf{Revision history}}\\
\hline
\hline
\textbf{HDL version} & \textbf{Module} & \textbf{Date}\\
\hline
0.1 & Multiboot manager & February 23, 2012\\
\hline
\end{tabular}
\end{center}
\pagebreak
\tableofcontents
\pagebreak
\section{Structure}
\begin{tabular}{|l|}
\hline
\textit{NOTE1:} this module is platform specific. It only works with Spartan
6\\
\hline
\textit{NOTE2:} in case the EEPROM memory is replaced, SPI opcode will\\ change.
User should notice this issue.\\
\hline
\end{tabular}\\
The trigger module contains sever
blocks related the following way:\\
-- \textbf{\textit{multiboot\_top.vhd}}
----- \textbf{multiboot\_regs.vhd}
----- \textbf{multiboot\_core.vhd}
--------- ICAP\_SPARTAN6 (\textit{Xilinx primitive})
\subsection{\textit{multiboot\_top.vhd}}
The top file of the module. It interconnects the Wishbone to internal register
module, \textit{multiboot\_regs.vhd}, to the core logic in
\textit{multiboot\_core.vhd}.
No \textit{generics} are implemented in this HDL module.
\subsection{multiboot\_regs.vhd}
In this module the registers neeeded for specifiying the memory addresses in
which the FPGA must boot to are defined.
An internal register is defined for selectively controlling operations to be
performed by this module (full ICAP reprogramming process, issuing ICAP
commands, refreshing ICAP registers). The set of operations that can be issued
is restricted for security reasons. The allowed operations are further listed in
the \textit{Register subsection}.
\subsection{multiboot\_core.vhd}
It is responsible of accessing ICAP port through the internal
\textit{ICAP\_SPARTAN6 Xilinx primitive}. A finite state machine is implemented
in accordance to Chapter 7 of \cite{UG380}.
\subsection{Behaviour}
Following the instructions of \cite{UG380} strictly leads to correct multiboot
of the FPGA. Firstly, registers \textit{GENERAL1}, \textit{GENERAL2},
\textit{GENERAL3} and \textit{GENERAL4} must be programmed with valid values. It
should be keept in mind that the \textit{SPI opcode} in \textit{GENERAL4}
register depends on the \textit{EEPROM chip} mounted on the board.\\
Then, a \textit{full multiboot} command must be performed via ICAP interface
through a write in \textit{CTRL} register in \textit{multiboot module}.
\section{Parameters}
No \textit{generic} parameters are offered in this module.
\section{Registers}
\subsection{CTRL}
The \textit{CTRL} register is a read-write register for \textit{OP} field and a
read-only for \textit{PEND} bit.
It specifies the operations that can be controlled by an user.\\
\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
3-0 & OP & OPeration to be performed \\
\hline
4 & PEND & operation PENDing \\
\hline
\end{tabular}\\
Whenever an operation is specified by the user, it is passed to ICAP Xilinx
primitive through \textit{multiboot\_core.vhd} and the bit flag \textit{PEND} is
set to '1' until it is completely finished.
\subsubsection{Operations}
The valid operations that can be requested are the following:\\
\begin{tabular}{| c | l |}
\hline
\textbf{OP byte} & \textbf{Operation}\\
\hline
\hline
0x0 & \textbf{Full multiboot process} as specified in \cite{UG380}\\
\hline
0x1 & \textbf{Write GENERAL1} register from \\
& \textit{multiboot\_regs.vhd} into FPGA\\
\hline
0x2 & \textbf{Write GENERAL2} register from \\
& \textit{multiboot\_regs.vhd} into FPGA\\
\hline
0x3 & \textbf{Write GENERAL3} register from \\
& \textit{multiboot\_regs.vhd} into FPGA\\
\hline
0x4 & \textbf{Write GENERAL4} register from \\
& \textit{multiboot\_regs.vhd} into FPGA\\
\hline
0x7 & Perform \textbf{IPROG command}\\
\hline
0xD & \textbf{Refresh STAT} register\\
& into \textit{multiboot\_regs.vhd} \\
\hline
\end{tabular}\\
Full multiboot process, \textit{OP} = 0x0, comprises commamnds:
\begin{enumerate}
\item \textit{OP} = 0x1
\item \textit{OP} = 0x2
\item \textit{OP} = 0x3
\item \textit{OP} = 0x4
\item \textit{OP} = 0x7
\end{enumerate}
\subsection{STAT}
The \textit{STAT} register is a read-only register. A \textit{refresh operation}
should be completed before retrieving correct \textit{STAT} information.\\
\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & CRC\_ERROR & CRC ERROR detected in bitstream\\
\hline
1 & ID\_ERROR & IDCODE not validated\\
\hline
2 & DCM\_LOCK & DCMs and PLL are locked \\
\hline
3 & GTS\_CFG\_B & Global tristate\\
\hline
4 & GWE & Global Write Enable\\
\hline
5 & GHIGH\_B & GHIGH\\
\hline
6 & DEC\_ERROR & DEC\_ERROR\\
\hline
7 & PART\_SECURED & Decryption is set\\
\hline
8 & HSWAPEN & HWSAPEN\\
\hline
11-9 & MODE & MODE pins\\
\hline
12 & INIT\_B & INIT\_B\\
\hline
13 & DONE & DONE input pins\\
\hline
14 & IN\_PWRDWN & suspend status\\
\hline
15 & SWWD\_STRIKEOUT & config error because of invalid sync\\
\hline
\end{tabular}\\
\subsection{GENERAL1}
Bit scrambling is done in VHDL code. Bit order must be as specified below:\\
\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
15-0 & MBT\_ADDR\_L & MultiBoot image ADDRess Lower half\\
\hline
\end{tabular}\\
\subsection{GENERAL2}
Bit scrambling is done in VHDL code. Bit order must be as specified below:\\
\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
7-0 & MBT\_ADDR\_L & Multiboot image ADDRess Lower Half\\
\hline
15-8 & SPIO & SPI Opcode\\
\hline
\end{tabular}\\
\subsection{GENERAL3}
Bit scrambling is done in VHDL code. Bit order must be as specified below:\\
\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
15-0 & GLD\_ADDR\_L & GolDen image ADDRess Lower half\\
\hline
\end{tabular}\\
\subsection{GENERAL4}
Bit scrambling is done in VHDL code. Bit order must be as specified below:\\
\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
7-0 & GLD\_ADDR\_H & GoLDen image ADDRess Higher Half\\
\hline
15-8 & SPIO & SPI Opcode\\
\hline
\end{tabular}\\
\section{Internal Memory Mapping}
The Internal Memory Mapping is as follows:\\
\begin{tabular}{| c | c | c |}
\hline
\textbf{Address} & \textbf{Register} & \textbf{Access} \\
\hline
\hline
\textbf{0x0} & \textit{CTRL} & Read-only\\
\hline
\textbf{0x1} & \textit{STAT} & See \textit{STAT} description\\
\hline
\textbf{0x2} & \multicolumn{2}{l|}{Not used}\\
\hline
\textbf{0x3} & \multicolumn{2}{l|}{Not used}\\
\hline
\textbf{0x4} & \textit{GENERAL1} & Read-write\\
\hline
\textbf{0x5} & \textit{GENERAL2} & Read-write\\
\hline
\textbf{0x6} & \textit{GENERAL3} & Read-only\\
\hline
\textbf{0x7} & \textit{GENERAL4} & Read-write\\
\hline
\end{tabular}
\section{How to use it}
It requieres three parameters to be specified:
\begin{itemize}
\item Address of the Golden Image
\item Address of the Multiboot Image
\item SPI Opcode of the EEPROM serial interface
\end{itemize}
Bad specifications of addresses will not reprogram the FPGA.
\subsection{Submitting ICAP instructions}
It can be either a two-step or a single-step process. Two-step processes are
related with changes in \textit{GENERAL[X]} register. Submitting an ICAP
command is a single-step-process (\textit{IPROG} instruction, for instance).
\begin {itemize}
\item[\textbf{Example A:}]\\
\textbf{Full Multiboot Configuration}\\
This is a scenario is useful when the EEPROM memory map has changed for
the allocation of the two FPGA bitstreams.
\begin {enumerate}
\item Write \textit{GENERAL1} register.
\item Write \textit{GENERAL2} register.
\item Write \textit{GENERAL3} register.
\item Write \textit{GENERAL4} register.
\item Write \textit{CTRL} register.\\
\textit{CTRL} should issue a \textbf{Full multiboot process} operation code
(0x0).
\end {enumerate}
\item[\textbf{Example B:}]\\
\textbf{Change an individual Boot Look Up Address}\\
This is a scenario is useful when the EEPROM memory map has changed for
the allocation of only one of the FPGA bitstreams.
\begin {enumerate}
\item Write \textit{GENERAL[X]} register. Where X={1,3}
\item Write \textit{GENERAL[X+1]} register.
\item Write \textit{CTRL} register.\\
\textit{CTRL} should issue a \textbf{Write GENERAL[X]} operation code.
\item Write \textit{CTRL} register.\\
\textit{CTRL} should issue a \textbf{Write GENERAL[X+1]} operation code.
\end {enumerate}
\item[\textbf{Example C:}]\\
\textbf{Reprogram FPGA without change in Bitstream Location}\\
If the EEPROM memory map has not changed but we want to reload one of the
images, we just issue an \textit{IPROG} instruction through the \textit{ICAP}
interface.
\begin {enumerate}
\item Write \textit{CTRL} register.\\
\textit{CTRL} should issue an \textbf{IPROG} operation code(0x7).
\end {enumerate}
\end {itemize}
\pagebreak
\bibliographystyle{unsrt}
\bibliography{multiboot}
\end{document}
hdl/multiboot/project/multiboot.xise 0 → 100644
View file @ a63e5773
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<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|multiboot_core_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="multiboot" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-02-20T11:49:04" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="32435B4919B3D988E6F9BAE3046A86A5" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
hdl/multiboot/project/wave.do 0 → 100644
View file @ a63e5773
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -radix hexadecimal /multiboot_core_tb/rst
add wave -noupdate -radix hexadecimal /multiboot_core_tb/clk
add wave -noupdate -radix hexadecimal /multiboot_core_tb/CTRL0_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/CTRL1_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/STAT_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL1_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL2_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL3_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL4_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL1_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL2_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL3_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL4_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/multiboot_fsm
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/readback_fsm
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_busy_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_o_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_ce_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_i_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_write_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/op_cycles
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1750000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {1057409 ps} {1887747 ps}
pcb/doc/report/16nov.txt 0 → 100644
View file @ a63e5773
-------------------------------------------------------------------------------
CONV-TTL-BLO v2 layout review 16.11.2012
-------------------------------------------------------------------------------
MEETING SUMMARY
+ DATE 16.11.2012 15:30 - 17:00
+ PLACE CERN Prevessin, Building 864, Room 1-A11
+ SUBJECT CONV-TTL-BLO v2 Layout Review
+ SVN http://www.ohwr.org/projects/conv-ttl-blo/wiki
+ REVISION 1
+ PARTICIPANTS:
Van der Bij, Erik EVB Erik.van.der.Bij@cern.ch
Cattin, Matthieu MC matthieu.cattin@cern.ch
Gil Soriano, Carlos CGS carlos.gil.soriano@cern.ch
+ SUMMARY
The goal of the meeting is to correct the errors found in the layout of
CONV-TTL-BLO v2 received from DEM
===============================================================================
| ! : fatal |
| + : important |
| - : minor |
| ? : question |
| * : note |
===============================================================================
===============================================================================
FRONT PANEL
SCHEMATICS
+ ConvTtlBlo_TOP.SchDoc
--+ FPGAps.SchDoc
--+ PowerSupplyBlocking.SchDoc
--+ FPGAbank.SchDoc
--+ Clocks&Monitor.SchDoc
--+ Communication.SchDoc
--+ JTAG&Button.SchDoc
--+ VME64xConn.SchDoc
--+ InputBlocking.SchDoc
----+ InputBlockingUnit.SchDoc
--+ BlockingOutput.SchDoc
----+ BlockingUnit.SchDoc
--+ FrontPanelLeds.SchDoc
--+ FrontTTL.SchDoc
--> BOM
LAYOUT
===============================================================================
===============================================================================
--------------------------------------
FRONT PANEL
--------------------------------------
[EVB] - Change the Front panel serigraphy:
"MULTICAST" -> "MULTICAST ADDR"
"3 2 1 0" -> "8 4 2 1"
--------------------------------------
===============================================================================
===============================================================================
SCHEMATICS
--------------------------------------
General:
--------------------------------------
[CGS] * All the footboxes are correct.
[CGS] * Compilation is OK. No errors.
--------------------------------------
--------------------------------------
ConvTtlBlo_TOP.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
FPGAps.SchDoc
--------------------------------------
[CGS] * 24V testpoint added since submission to DEM.
--------------------------------------
--------------------------------------
PowerSupplyBlocking.SchDoc
--------------------------------------
[CGS] * T19 has been replaced due to lack of long-term stock.
--------------------------------------
--------------------------------------
FPGAbank.SchDoc
--------------------------------------
[CGS] * FPGA_BLO_IN connected correctly for SerDes
FPGA_TRIG_BLO connected correctly for SerDes
FPGA_INPUT_TTL_N connected correctly for SerDes
INV_IN_N connected correctly for SerDes
INV_OUT_N connected correctly for SerDes
--------------------------------------
--------------------------------------
Clocks&Monitor.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
Communication.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
JTAG&Button.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
VME64xConn.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
InputBlocking.SchDoc
--------------------------------------
[CGS] * Bruno moved out the open
collector resistor to this page.
-------------------------------------
--------------------------------------
InputBlockingUnit.SchDoc
--------------------------------------
[CGS] * Bruno moved out the open
collector resistor from this page.
--------------------------------------
--------------------------------------
BlockingOutput.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
BlockingUnit.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
FrontTTL.SchDoc
--------------------------------------
[CGS] * Small clean-up from Bruno.
Removed not necessary extra
caps.
--------------------------------------
--------------------------------------
FrontPanelLeds.SchDoc
--------------------------------------
[CGS] * I think it is correct. However,
recheck it.
--> OK
Easiest arrangement for HDL?
--------------------------------------
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
BOM
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
===============================================================================
LAYOUT
===============================================================================
*** STACKUP**
1- TOP
2- L2GND
3- L3
4- L4PWR
5- L5PWR
6- L6
7- L7GND
8- BOTTOM
--------------------------------------
General
--------------------------------------
[CGS] * Track length well adapted.
* Correct stackp and height.
! Move array LEDs a little bit
inside so as to fit with new
front panel.
- Legend not inte.. Ask DEM
what is this for.
--------------------------------------
--------------------------------------
Top Overlay
--------------------------------------
[CGS] * No overlaps.
- Check sticked box.
- Put a line to bit 8 to TTL
switch.
+ Put big sticker in the back.
--------------------------------------
--------------------------------------
Top Layer
--------------------------------------
[CGS] * Power supply area was extended
due to adding the 5V rail and
the fuses.
--------------------------------------
--------------------------------------
L2GND
--------------------------------------
--------------------------------------
--------------------------------------
L3
--------------------------------------
[CGS] * No plane cross in HS lines.
--------------------------------------
--------------------------------------
L4PWR
--------------------------------------
[CGS] * Added here the 5V rail.
--------------------------------------
--------------------------------------
L5PWR
--------------------------------------
[MC] * Make bigger 24V
--------------------------------------
--------------------------------------
L6
--------------------------------------
[CGS] * No plane cross in HS lines.
--------------------------------------
--------------------------------------
L7GND
--------------------------------------
--------------------------------------
--------------------------------------
BOTTOM
--------------------------------------
[CGS] * No overlaps.
--------------------------------------
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