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Conv TTL Blocking
Commit a6b105fd authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Switching branches to compare trigger cores. Compiled image1 project, repetition not working.

parent b9e138fd
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Showing with 198 additions and 313 deletions
hdl/IMAGES/image1/constraints/V2/BloV2.ucf
View file @ a6b105fd
......@@ -8,14 +8,16 @@
NET "RST_N" LOC = N20;
NET "RST_N" IOSTANDARD = "LVTTL";
#NET "FPGA_SYSRESET_N" LOC = L20;
NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = "LVTTL";
NET "CLK20_VCXO" LOC = E16;
TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50%;
NET "FPGA_CLK_N" LOC = H11;
NET "FPGA_CLK_P" LOC = G11;
NET "FPGA_CLK_P" LOC = H12;
NET "FPGA_CLK_N" LOC = G11;
##======================================
......@@ -26,15 +28,34 @@ NET "FPGA_CLK_P" LOC = G11;
##-- + UBT: LVTTL input
##-------------------
NET "LED_CTRL0" LOC = M18;
NET "LED_CTRL0" IOSTANDARD = "LVTTL";
NET "LED_CTRL0_OEN" LOC = T20;
NET "LED_CTRL0_OEN" IOSTANDARD = "LVTTL";
NET "LED_CTRL1" LOC = M17;
NET "LED_CTRL1" IOSTANDARD = "LVTTL";
NET "LED_CTRL1_OEN" LOC = U19;
NET "LED_CTRL1_OEN" IOSTANDARD = "LVTTL";
NET "LED_MULTICAST_2_0" LOC = P16;
NET "LED_MULTICAST_2_0" IOSTANDARD = "LVTTL";
NET "LED_MULTICAST_3_1" LOC = P17;
NET "LED_MULTICAST_3_1" IOSTANDARD = "LVTTL";
NET "LED_WR_GMT_TTL_TTLN" LOC = N16;
NET "LED_WR_GMT_TTL_TTLN" IOSTANDARD = "LVTTL";
NET "LED_WR_LINK_SYSERROR" LOC = R15;
NET "LED_WR_LINK_SYSERROR" IOSTANDARD = "LVTTL";
NET "LED_WR_OK_SYSPW" LOC = R16;
NET "LED_WR_OK_SYSPW" IOSTANDARD = "LVTTL";
NET "LED_WR_OWNADDR_I2C" LOC = N15;
NET "LED_WR_OWNADDR_I2C" IOSTANDARD = "LVTTL";
##-------------------
##-- Front channel LEDs
##--
......
hdl/IMAGES/image1/project/image1.gise
View file @ a6b105fd
......@@ -23,174 +23,90 @@
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="image1_top.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="image1_top.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="image1_top.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="image1_top.cmd_log"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="image1_top.fdo"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="image1_top.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="image1_top.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="image1_top.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="image1_top.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="image1_top.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="image1_top.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="image1_top.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="image1_top.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="image1_top.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="image1_top.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="image1_top.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="image1_top.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="image1_top.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="image1_top.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="image1_top.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="image1_top.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="image1_top.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="image1_top.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="image1_top.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="image1_top_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="image1_top_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="image1_top_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="image1_top_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="image1_top_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="image1_top_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="image1_top_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="image1_top_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="image1_top_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="image1_top_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="image1_top_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_xst.xrpt"/>
<<<<<<< HEAD
=======
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_LOG" xil_pn:name="vsim.wlf"/>
>>>>>>> 15f461cc70ccb4f36a23fc49acc82d45b5f9de6f
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<<<<<<< HEAD
<transform xil_pn:end_ts="1359733038" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1359733038">
<transform xil_pn:end_ts="1360077197" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1360077197">
<status xil_pn:value="SuccessfullyRun"/>
</transform>
<transform xil_pn:end_ts="1359733038" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1112065682908869959" xil_pn:start_ts="1359733038">
<transform xil_pn:end_ts="1360077197" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1112065682908869959" xil_pn:start_ts="1360077197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1359733038" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1359733038">
<transform xil_pn:end_ts="1360077197" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1360077197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1359733038" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1359733038">
<transform xil_pn:end_ts="1360077197" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1360077197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1359733038" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6110598410798097591" xil_pn:start_ts="1359733038">
<transform xil_pn:end_ts="1360077197" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6110598410798097591" xil_pn:start_ts="1360077197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1359733038" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1359733038">
=======
<transform xil_pn:end_ts="1359108425" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1359108425">
<status xil_pn:value="SuccessfullyRun"/>
</transform>
<transform xil_pn:end_ts="1359109243" xil_pn:in_ck="-7672365651252725296" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1359109243">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd"/>
<outfile xil_pn:name="../../../../../general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"/>
<outfile xil_pn:name="../../../../../general-cores/modules/wishbone/wishbone_pkg.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd"/>
<outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd"/>
<outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_debounce.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_tb_pkg.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_core.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_top.vhd"/>
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd"/>
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_core.vhd"/>
<outfile xil_pn:name="../rtl/image1_led_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_wrappers_pkg.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
<outfile xil_pn:name="../top/image1_top.vhd"/>
</transform>
<transform xil_pn:end_ts="1359108983" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="239257099518693425" xil_pn:start_ts="1359108983">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1359108983" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-3020523367752079697" xil_pn:start_ts="1359108983">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1359108425" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1359108425">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1359109243" xil_pn:in_ck="-7672365651252725296" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1359109243">
<transform xil_pn:end_ts="1360077197" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1360077197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd"/>
<outfile xil_pn:name="../../../../../general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"/>
<outfile xil_pn:name="../../../../../general-cores/modules/wishbone/wishbone_pkg.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd"/>
<outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd"/>
<outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_debounce.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_tb_pkg.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_core.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_top.vhd"/>
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd"/>
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_core.vhd"/>
<outfile xil_pn:name="../rtl/image1_led_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_wrappers_pkg.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
<outfile xil_pn:name="../top/image1_top.vhd"/>
</transform>
<transform xil_pn:end_ts="1359109244" xil_pn:in_ck="-7672365651252725296" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1359109243">
>>>>>>> 15f461cc70ccb4f36a23fc49acc82d45b5f9de6f
<transform xil_pn:end_ts="1360077197" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8460592660931398612" xil_pn:start_ts="1360077197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<<<<<<< HEAD
<transform xil_pn:end_ts="1359733038" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8460592660931398612" xil_pn:start_ts="1359733038">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1359734187" xil_pn:in_ck="-1823852009266447159" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1359734101">
<transform xil_pn:end_ts="1360078715" xil_pn:in_ck="4009373323416370228" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1360078640">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="image1_top.lso"/>
<outfile xil_pn:name="image1_top.ngc"/>
......@@ -203,26 +119,73 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1359733124" xil_pn:in_ck="-6619133686387830372" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1359733124">
<transform xil_pn:end_ts="1360077789" xil_pn:in_ck="-6700002251458007206" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1360077789">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1359734197" xil_pn:in_ck="5852800249754258408" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1359734187">
<status xil_pn:value="FailedRun"/>
<transform xil_pn:end_ts="1360078726" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1360078715">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="image1_top.bld"/>
<outfile xil_pn:name="image1_top.ngd"/>
<outfile xil_pn:name="image1_top_ngdbuild.xrpt"/>
</transform>
=======
>>>>>>> 15f461cc70ccb4f36a23fc49acc82d45b5f9de6f
<transform xil_pn:end_ts="1360078988" xil_pn:in_ck="-662876564851204569" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1360078726">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="image1_top.pcf"/>
<outfile xil_pn:name="image1_top_map.map"/>
<outfile xil_pn:name="image1_top_map.mrp"/>
<outfile xil_pn:name="image1_top_map.ncd"/>
<outfile xil_pn:name="image1_top_map.ngm"/>
<outfile xil_pn:name="image1_top_map.xrpt"/>
<outfile xil_pn:name="image1_top_summary.xml"/>
<outfile xil_pn:name="image1_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1360079142" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1360078988">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="image1_top.ncd"/>
<outfile xil_pn:name="image1_top.pad"/>
<outfile xil_pn:name="image1_top.par"/>
<outfile xil_pn:name="image1_top.ptwx"/>
<outfile xil_pn:name="image1_top.unroutes"/>
<outfile xil_pn:name="image1_top.xpi"/>
<outfile xil_pn:name="image1_top_pad.csv"/>
<outfile xil_pn:name="image1_top_pad.txt"/>
<outfile xil_pn:name="image1_top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1360079185" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1360079142">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="image1_top.bgn"/>
<outfile xil_pn:name="image1_top.bit"/>
<outfile xil_pn:name="image1_top.drc"/>
<outfile xil_pn:name="image1_top.ut"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1360079239" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1360079238">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1360079142" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1360079125">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="image1_top.twr"/>
<outfile xil_pn:name="image1_top.twx"/>
</transform>
</transforms>
</generated_project>
hdl/IMAGES/image1/project/image1.xise
View file @ a6b105fd
......@@ -15,270 +15,174 @@
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
<files>
<<<<<<< HEAD
<file xil_pn:name="../rtl/image1_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
=======
<file xil_pn:name="../constraints/V2/BloV2.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../rtl/image1_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../rtl/image1_led_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
>>>>>>> 15f461cc70ccb4f36a23fc49acc82d45b5f9de6f
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../rtl/image1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../rtl/image1_wrappers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../top/image1_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd" xil_pn:type="FILE_VHDL">
<<<<<<< HEAD
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
=======
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
>>>>>>> 15f461cc70ccb4f36a23fc49acc82d45b5f9de6f
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<<<<<<< HEAD
<file xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
=======
<file xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
>>>>>>> 15f461cc70ccb4f36a23fc49acc82d45b5f9de6f
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_debounce.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd" xil_pn:type="FILE_VHDL">
<<<<<<< HEAD
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
=======
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
>>>>>>> 15f461cc70ccb4f36a23fc49acc82d45b5f9de6f
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_clk_divider.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<<<<<<< HEAD
<file xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
=======
>>>>>>> 15f461cc70ccb4f36a23fc49acc82d45b5f9de6f
<file xil_pn:name="../../../multiboot/rtl/multiboot_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_top.vhd" xil_pn:type="FILE_VHDL">
<<<<<<< HEAD
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../rtl/image1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
=======
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
>>>>>>> 15f461cc70ccb4f36a23fc49acc82d45b5f9de6f
</file>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<<<<<<< HEAD
<file xil_pn:name="../test/image1_top_tb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../test/image1_top_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/test/i2c_tb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../FPGAbank.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
=======
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../../../../general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../../../general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../test/image1_top_tb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../test/image1_top_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/test/i2c_tb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
>>>>>>> 15f461cc70ccb4f36a23fc49acc82d45b5f9de6f
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../constraints/V2/BloV2.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
......@@ -483,6 +387,7 @@
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -500,10 +405,6 @@
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<<<<<<< HEAD
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
=======
>>>>>>> 15f461cc70ccb4f36a23fc49acc82d45b5f9de6f
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......
hdl/IMAGES/image1/top/image1_top.vhd
View file @ a6b105fd
......@@ -155,33 +155,33 @@ begin
port map (O => s_clk_125MHz, I => FPGA_CLK_P,
IB => FPGA_CLK_N);
LED_CTRL0 <= s_led_array.CTRL0;
LED_CTRL0_OEN <= s_led_array.CTRL0_OEN;
LED_CTRL1 <= s_led_array.CTRL1;
LED_CTRL1_OEN <= s_led_array.CTRL1_OEN;
LED_MULTICAST_2_0 <= s_led_array.MULTICAST_2_0;
LED_MULTICAST_3_1 <= s_led_array.MULTICAST_3_1;
LED_WR_GMT_TTL_TTLN <= s_led_array.WR_GMT_TTL_TTLN;
LED_WR_LINK_SYSERROR <= s_led_array.WR_LINK_SYSERROR;
LED_WR_OK_SYSPW <= s_led_array.WR_OK_SYSPW;
LED_WR_OWNADDR_I2C <= s_led_array.WR_OWNADDR_I2C;
s_i2c_slave_i.SCL_I <= SCL_I;
s_i2c_slave_i.SDA_I <= SDA_I;
SCL_O <= s_i2c_slave_o.SCL_O;
SCL_OE <= s_i2c_slave_o.SCL_OE;
SDA_O <= s_i2c_slave_o.SDA_O;
SDA_OE <= s_i2c_slave_o.SDA_OE;
s_spi_master_i.DIN <= FPGA_PROM_DIN;
FPGA_PROM_CCLK <= s_spi_master_o.CCLK;
FPGA_PROM_CSO_B_N <= s_spi_master_o.CSO_B_N;
FPGA_PROM_MOSI <= s_spi_master_o.MOSI;
s_rtm_i.RTMM_N <= FPGA_RTMM_N;
s_rtm_i.RTMP_N <= fpga_rtmp_n;
s_switch_i <= EXTRA_SWITCH;
LED_CTRL0 <= s_led_array.CTRL0;
LED_CTRL0_OEN <= s_led_array.CTRL0_OEN;
LED_CTRL1 <= s_led_array.CTRL1;
LED_CTRL1_OEN <= s_led_array.CTRL1_OEN;
LED_MULTICAST_2_0 <= s_led_array.MULTICAST_2_0;
LED_MULTICAST_3_1 <= s_led_array.MULTICAST_3_1;
LED_WR_GMT_TTL_TTLN <= s_led_array.WR_GMT_TTL_TTLN;
LED_WR_LINK_SYSERROR <= s_led_array.WR_LINK_SYSERROR;
LED_WR_OK_SYSPW <= s_led_array.WR_OK_SYSPW;
LED_WR_OWNADDR_I2C <= s_led_array.WR_OWNADDR_I2C;
s_i2c_slave_i.SCL_I <= SCL_I;
s_i2c_slave_i.SDA_I <= SDA_I;
SCL_O <= s_i2c_slave_o.SCL_O;
SCL_OE <= s_i2c_slave_o.SCL_OE;
SDA_O <= s_i2c_slave_o.SDA_O;
SDA_OE <= s_i2c_slave_o.SDA_OE;
s_spi_master_i.DIN <= FPGA_PROM_DIN;
FPGA_PROM_CCLK <= s_spi_master_o.CCLK;
FPGA_PROM_CSO_B_N <= s_spi_master_o.CSO_B_N;
FPGA_PROM_MOSI <= s_spi_master_o.MOSI;
s_rtm_i.RTMM_N <= FPGA_RTMM_N;
s_rtm_i.RTMP_N <= fpga_rtmp_n;
s_switch_i <= EXTRA_SWITCH;
inst_image1_core: image1_core
generic map(g_NUMBER_OF_CHANNELS => 6)
......
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