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Conv TTL Blocking
Commit b9e138fd authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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@misc{StdBlocking,
author = "C. Gil Soriano",
title = {{Standard Blocking Output Signal Definition for CTDAH board}},
month = sep,
year = 2011,
note = "{\url{http://www.ohwr.org/documents/109}}"
}
@misc{FunSpecs,
author = "C. Gil Soriano",
title = {{Standard Blocking Repeater in VME64x Format, Functional Specifications}},
month = aug,
year = 2012,
note = "{\url{http://www.ohwr.org/documents/104}}"
}
@misc{TechFlyback,
author = "C. Gil Soriano",
title = {{Flyback circuit outputting Standard Blocking for CTDAH}},
month = sep,
year = 2011,
note = "{\url{http://www.ohwr.org/documents/110}}"
}
@misc{BlockingMono,
author = "C. Gil Soriano",
title = {{A Triggered Monostable Blocking Oscillator Used in legacy Channel
Repeaters}},
month = aug,
year = 2012,
note = "{\url{http://www.ohwr.org/documents/94}}"
}
@misc{issuesReportV1,
author = "C. Gil Soriano",
title = {{Report of issues in CONV-TTL-BLO v1.0 EDA-02446-V1-0}},
month = oct,
year = 2012,
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/show/pcb/doc/issues/conv-ttl-blo?rev=basic_trigger_addingGenerics}}"
}
@TECHREPORT{I2Cdoc,
author = "C. Gil Soriano",
institution = "CERN, BE-CO-HT",
title = "{I2C Slave to Wishbone Master module}",
month = nov,
year = 2012,
number = "v0.9",
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/changes/hdl/i2c_slave_wb_master/doc/i2cSpecs.pdf}}"
}
@TECHREPORT{SPIdoc,
author = "C. Gil Soriano",
institution = "CERN, BE-CO-HT",
title = "{SPI master multifield HDL core}",
month = oct,
year = 2012,
number = "v0.9",
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/changes/hdl/spi_master_multifield/doc/spiSpecs.pdf}}"
}
@TECHREPORT{M25P32doc,
author = "C. Gil Soriano",
institution = "CERN, BE-CO-HT",
title = "{m25p32 manager HDL core}",
month = oct,
year = 2012,
number = "v0.9",
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/changes/hdl/m25p32/doc/m25p32.pdf}}"
}
@TECHREPORT{multibootDoc,
author = "C. Gil Soriano",
institution = "CERN, BE-CO-HT",
title = "{Multiboot HDL module}",
month = jan,
year = 2013,
number = "v0.9",
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/changes/hdl/multiboot/doc/multiboot.pdf}}"
}
@TECHREPORT{ELMAspecI2C,
author = "S. Iglesias Gonsalvez",
institution = "CERN, BE-CO-HT",
title = "{ELMA Crates Specification, Access to board data using
SNMP and I2C}",
month = feb,
year = 2011,
note = "{\url{http://www.ohwr.org/documents/227}}"
}
@TECHREPORT{ELMAsysMonDoc,
institution = "ELMA",
title = "{NEW Sysmon Manual}",
number = "v1.11",
note = "{\url{http://www.ohwr.org/documents/226}}"
}
@TECHREPORT{UG380,
institution = "Xilinx Inc.",
title = {{Spartan-6 FPGA Configuration User Guide}},
month = jul,
year = 2011,
number = "UG380 v2.3",
note = "{\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}"
}
@TECHREPORT{UG381,
institution = "Xilinx Inc.",
title = "{Spartan-6 FPGA SelectIO Resources}",
month = dec,
year = 2010,
number = "v1.4",
note =
"{\url{http://www.xilinx.com/support/documentation/user_guides/ug381.pdf}}"
}
@TECHREPORT{,
institution = "Xilinx Inc.",
title = "{}",
month = jan,
year = 2012,
number = "v0.9",
note =
"{\url{}}"
}
@TECHREPORT{,
institution = "Xilinx Inc.",
title = "{}",
month = jan,
year = 2012,
number = "v0.9",
note =
"{\url{}}"
}
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--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: image1_led_pkg.vhd
--
-- author: Carlos Gil Soriano (gilsoriano@gmail.com)
--
-- date: 23-01-2013
--
-- version: 1.0
--
-- description: Package for easy accessing LED array in CONV-TTL-BLO V2
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.bicolor_led_ctrl_pkg.ALL;
package image1_led_pkg is
--! LEDs IP core constants
constant c_NB_COLUMN : NATURAL := 6;
constant c_NB_LINE : NATURAL := 2;
--! LEDs
constant c_NB_ARRAY_LEDS : NATURAL := 12;
constant c_LED_INTENSITY : STD_LOGIC_VECTOR(6 downto 0) := "0011111";
--! Front array LEDs individual assignment
--! Pairings:
--! COLUMN t_led_state
--! 0 0 - 6
--! 1 1 - 7
--! 2 2 - 8
--! 3 3 - 9
--! 4 4 - 10
--! 5 5 - 11
constant c_LED_NB_WR_ADDR : NATURAL := 0;
constant c_LED_NB_WR_GMT : NATURAL := 1;
constant c_LED_NB_WR_LINK : NATURAL := 2;
constant c_LED_NB_WR_OK : NATURAL := 3;
constant c_LED_NB_MULTICAST0 : NATURAL := 4;
constant c_LED_NB_MULTICAST1 : NATURAL := 5;
constant c_LED_NB_I2C : NATURAL := 6;
constant c_LED_NB_TTL_N : NATURAL := 7;
constant c_LED_NB_ERR : NATURAL := 8;
constant c_LED_NB_PWR : NATURAL := 9;
constant c_LED_NB_MULTICAST2 : NATURAL := 10;
constant c_LED_NB_MULTICAST3 : NATURAL := 11;
constant c_LED_COLOR_PWR : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_ERR : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_RED);
constant c_LED_COLOR_TTL_N : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_I2C : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_WR_OK : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_WR_LINK : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_WR_GMT : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_WR_ADDR : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_MULTICAST3 : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_MULTICAST2 : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_MULTICAST1 : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_MULTICAST0 : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
type t_leds_array_top is
record
PWR : STD_LOGIC;
ERR : STD_LOGIC;
TTL_N : STD_LOGIC;
I2C : STD_LOGIC;
end record;
type t_leds_array_middle is
record
WR_OK : STD_LOGIC;
WR_LINK : STD_LOGIC;
WR_GMT : STD_LOGIC;
WR_ADDR : STD_LOGIC;
end record;
type t_leds_array_bottom is
record
MULTICAST : UNSIGNED(3 downto 0);
end record;
type t_leds_array is
record
top : t_leds_array_top;
middle : t_leds_array_middle;
bottom : t_leds_array_bottom;
end record;
type t_led_state is
record
STATE : STD_LOGIC_VECTOR(1 downto 0);
end record;
type t_led_state_array is array(natural range <>) of t_led_state;
function f_LED_STATE(state: STD_LOGIC_VECTOR(1 downto 0)) return t_led_state;
function f_STD_LOGIC_VECTOR(led_state : t_led_state) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(led_state_array : t_led_state_array)
return STD_LOGIC_VECTOR;
end image1_led_pkg;
package body image1_led_pkg is
--! @brief Translation function from STD_LOGIC_VECTOR to t_led_state
--! @param state LED state in STD_LOGIC_VECTOR format
function f_LED_STATE(state: STD_LOGIC_VECTOR(1 downto 0)) return t_led_state is
variable v_return : t_led_state;
begin
v_return.STATE(0) := state(0);
v_return.STATE(1) := state(1);
return v_return;
end f_LED_STATE;
--! @brief Translation function from STD_LOGIC_VECTOR to
--! t_led_state
--! @param led_state_array LED state in STD_LOGIC_VECTOR format
function f_STD_LOGIC_VECTOR(led_state : t_led_state)
return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(1 downto 0);
begin
v_return(0) := led_state.STATE(0);
v_return(1) := led_state.STATE(1);
return v_return;
end f_STD_LOGIC_VECTOR;
--! @brief Translation function from STD_LOGIC_VECTOR to
--! t_led_state_array
--! @param led_state_array LED array state in STD_LOGIC_VECTOR format
function f_STD_LOGIC_VECTOR(led_state_array : t_led_state_array)
return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(2*c_NB_COLUMN*c_NB_LINE - 1 downto 0);
variable v_led_state_tmp : t_led_state;
variable v_led_state_slv_tmp : STD_LOGIC_VECTOR(1 downto 0);
begin
for i in 0 to (c_NB_COLUMN*c_NB_LINE - 1) loop
v_led_state_tmp := led_state_array(i);
v_led_state_slv_tmp := f_STD_LOGIC_VECTOR(v_led_state_tmp);
v_return(2*i + 1 downto 2*i) := v_led_state_slv_tmp;
end loop;
return v_return;
end f_STD_LOGIC_VECTOR;
end image1_led_pkg;
hdl/IMAGES/image1/rtl/image1_pkg.vhd
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--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: image1_top.vhd
--
-- author: Carlos Gil Soriano (gilsoriano@gmail.com)
--
-- date: 23-01-2013
--
-- version: 1.0
--
-- description: Package for top entity of CONV-TTL-BLO V1
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library IEEE;
library work;
......@@ -16,6 +49,8 @@ package image1_pkg is
--! Blocking repetition parameters
constant c_NUMBER_OF_CHANNELS : NATURAL := 6;
--! Pulse repetition constants
constant c_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
constant c_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns;
......@@ -52,9 +87,9 @@ package image1_pkg is
--! will be processed as an access to such register (indeed, like
--! accessing to byte 0).
--! ==================================
--! M25P32 [0200-03FF]
--! MULTIBOOT [0080-00CF]
--! I2C_SLAVE [0040-007F]
--! M25P32 [0200-03FF]
--! MULTIBOOT [0080-00CF]
--! I2C_SLAVE [0040-007F]
--! ==================================
constant c_ADDR_M25P32 : t_wishbone_address := X"00000200";
constant c_ADDR_MULTIBOOT : t_wishbone_address := X"00000080";
......@@ -215,7 +250,7 @@ package image1_pkg is
end component;
-- function check_sys_cfg return BOOLEAN;
-- function check_sys_cfg return BOOLEAN;
function f_RENESAS_I2C_ADDRESSING(VME_slot : UNSIGNED(4 downto 0))
return STD_LOGIC_VECTOR;
end image1_pkg;
......@@ -236,6 +271,7 @@ package body image1_pkg is
-- return TRUE;
-- end check_sys_cfg;
--! @brief Translation function for i2c_addressing
--! The specification of this criteria can be found in
--! Samuel's document "Specification. Access to board data
......
hdl/IMAGES/image1/rtl/image1_wrappers_pkg.vhd 0 → 100644
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--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: image1_wrappers_pkg.vhd
--
-- author: Carlos Gil Soriano (gilsoriano@gmail.com)
--
-- date: 23-01-2013
--
-- version: 1.0
--
-- description: Package for the wrappers used in image1_core.vhd of
-- CONV-TTL-BLO V2
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
package image1_wrappers_pkg is
--! Wrappers for image1_top FPGA pinouts
type t_led_array_o is
record
CTRL0 : STD_LOGIC;
CTRL0_OEN : STD_LOGIC;
CTRL1 : STD_LOGIC;
CTRL1_OEN : STD_LOGIC;
MULTICAST_2_0 : STD_LOGIC;
MULTICAST_3_1 : STD_LOGIC;
WR_GMT_TTL_TTLN : STD_LOGIC;
WR_LINK_SYSERROR : STD_LOGIC;
WR_OK_SYSPW : STD_LOGIC;
WR_OWNADDR_I2C : STD_LOGIC;
end record;
type t_i2c_slave_i is
record
SCL_I : STD_LOGIC;
SDA_I : STD_LOGIC;
end record;
type t_i2c_slave_o is
record
SCL_O : STD_LOGIC;
SCL_OE : STD_LOGIC;
SDA_O : STD_LOGIC;
SDA_OE : STD_LOGIC;
end record;
type t_spi_master_i is
record
DIN : STD_LOGIC;
end record;
type t_spi_master_o is
record
CCLK : STD_LOGIC;
CSO_B_N : STD_LOGIC;
MOSI : STD_LOGIC;
end record;
type t_rtm_i is
record
RTMM_N : STD_LOGIC_VECTOR(2 downto 0);
RTMP_N : STD_LOGIC_VECTOR(2 downto 0);
end record;
constant c_led_array_default : t_led_array_o := (CTRL0 => '0',
CTRL0_OEN => '0',
CTRL1 => '0',
CTRL1_OEN => '0',
MULTICAST_2_0 => '0',
MULTICAST_3_1 => '0',
WR_GMT_TTL_TTLN => '0',
WR_LINK_SYSERROR => '0',
WR_OK_SYSPW => '0',
WR_OWNADDR_I2C => '0');
end image1_wrappers_pkg;
package body image1_wrappers_pkg is
end image1_wrappers_pkg;
hdl/IMAGES/image1/test/image1_top_tb.vhd
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hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
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......@@ -21,50 +21,57 @@ package image1_top_tb_pkg is
component image1_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (FPGA_CLK_P : in STD_LOGIC;
FPGA_CLK_N : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1);
port (RST_N : in STD_LOGIC;
CLK20_VCXO : in STD_LOGIC;
FPGA_CLK_P : in STD_LOGIC; --Using the 125MHz clock
FPGA_CLK_N : in STD_LOGIC;
--! LEDs
LED_CTRL0 : out STD_LOGIC;
LED_CTRL0_OEN : out STD_LOGIC;
LED_CTRL1 : out STD_LOGIC;
LED_CTRL1_OEN : out STD_LOGIC;
LED_MULTICAST_2_0 : out STD_LOGIC;
LED_MULTICAST_3_1 : out STD_LOGIC;
LED_WR_GMT_TTL_TTLN : out STD_LOGIC;
LED_WR_LINK_SYSERROR : out STD_LOGIC;
LED_WR_OK_SYSPW : out STD_LOGIC;
LED_WR_OWNADDR_I2C : out STD_LOGIC;
--! I/Os for pulses
PULSE_FRONT_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
PULSE_REAR_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_INPUT_TTL_N : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_OUT_TTL : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_BLO_IN : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_TRIG_BLO : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
INV_IN_N : in STD_LOGIC_VECTOR(4 downto 1);
INV_OUT : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_OE : out STD_LOGIC;
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_OE : out STD_LOGIC;
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_OE : out STD_LOGIC;
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_OE : out STD_LOGIC;
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
--! Pins of the SPI interface to write into the Flash memory
FPGA_PROM_CCLK : out STD_LOGIC;
FPGA_PROM_CSO_B_N : out STD_LOGIC;
FPGA_PROM_DIN : in STD_LOGIC;
FPGA_PROM_MOSI : out STD_LOGIC;
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP : in STD_LOGIC_VECTOR(2 downto 0));
FPGA_PROM_CCLK : out STD_LOGIC;
FPGA_PROM_CSO_B_N : out STD_LOGIC;
FPGA_PROM_DIN : in STD_LOGIC;
FPGA_PROM_MOSI : out STD_LOGIC;
--! RTM identifiers, should match with the expected values
--! TODO: add matching
FPGA_OE : out STD_LOGIC;
FPGA_BLO_OE : out STD_LOGIC;
FPGA_TRIG_TTL_OE : out STD_LOGIC;
FPGA_INV_OE : out STD_LOGIC;
LEVEL : in STD_LOGIC;
EXTRA_SWITCH : in STD_LOGIC_VECTOR(1 downto 1);--! General enable
MR_N : out STD_LOGIC;--! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM_N : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP_N : in STD_LOGIC_VECTOR(2 downto 0));
end component;
type t_pulse_vector is
......
hdl/IMAGES/image1/top/image1_top.vhd 0 → 100644
View file @ b9e138fd
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: image1_top.vhd
--
-- author: Carlos Gil Soriano (gilsoriano@gmail.com)
--
-- date: 01-12-2012
--
-- version: 0.9
--
-- description: Top entity of CONV-TTL-BLO V1
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library IEEE;
library unisim;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.image1_pkg.ALL;
use work.image1_wrappers_pkg.ALL;
use work.wishbone_pkg.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity image1_top is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (RST_N : in STD_LOGIC;
CLK20_VCXO : in STD_LOGIC;
FPGA_CLK_P : in STD_LOGIC; --Using the 125MHz clock
FPGA_CLK_N : in STD_LOGIC;
--! LEDs
LED_CTRL0 : out STD_LOGIC;
LED_CTRL0_OEN : out STD_LOGIC;
LED_CTRL1 : out STD_LOGIC;
LED_CTRL1_OEN : out STD_LOGIC;
LED_MULTICAST_2_0 : out STD_LOGIC;
LED_MULTICAST_3_1 : out STD_LOGIC;
LED_WR_GMT_TTL_TTLN : out STD_LOGIC;
LED_WR_LINK_SYSERROR : out STD_LOGIC;
LED_WR_OK_SYSPW : out STD_LOGIC;
LED_WR_OWNADDR_I2C : out STD_LOGIC;
--! I/Os for pulses
PULSE_FRONT_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
PULSE_REAR_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_INPUT_TTL_N : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_OUT_TTL : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_BLO_IN : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_TRIG_BLO : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
INV_IN_N : in STD_LOGIC_VECTOR(4 downto 1);
INV_OUT : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_OE : out STD_LOGIC;
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_OE : out STD_LOGIC;
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
--! Pins of the SPI interface to write into the Flash memory
FPGA_PROM_CCLK : out STD_LOGIC;
FPGA_PROM_CSO_B_N : out STD_LOGIC;
FPGA_PROM_DIN : in STD_LOGIC;
FPGA_PROM_MOSI : out STD_LOGIC;
--! RTM identifiers, should match with the expected values
--! TODO: add matching
FPGA_OE : out STD_LOGIC;
FPGA_BLO_OE : out STD_LOGIC;
FPGA_TRIG_TTL_OE : out STD_LOGIC;
FPGA_INV_OE : out STD_LOGIC;
LEVEL : in STD_LOGIC;--!TTL/INV_TTL_N
EXTRA_SWITCH : in STD_LOGIC_VECTOR(1 downto 1);--! General enable
MR_N : out STD_LOGIC;--! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM_N : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP_N : in STD_LOGIC_VECTOR(2 downto 0));
end image1_top;
architecture Behavioral of image1_top is
component image1_core is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (rst_n : in STD_LOGIC;
clk_20MHz_i : in STD_LOGIC;
clk_125MHz_i : in STD_LOGIC;
--! LEDs
led_array_o : out t_led_array_o;
--! I/Os for pulses
led_front_n : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_rear_n : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_front_n : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i_n : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
i2c_slave_i : in t_i2c_slave_i;
i2c_slave_o : out t_i2c_slave_o;
--! FPGA Geographical address pins (reused for i2c address)
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
--! Pins of the SPI interface to write into the Flash memory
spi_master_i : in t_spi_master_i;
spi_master_o : out t_spi_master_o;
--! RTM identifiers, should match with the expected values
--! TODO: add matching
fpga_o_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
rtm_i : in t_rtm_i);
end component;
signal s_clk_125MHz : STD_LOGIC;
signal s_led_array : t_led_array_o := c_led_array_default;
signal s_i2c_slave_i : t_i2c_slave_i;
signal s_i2c_slave_o : t_i2c_slave_o;
signal s_spi_master_i : t_spi_master_i;
signal s_spi_master_o : t_spi_master_o;
signal s_rtm_i : t_rtm_i;
signal s_switch_i : STD_LOGIC_VECTOR(1 downto 1);
begin
inst_125m_IBUFGDS : IBUFGDS
generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => TRUE)
port map (O => s_clk_125MHz, I => FPGA_CLK_P,
IB => FPGA_CLK_N);
LED_CTRL0 <= s_led_array.CTRL0;
LED_CTRL0_OEN <= s_led_array.CTRL0_OEN;
LED_CTRL1 <= s_led_array.CTRL1;
LED_CTRL1_OEN <= s_led_array.CTRL1_OEN;
LED_MULTICAST_2_0 <= s_led_array.MULTICAST_2_0;
LED_MULTICAST_3_1 <= s_led_array.MULTICAST_3_1;
LED_WR_GMT_TTL_TTLN <= s_led_array.WR_GMT_TTL_TTLN;
LED_WR_LINK_SYSERROR <= s_led_array.WR_LINK_SYSERROR;
LED_WR_OK_SYSPW <= s_led_array.WR_OK_SYSPW;
LED_WR_OWNADDR_I2C <= s_led_array.WR_OWNADDR_I2C;
s_i2c_slave_i.SCL_I <= SCL_I;
s_i2c_slave_i.SDA_I <= SDA_I;
SCL_O <= s_i2c_slave_o.SCL_O;
SCL_OE <= s_i2c_slave_o.SCL_OE;
SDA_O <= s_i2c_slave_o.SDA_O;
SDA_OE <= s_i2c_slave_o.SDA_OE;
s_spi_master_i.DIN <= FPGA_PROM_DIN;
FPGA_PROM_CCLK <= s_spi_master_o.CCLK;
FPGA_PROM_CSO_B_N <= s_spi_master_o.CSO_B_N;
FPGA_PROM_MOSI <= s_spi_master_o.MOSI;
s_rtm_i.RTMM_N <= FPGA_RTMM_N;
s_rtm_i.RTMP_N <= fpga_rtmp_n;
s_switch_i <= EXTRA_SWITCH;
inst_image1_core: image1_core
generic map(g_NUMBER_OF_CHANNELS => 6)
port map(rst_n => RST_N,
clk_20MHz_i => CLK20_VCXO,
clk_125MHz_i => s_clk_125MHz,
led_array_o => s_led_array,
led_front_n => PULSE_FRONT_LED_N,
led_rear_n => PULSE_REAR_LED_N,
pulse_i_front_n => FPGA_INPUT_TTL_N,
pulse_o_front => FPGA_OUT_TTL,
pulse_i_rear => FPGA_BLO_IN,
pulse_o_rear => FPGA_TRIG_BLO,
inv_i_n => INV_IN_N,
inv_o => INV_OUT,
i2c_slave_i => s_i2c_slave_i,
i2c_slave_o => s_i2c_slave_o,
FPGA_GA => FPGA_GA ,
FPGA_GAP => FPGA_GAP,
spi_master_i => s_spi_master_i,
spi_master_o => s_spi_master_o,
fpga_o_en => FPGA_OE,
fpga_o_blo_en => FPGA_BLO_OE,
fpga_o_ttl_en => FPGA_TRIG_TTL_OE,
fpga_o_inv_en => FPGA_INV_OE,
level => LEVEL,
switch_i => s_switch_i(1),
manual_rst_n_o => MR_N,
rtm_i => s_rtm_i);
end Behavioral;
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