Added modified pulse generators from pts branch

a75842b3 · Theodor-Adrian Stana · 37233295 · a75842b3 · a75842b3 · a75842b3
Commit a75842b3 authored May 30, 2013 by Theodor-Adrian Stana
6 changed files
--- a/hdl/ctb_pulse_gen/Manifest.py
+++ b/hdl/ctb_pulse_gen/Manifest.py
+modules = {
+      "local" : "rtl"
+    }
--- a/hdl/ctb_pulse_gen/rtl/Manifest.py
+++ b/hdl/ctb_pulse_gen/rtl/Manifest.py
+files = "ctb_pulse_gen.vhd"
+
+modules = { 
+  "local" : [
+    "../../glitch_filt",
+    "../../../../ip_cores/general-cores"
+  ]
+}
--- a/hdl/ctb_pulse_gen/rtl/ctb_pulse_gen.vhd
+++ b/hdl/ctb_pulse_gen/rtl/ctb_pulse_gen.vhd
--- a/hdl/ctb_pulse_gen_gp/Manifest.py
+++ b/hdl/ctb_pulse_gen_gp/Manifest.py
+modules = {"local" : "rtl"}
--- a/hdl/ctb_pulse_gen_gp/rtl/Manifest.py
+++ b/hdl/ctb_pulse_gen_gp/rtl/Manifest.py
+files = [
+      "ctb_pulse_gen_gp.vhd"
+    ]
--- a/hdl/ctb_pulse_gen_gp/rtl/ctb_pulse_gen_gp.vhd
+++ b/hdl/ctb_pulse_gen_gp/rtl/ctb_pulse_gen_gp.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- Test module for old repeater boards
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- date of creation: 2013-02-28
+--
+-- version: 1.0
+--
+-- description: 
+--
+-- dependencies:
+--
+-- references:
+-- 
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    2013-02-28   Theodor Stana     t.stana@cern.ch     File created
+--==============================================================================
+-- TODO: - 
+--==============================================================================
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity ctb_pulse_gen_gp is
+  generic
+  (
+    g_pwidth : natural := 200;
+    g_freq   : natural := 400;
+    g_delay  : natural := 0
+  );
+  port
+  (
+    clk_i   : in  std_logic;
+    rst_n_i : in  std_logic;
+    en_i    : in  std_logic;
+    pulse_o : out std_logic
+  );
+end entity ctb_pulse_gen_gp;
+
+
+architecture behav of ctb_pulse_gen_gp is
+
+  --============================================================================
+  -- Function and procedure declarations
+  --============================================================================
+  function f_log2_size (A : natural) return natural is
+  begin
+    for I in 1 to 64 loop               -- Works for up to 64 bits
+      if (2**I >= A) then
+        return(I);
+      end if;
+    end loop;
+    return(63);
+  end function f_log2_size;
+
+  --============================================================================
+  -- Signal declarations
+  --============================================================================
+  signal freq_cnt  : unsigned(f_log2_size(g_freq)-1 downto 0);
+  signal delay_cnt : unsigned(f_log2_size(g_delay)-1 downto 0);
+  signal delay_en  : std_logic;
+
+--==============================================================================
+--  architecture begin
+--==============================================================================
+begin
+
+  --============================================================================
+  -- Delay logic
+  --============================================================================
+  gen_nodelay: if (g_delay = 0) generate
+    delay_en <= '0';
+  end generate gen_nodelay;
+
+  gen_delay: if (g_delay > 0) generate
+    p_delay: process (clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if (rst_n_i = '0') then
+          delay_en  <= '1';
+          delay_cnt <= (others => '0');
+        elsif (en_i = '1') and (delay_en = '1') then
+          delay_cnt <= delay_cnt + 1;
+          if (delay_cnt = g_delay-1) then
+            delay_en  <= '0';
+            delay_cnt <= (others => '0'); 
+          end if;
+        end if;
+      end if;
+    end process p_delay;
+  end generate gen_delay;
+
+  --============================================================================
+  -- Pulse generation logic
+  --============================================================================
+  p_gen_pulse: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0') then
+        freq_cnt  <= (others => '0');
+        pulse_o   <= '0';
+      elsif (en_i = '1') and (delay_en = '0') then
+        freq_cnt <= freq_cnt + 1;
+        pulse_o  <= '0';
+        if (freq_cnt < g_pwidth) then
+          pulse_o  <= '1';
+        elsif (freq_cnt = g_freq-1) then
+          freq_cnt <= (others => '0');
+        end if;
+      end if;
+    end if;
+  end process p_gen_pulse;
+
+end architecture behav;
+--==============================================================================
+--  architecture end
+--==============================================================================