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Conv TTL Blocking
Commit a8566fda authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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Kickstart for the image integrating everything

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hdl/IMAGES/image1/constraints/FPGAbank.ucf
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##---------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##----------------------------------------
#
#
NET "CLK20_VCXO" LOC = E16;
NET "CLK20_VCXO" IOSTANDARD = "LVCMOS33";
NET "CLK20_VCXO" TNM_NET = "CLK20_VCXO";
TIMESPEC TS_CLK20_VCXO = PERIOD "CLK20_VCXO" 20 MHz HIGH 50%;
#
#NET "FPGA_CLK_N" LOC = G11;
# NET "FPGA_CLK_N" IOSTANDARD = "LVDS_25";
#NET "FPGA_CLK_P" LOC = H12;
# NET "FPGA_CLK_P" IOSTANDARD = "LVDS_25";
#
#NET "FPGA_SYSRESET_N" LOC = L20;
#NET "MR_N" LOC = T22;
#
##======================================
##-- FRONT PANEL TTLS
##======================================
##-- LEDs
##--
##-- + ACT: CMOS 3.3V input
##-------------------
NET "LED_SYS_PW" LOC = F10;
NET "LED_SYS_PW" IOSTANDARD = "LVCMOS33";
NET "LED_SYS_PW" DRIVE = "4";
NET "LED_SYS_PW" SLEW = "QUIETIO";
NET "LED_SYS_ERROR" LOC = F9;
NET "LED_SYS_ERROR" IOSTANDARD = "LVCMOS33";
NET "LED_SYS_ERROR" DRIVE = "4";
NET "LED_SYS_ERROR" SLEW = "QUIETIO";
NET "LED_TTL" LOC = F8;
NET "LED_TTL" IOSTANDARD = "LVCMOS33";
NET "LED_TTL" DRIVE = "4";
NET "LED_TTL" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED[1]" LOC = H3;
NET "PULSE_FRONT_LED[1]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED[1]" DRIVE = "4";
NET "PULSE_FRONT_LED[1]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED[2]" LOC = J4;
NET "PULSE_FRONT_LED[2]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED[2]" DRIVE = "4";
NET "PULSE_FRONT_LED[2]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED[3]" LOC = J3;
NET "PULSE_FRONT_LED[3]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED[3]" DRIVE = "4";
NET "PULSE_FRONT_LED[3]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED[4]" LOC = K3;
NET "PULSE_FRONT_LED[4]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED[4]" DRIVE = "4";
NET "PULSE_FRONT_LED[4]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED[5]" LOC = L4;
NET "PULSE_FRONT_LED[5]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED[5]" DRIVE = "4";
NET "PULSE_FRONT_LED[5]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED[6]" LOC = L3;
NET "PULSE_FRONT_LED[6]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED[6]" DRIVE = "4";
NET "PULSE_FRONT_LED[6]" SLEW = "QUIETIO";
##-------------------
##-- TTL trigger inputs
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "FPGA_INPUT_TTL[1]" LOC = T3;
NET "FPGA_INPUT_TTL[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL[2]" LOC = U4;
NET "FPGA_INPUT_TTL[2]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL[3]" LOC = W3;
NET "FPGA_INPUT_TTL[3]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL[4]" LOC = W4;
NET "FPGA_INPUT_TTL[4]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL[5]" LOC = V3;
NET "FPGA_INPUT_TTL[5]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL[6]" LOC = U3;
NET "FPGA_INPUT_TTL[6]" IOSTANDARD = "LVCMOS33";
##-------------------
##-- TTL Blocking pulses outputs
##--
##-- + BCT family (BiCMOS) TTL inputs
##-------------------
NET "FPGA_OUT_TTL[1]" LOC = D1;
NET "FPGA_OUT_TTL[1]" IOSTANDARD = "LVTTL";
NET "FPGA_OUT_TTL[1]" SLEW = "FAST";
NET "FPGA_OUT_TTL[2]" LOC = E1;
NET "FPGA_OUT_TTL[2]" IOSTANDARD = "LVTTL";
NET "FPGA_OUT_TTL[2]" SLEW = "FAST";
NET "FPGA_OUT_TTL[3]" LOC = F2;
NET "FPGA_OUT_TTL[3]" IOSTANDARD = "LVTTL";
NET "FPGA_OUT_TTL[3]" SLEW = "FAST";
NET "FPGA_OUT_TTL[4]" LOC = F1;
NET "FPGA_OUT_TTL[4]" IOSTANDARD = "LVTTL";
NET "FPGA_OUT_TTL[4]" SLEW = "FAST";
NET "FPGA_OUT_TTL[5]" LOC = G1;
NET "FPGA_OUT_TTL[5]" IOSTANDARD = "LVTTL";
NET "FPGA_OUT_TTL[5]" SLEW = "FAST";
NET "FPGA_OUT_TTL[6]" LOC = H2;
NET "FPGA_OUT_TTL[6]" IOSTANDARD = "LVTTL";
NET "FPGA_OUT_TTL[6]" SLEW = "FAST";
##-------------------
##-- Bottom located GPIOs
##--
##-- + IN ACT family: CMOS/TTL 3.3V inputs
##-- + OUT BCT family (BiCMOS): TTL inputs
##
##-- Schematics name: INV_IN_*
##---- renamed to INV_IN[*]
##-------------------
## NET "INV_IN[1]" LOC = Y1;
## NET "INV_IN[1]" IOSTANDARD = "LVCMOS33";
## NET "INV_IN[2]" LOC = Y2;
## NET "INV_IN[2]" IOSTANDARD = "LVCMOS33";
## NET "INV_IN[3]" LOC = AA1;
## NET "INV_IN[3]" IOSTANDARD = "LVCMOS33";
## NET "INV_IN[4]" LOC = AA2;
## NET "INV_IN[4]" IOSTANDARD = "LVCMOS33";
NET "INV_OUT[1]" LOC = J1;
NET "INV_OUT[1]" IOSTANDARD = "LVTTL";
NET "INV_OUT[2]" LOC = K2;
NET "INV_OUT[2]" IOSTANDARD = "LVTTL";
NET "INV_OUT[3]" LOC = K1;
NET "INV_OUT[3]" IOSTANDARD = "LVTTL";
NET "INV_OUT[4]" LOC = L1;
NET "INV_OUT[4]" IOSTANDARD = "LVTTL";
##
##
##======================================
##-- RTM signals
##======================================
##-- Blocking input to FPGA
##
##-- Schematics name: FPGA_BLO_IN_*
##---- renamed to FPGA_BLO_IN[*]
##-------------------
NET "FPGA_BLO_IN[1]" LOC = W18;
NET "FPGA_BLO_IN[1]" IOSTANDARD = "LVTTL";
NET "FPGA_BLO_IN[2]" LOC = Y18;
NET "FPGA_BLO_IN[2]" IOSTANDARD = "LVTTL";
NET "FPGA_BLO_IN[3]" LOC = W17;
NET "FPGA_BLO_IN[3]" IOSTANDARD = "LVTTL";
NET "FPGA_BLO_IN[4]" LOC = Y17;
NET "FPGA_BLO_IN[4]" IOSTANDARD = "LVTTL";
NET "FPGA_BLO_IN[5]" LOC = Y16;
NET "FPGA_BLO_IN[5]" IOSTANDARD = "LVTTL";
NET "FPGA_BLO_IN[6]" LOC = Y15;
NET "FPGA_BLO_IN[6]" IOSTANDARD = "LVTTL";
##-------------------
##-- Blocking driver triggers from FPGA
##--
##-- + OUT BCT family (BiCMOS): TTL inputs
##-------------------
NET "FPGA_TRIG_BLO[1]" LOC = V1;
NET "FPGA_TRIG_BLO[1]" IOSTANDARD = "LVTTL";
NET "FPGA_TRIG_BLO[1]" SLEW = "FAST";
NET "FPGA_TRIG_BLO[2]" LOC = U1;
NET "FPGA_TRIG_BLO[2]" IOSTANDARD = "LVTTL";
NET "FPGA_TRIG_BLO[2]" SLEW = "FAST";
NET "FPGA_TRIG_BLO[3]" LOC = T2;
NET "FPGA_TRIG_BLO[3]" IOSTANDARD = "LVTTL";
NET "FPGA_TRIG_BLO[3]" SLEW = "FAST";
NET "FPGA_TRIG_BLO[4]" LOC = T1;
NET "FPGA_TRIG_BLO[4]" IOSTANDARD = "LVTTL";
NET "FPGA_TRIG_BLO[4]" SLEW = "FAST";
NET "FPGA_TRIG_BLO[5]" LOC = R1;
NET "FPGA_TRIG_BLO[5]" IOSTANDARD = "LVTTL";
NET "FPGA_TRIG_BLO[5]" SLEW = "FAST";
NET "FPGA_TRIG_BLO[6]" LOC = P2;
NET "FPGA_TRIG_BLO[6]" IOSTANDARD = "LVTTL";
NET "FPGA_TRIG_BLO[6]" SLEW = "FAST";
##-------------------
##-- Rear LEDs
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "PULSE_REAR_LED[1]" LOC = AB17;
NET "PULSE_REAR_LED[1]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED[1]" DRIVE = "4";
NET "PULSE_REAR_LED[1]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED[2]" LOC = AB19;
NET "PULSE_REAR_LED[2]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED[2]" DRIVE = "4";
NET "PULSE_REAR_LED[2]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED[3]" LOC = AA16;
NET "PULSE_REAR_LED[3]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED[3]" DRIVE = "4";
NET "PULSE_REAR_LED[3]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED[4]" LOC = AA18;
NET "PULSE_REAR_LED[4]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED[4]" DRIVE = "4";
NET "PULSE_REAR_LED[4]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED[5]" LOC = AB16;
NET "PULSE_REAR_LED[5]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED[5]" DRIVE = "4";
NET "PULSE_REAR_LED[5]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED[6]" LOC = AB18;
NET "PULSE_REAR_LED[6]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED[6]" DRIVE = "4";
NET "PULSE_REAR_LED[6]" SLEW = "QUIETIO";
---------------------------------------
-- Default attributes
--
-- IOSTANDARD = "LVCMOS25"
-- SLEW = "SLOW"
-- DRIVE = "12"
----------------------------------------
##======================================
##-- VME CONNECTOR SIGNALS
##======================================
##-- I2C lines
##--
##-- + UBT: LVTTL input
##-------------------
NET "clk_i" LOC = E16;
NET "clk_i" IOSTANDARD = "LVCMOS33";
NET "clk_i" TNM_NET = "clk_i";
TIMESPEC TS_clk_i = PERIOD "clk_i" 20 MHz HIGH 50%;
NET "FPGA_CLK_N" LOC = G11;
NET "FPGA_CLK_N" IOSTANDARD = "LVDS_25";
NET "FPGA_CLK_P" LOC = H12;
NET "FPGA_CLK_P" IOSTANDARD = "LVDS_25";
NET "FPGA_SYSRESET_N" LOC = L20;
NET "manual_rst_n_o" LOC = T22;
NET "manual_rst_n_o" IOSTANDARD = "LVCMOS33";
======================================
-- FRONT PANEL TTLS
======================================
-- LEDs
--
-- + ACT: CMOS 3.3V input
-------------------
NET "led_pw_o" LOC = F10;
NET "led_pw_o" IOSTANDARD = "LVCMOS33";
NET "led_pw_o" DRIVE = "4";
NET "led_pw_o" SLEW = "QUIETIO";
NET "led_err_o" LOC = F9;
NET "led_err_o" IOSTANDARD = "LVCMOS33";
NET "led_err_o" DRIVE = "4";
NET "led_err_o" SLEW = "QUIETIO";
NET "led_ttl_o" LOC = F8;
NET "led_ttl_o" IOSTANDARD = "LVCMOS33";
NET "led_ttl_o" DRIVE = "4";
NET "led_ttl_o" SLEW = "QUIETIO";
NET "led_o_front[1]" LOC = H3;
NET "led_o_front[1]" IOSTANDARD = "LVCMOS33";
NET "led_o_front[1]" DRIVE = "4";
NET "led_o_front[1]" SLEW = "QUIETIO";
NET "led_o_front[2]" LOC = J4;
NET "led_o_front[2]" IOSTANDARD = "LVCMOS33";
NET "led_o_front[2]" DRIVE = "4";
NET "led_o_front[2]" SLEW = "QUIETIO";
NET "led_o_front[3]" LOC = J3;
NET "led_o_front[3]" IOSTANDARD = "LVCMOS33";
NET "led_o_front[3]" DRIVE = "4";
NET "led_o_front[3]" SLEW = "QUIETIO";
NET "led_o_front[4]" LOC = K3;
NET "led_o_front[4]" IOSTANDARD = "LVCMOS33";
NET "led_o_front[4]" DRIVE = "4";
NET "led_o_front[4]" SLEW = "QUIETIO";
NET "led_o_front[5]" LOC = L4;
NET "led_o_front[5]" IOSTANDARD = "LVCMOS33";
NET "led_o_front[5]" DRIVE = "4";
NET "led_o_front[5]" SLEW = "QUIETIO";
NET "led_o_front[6]" LOC = L3;
NET "led_o_front[6]" IOSTANDARD = "LVCMOS33";
NET "led_o_front[6]" DRIVE = "4";
NET "led_o_front[6]" SLEW = "QUIETIO";
-------------------
-- TTL trigger inputs
--
-- + ACT family: CMOS/TTL 3.3V inputs
-------------------
NET "pulse_i_front[1]" LOC = T3;
NET "pulse_i_front[1]" IOSTANDARD = "LVCMOS33";
NET "pulse_i_front[2]" LOC = U4;
NET "pulse_i_front[2]" IOSTANDARD = "LVCMOS33";
NET "pulse_i_front[3]" LOC = W3;
NET "pulse_i_front[3]" IOSTANDARD = "LVCMOS33";
NET "pulse_i_front[4]" LOC = W4;
NET "pulse_i_front[4]" IOSTANDARD = "LVCMOS33";
NET "pulse_i_front[5]" LOC = V3;
NET "pulse_i_front[5]" IOSTANDARD = "LVCMOS33";
NET "pulse_i_front[6]" LOC = U3;
NET "pulse_i_front[6]" IOSTANDARD = "LVCMOS33";
-------------------
-- TTL Blocking pulses outputs
--
-- + BCT family (BiCMOS) TTL inputs
-------------------
NET "pulse_o_front[1]" LOC = D1;
NET "pulse_o_front[1]" IOSTANDARD = "LVTTL";
NET "pulse_o_front[1]" SLEW = "FAST";
NET "pulse_o_front[2]" LOC = E1;
NET "pulse_o_front[2]" IOSTANDARD = "LVTTL";
NET "pulse_o_front[2]" SLEW = "FAST";
NET "pulse_o_front[3]" LOC = F2;
NET "pulse_o_front[3]" IOSTANDARD = "LVTTL";
NET "pulse_o_front[3]" SLEW = "FAST";
NET "pulse_o_front[4]" LOC = F1;
NET "pulse_o_front[4]" IOSTANDARD = "LVTTL";
NET "pulse_o_front[4]" SLEW = "FAST";
NET "pulse_o_front[5]" LOC = G1;
NET "pulse_o_front[5]" IOSTANDARD = "LVTTL";
NET "pulse_o_front[5]" SLEW = "FAST";
NET "pulse_o_front[6]" LOC = H2;
NET "pulse_o_front[6]" IOSTANDARD = "LVTTL";
NET "pulse_o_front[6]" SLEW = "FAST";
-------------------
-- Bottom located GPIOs
--
-- + IN ACT family: CMOS/TTL 3.3V inputs
-- + OUT BCT family (BiCMOS): TTL inputs
-- Schematics name: INV_IN_*
---- renamed to INV_IN[*]
-------------------
NET "inv_i[1]" LOC = Y1;
NET "inv_i[1]" IOSTANDARD = "LVCMOS33";
NET "inv_i[2]" LOC = Y2;
NET "inv_i[2]" IOSTANDARD = "LVCMOS33";
NET "inv_i[3]" LOC = AA1;
NET "inv_i[3]" IOSTANDARD = "LVCMOS33";
NET "inv_i[4]" LOC = AA2;
NET "inv_i[4]" IOSTANDARD = "LVCMOS33";
NET "inv_o[1]" LOC = J1;
NET "inv_o[1]" IOSTANDARD = "LVTTL";
NET "inv_o[1]" SLEW = "FAST";
NET "inv_o[1]" DRIVE = "4";
NET "inv_o[2]" LOC = K2;
NET "inv_o[2]" IOSTANDARD = "LVTTL";
NET "inv_o[2]" SLEW = "FAST";
NET "inv_o[2]" DRIVE = "4";
NET "inv_o[3]" LOC = K1;
NET "inv_o[3]" IOSTANDARD = "LVTTL";
NET "inv_o[3]" SLEW = "FAST";
NET "inv_o[3]" DRIVE = "4";
NET "inv_o[4]" LOC = L1;
NET "inv_o[4]" IOSTANDARD = "LVTTL";
NET "inv_o[4]" SLEW = "FAST";
NET "inv_o[4]" DRIVE = "4";
======================================
-- RTM signals
======================================
-- Blocking input to FPGA
-- Schematics name: FPGA_BLO_IN_*
---- renamed to FPGA_BLO_IN[*]
-------------------
NET "pulse_i_rear[1]" LOC = W18;
NET "pulse_i_rear[1]" IOSTANDARD = "LVTTL";
NET "pulse_i_rear[2]" LOC = Y18;
NET "pulse_i_rear[2]" IOSTANDARD = "LVTTL";
NET "pulse_i_rear[3]" LOC = W17;
NET "pulse_i_rear[3]" IOSTANDARD = "LVTTL";
NET "pulse_i_rear[4]" LOC = Y17;
NET "pulse_i_rear[4]" IOSTANDARD = "LVTTL";
NET "pulse_i_rear[5]" LOC = Y16;
NET "pulse_i_rear[5]" IOSTANDARD = "LVTTL";
NET "pulse_i_rear[6]" LOC = Y15;
NET "pulse_i_rear[6]" IOSTANDARD = "LVTTL";
-------------------
-- Blocking driver triggers from FPGA
--
-- + OUT BCT family (BiCMOS): TTL inputs
-------------------
NET "pulse_o_rear[1]" LOC = V1;
NET "pulse_o_rear[1]" IOSTANDARD = "LVTTL";
NET "pulse_o_rear[1]" SLEW = "FAST";
NET "pulse_o_rear[2]" LOC = U1;
NET "pulse_o_rear[2]" IOSTANDARD = "LVTTL";
NET "pulse_o_rear[2]" SLEW = "FAST";
NET "pulse_o_rear[3]" LOC = T2;
NET "pulse_o_rear[3]" IOSTANDARD = "LVTTL";
NET "pulse_o_rear[3]" SLEW = "FAST";
NET "pulse_o_rear[4]" LOC = T1;
NET "pulse_o_rear[4]" IOSTANDARD = "LVTTL";
NET "pulse_o_rear[4]" SLEW = "FAST";
NET "pulse_o_rear[5]" LOC = R1;
NET "pulse_o_rear[5]" IOSTANDARD = "LVTTL";
NET "pulse_o_rear[5]" SLEW = "FAST";
NET "pulse_o_rear[6]" LOC = P2;
NET "pulse_o_rear[6]" IOSTANDARD = "LVTTL";
NET "pulse_o_rear[6]" SLEW = "FAST";
-------------------
-- Rear LEDs
--
-- + ACT family: CMOS/TTL 3.3V inputs
-------------------
NET "led_o_rear[1]" LOC = AB17;
NET "led_o_rear[1]" IOSTANDARD = "LVCMOS33";
NET "led_o_rear[1]" DRIVE = "4";
NET "led_o_rear[1]" SLEW = "QUIETIO";
NET "led_o_rear[2]" LOC = AB19;
NET "led_o_rear[2]" IOSTANDARD = "LVCMOS33";
NET "led_o_rear[2]" DRIVE = "4";
NET "led_o_rear[2]" SLEW = "QUIETIO";
NET "led_o_rear[3]" LOC = AA16;
NET "led_o_rear[3]" IOSTANDARD = "LVCMOS33";
NET "led_o_rear[3]" DRIVE = "4";
NET "led_o_rear[3]" SLEW = "QUIETIO";
NET "led_o_rear[4]" LOC = AA18;
NET "led_o_rear[4]" IOSTANDARD = "LVCMOS33";
NET "led_o_rear[4]" DRIVE = "4";
NET "led_o_rear[4]" SLEW = "QUIETIO";
NET "led_o_rear[5]" LOC = AB16;
NET "led_o_rear[5]" IOSTANDARD = "LVCMOS33";
NET "led_o_rear[5]" DRIVE = "4";
NET "led_o_rear[5]" SLEW = "QUIETIO";
NET "led_o_rear[6]" LOC = AB18;
NET "led_o_rear[6]" IOSTANDARD = "LVCMOS33";
NET "led_o_rear[6]" DRIVE = "4";
NET "led_o_rear[6]" SLEW = "QUIETIO";
======================================
-- VME CONNECTOR SIGNALS
======================================
-- I2C lines
--
-- + UBT: LVTTL input
-------------------
NET "SCL_I" LOC = F19;
NET "SCL_I" IOSTANDARD = "LVTTL";
NET "SCL_I" IOSTANDARD = "LVTTL";
NET "SCL_O" LOC = E20;
NET "SCL_O" IOSTANDARD = "LVTTL";
NET "SCL_O" DRIVE = "4";
NET "SCL_O" IOSTANDARD = "LVTTL";
NET "SCL_O" DRIVE = "4";
NET "SCL_OE" LOC = H18;
NET "SCL_OE" IOSTANDARD = "LVTTL";
NET "SCL_OE" IOSTANDARD = "LVTTL";
NET "SCL_OE" DRIVE = "4";
NET "SCL_OE" PULLDOWN;
NET "SCL_OE" PULLDOWN;
NET "SDA_I" LOC = G20;
NET "SDA_I" IOSTANDARD = "LVTTL";
NET "SDA_I" IOSTANDARD = "LVTTL";
NET "SDA_O" LOC = F20;
NET "SDA_O" IOSTANDARD = "LVTTL";
NET "SDA_O" SLEW = "FAST";
NET "SDA_O" DRIVE = "4";
NET "SDA_O" PULLUP;
NET "SDA_O" IOSTANDARD = "LVTTL";
NET "SDA_O" SLEW = "FAST";
NET "SDA_O" DRIVE = "4";
NET "SDA_O" PULLUP;
NET "SDA_OE" LOC = J19;
NET "SDA_OE" IOSTANDARD = "LVTTL";
NET "SDA_OE" SLEW = "FAST";
NET "SDA_OE" IOSTANDARD = "LVTTL";
NET "SDA_OE" SLEW = "FAST";
NET "SDA_OE" DRIVE = "4";
NET "SDA_OE" PULLDOWN;
##-------------------
##-- Geographical Address
##--
##-- + UBT: LVTTL input
##-------------------
NET "SDA_OE" PULLDOWN;
-------------------
-- Geographical Address
--
-- + UBT: LVTTL input
-------------------
NET "FPGA_GA[0]" LOC = H20;
NET "FPGA_GA[0]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[0]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[1]" LOC = J20;
NET "FPGA_GA[1]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[1]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[2]" LOC = K19;
NET "FPGA_GA[2]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[2]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[3]" LOC = K20;
NET "FPGA_GA[3]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[3]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[4]" LOC = L19;
NET "FPGA_GA[4]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[4]" IOSTANDARD = "LVTTL";
NET "FPGA_GAP" LOC = H19;
NET "FPGA_GAP" IOSTANDARD = "LVTTL";
NET "FPGA_GAP" IOSTANDARD = "LVTTL";
##======================================
##-- WHITE RABBIT
##======================================
##-- LEDs
##--
##-- + ACT: CMOS 3.3V input
##-------------------
NET "LED_LINK_UP" LOC = F7;
NET "LED_LINK_UP" IOSTANDARD = "LVCMOS33";
NET "LED_LINK_UP" DRIVE = "4";
NET "LED_LINK_UP" SLEW = "QUIETIO";
NET "LED_PPS" LOC = E6;
NET "LED_PPS" IOSTANDARD = "LVCMOS33";
NET "LED_PPS" DRIVE = "4";
NET "LED_PPS" SLEW = "QUIETIO";
NET "LED_WR_OK" LOC = E5;
NET "LED_WR_OK" IOSTANDARD = "LVCMOS33";
NET "LED_WR_OK" DRIVE = "4";
NET "LED_WR_OK" SLEW = "QUIETIO";
======================================
-- WHITE RABBIT
======================================
-- LEDs
--
-- + ACT: CMOS 3.3V input
-------------------
NET "led_link_up_o" LOC = F7;
NET "led_link_up_o" IOSTANDARD = "LVCMOS33";
NET "led_link_up_o" DRIVE = "4";
NET "led_link_up_o" SLEW = "QUIETIO";
NET "led_pps_o" LOC = E6;
NET "led_pps_o" IOSTANDARD = "LVCMOS33";
NET "led_pps_o" DRIVE = "4";
NET "led_pps_o" SLEW = "QUIETIO";
NET "led_wr_ok_o" LOC = E5;
NET "led_wr_ok_o" IOSTANDARD = "LVCMOS33";
NET "led_wr_ok_o" DRIVE = "4";
NET "led_wr_ok_o" SLEW = "QUIETIO";
##-------------------
##-- Thermo for UID
##-------------------
......@@ -281,13 +291,13 @@ NET "CLK20_VCXO" LOC = E16;
##-- + CMOS 3.3V input
##-------------------
## NET "FPGA_PLLDAC1_SYNC_N" LOC = AB15;
## NET "FPGA_PLLDAC1_SYNC_N" IOSTANDARD = "LVCMOS33";
## NET "FPGA_PLLDAC1_SYNC_N" IOSTANDARD = "LVCMOS33";
## NET "FPGA_PLLDAC2_SYNC_N" LOC = Y14;
## NET "FPGA_PLLDAC2_SYNC_N" IOSTANDARD = "LVCMOS33";
## NET "FPGA_PLLDAC2_SYNC_N" IOSTANDARD = "LVCMOS33";
## NET "FPGA_PLLDAC_DIN" LOC = AB14;
## NET "FPGA_PLLDAC_DIN" IOSTANDARD = "LVCMOS33";
## NET "FPGA_PLLDAC_DIN" IOSTANDARD = "LVCMOS33";
## NET "FPGA_PLLDAC_SCLK" LOC = AA14;
## NET "FPGA_PLLDAC_SCLK" IOSTANDARD = "LVCMOS33";
## NET "FPGA_PLLDAC_SCLK" IOSTANDARD = "LVCMOS33";
##-------------------
##-- SFP connection
##-------------------
......@@ -302,94 +312,94 @@ NET "CLK20_VCXO" LOC = E16;
##-- FPGA MGT lines
##-------------------
## NET "FPGAMGTCLK0_N" LOC = B10;
## NET "FPGAMGTCLK0_N" IOSTANDARD = "LVDS_12";
## NET "FPGAMGTCLK0_N" IOSTANDARD = "LVDS_12";
## NET "FPGAMGTCLK0_P" LOC = A10;
## NET "FPGAMGTCLK0_P" IOSTANDARD = "LVDS_12";
## NET "FPGAMGTCLK0_P" IOSTANDARD = "LVDS_12";
## NET "MGTSFPRX0_N" LOC = C7;
## NET "MGTSFPRX0_N" IOSTANDARD = "LVDS_12";
## NET "MGTSFPRX0_N" IOSTANDARD = "LVDS_12";
## NET "MGTSFPRX0_P" LOC = D7;
## NET "MGTSFPRX0_P" IOSTANDARD = "LVDS_12";
## NET "MGTSFPRX0_P" IOSTANDARD = "LVDS_12";
## NET "MGTSFPTX0_N" LOC = A6;
## NET "MGTSFPTX0_N" IOSTANDARD = "LVDS_12";
## NET "MGTSFPTX0_N" IOSTANDARD = "LVDS_12";
## NET "MGTSFPTX0_P" LOC = B6;
## NET "MGTSFPTX0_P" IOSTANDARD = "LVDS_12";
## NET "MGTSFPTX0_P" IOSTANDARD = "LVDS_12";
##======================================
##-- ADDITIONAL PINS
##======================================
##--
##-- + HC CMOS 3.3V input
##-------------------
NET "FPGA_OE" LOC = N4;
NET "FPGA_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_OE" DRIVE = "4";
NET "FPGA_OE" SLEW = "QUIETIO";
NET "FPGA_OE" PULLDOWN;
NET "FPGA_BLO_OE" LOC = N3;
NET "FPGA_BLO_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_OE" DRIVE = "4";
NET "FPGA_BLO_OE" SLEW = "QUIETIO";
NET "FPGA_BLO_OE" PULLDOWN;
NET "FPGA_TRIG_TTL_OE" LOC = M3;
NET "FPGA_TRIG_TTL_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_TTL_OE" DRIVE = "4";
NET "FPGA_TRIG_TTL_OE" SLEW = "QUIETIO";
NET "FPGA_TRIG_TTL_OE" PULLDOWN;
NET "FPGA_INV_OE" LOC = P3;
NET "FPGA_INV_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_INV_OE" DRIVE = "4";
NET "FPGA_INV_OE" SLEW = "QUIETIO";
NET "FPGA_INV_OE" PULLDOWN;
##-------------------
##-- Motherboard and piggyback IDs
##--
##-- + ACT: CMOS 3.3V input
##-------------------
# NET "FPGA_RTMM[0]" LOC = V21;
# NET "FPGA_RTMM[0]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_RTMM[1]" LOC = V22;
# NET "FPGA_RTMM[1]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_RTMM[2]" LOC = U22;
# NET "FPGA_RTMM[2]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_RTMP[0]" LOC = W22;
# NET "FPGA_RTMP[0]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_RTMP[1]" LOC = Y22;
# NET "FPGA_RTMP[1]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_RTMP[2]" LOC = Y21;
# NET "FPGA_RTMP[2]" IOSTANDARD = "LVCMOS33";
======================================
-- ADDITIONAL PINS
======================================
--
-- + HC CMOS 3.3V input
-------------------
NET "fpga_o_en" LOC = N4;
NET "fpga_o_en" IOSTANDARD = "LVCMOS33";
NET "fpga_o_en" DRIVE = "4";
NET "fpga_o_en" SLEW = "QUIETIO";
## NET "fpga_o_en" PULLDOWN;
NET "fpga_o_blo_en" LOC = N3;
NET "fpga_o_blo_en" IOSTANDARD = "LVCMOS33";
NET "fpga_o_blo_en" DRIVE = "4";
NET "fpga_o_blo_en" SLEW = "QUIETIO";
## NET "fpga_o_blo_en" PULLDOWN;
NET "fpga_o_ttl_en" LOC = M3;
NET "fpga_o_ttl_en" IOSTANDARD = "LVCMOS33";
NET "fpga_o_ttl_en" DRIVE = "4";
NET "fpga_o_ttl_en" SLEW = "QUIETIO";
## NET "fpga_o_ttl_en" PULLDOWN;
NET "fpga_o_inv_en" LOC = P3;
NET "fpga_o_inv_en" IOSTANDARD = "LVCMOS33";
NET "fpga_o_inv_en" DRIVE = "4";
NET "fpga_o_inv_en" SLEW = "QUIETIO";
NET "fpga_o_inv_en" PULLDOWN;
-------------------
-- Motherboard and piggyback IDs
--
-- + ACT: CMOS 3.3V input
-------------------
NET "FPGA_RTMM[0]" LOC = V21;
NET "FPGA_RTMM[0]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM[1]" LOC = V22;
NET "FPGA_RTMM[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM[2]" LOC = U22;
NET "FPGA_RTMM[2]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP[0]" LOC = W22;
NET "FPGA_RTMP[0]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP[1]" LOC = Y22;
NET "FPGA_RTMP[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP[2]" LOC = Y21;
NET "FPGA_RTMP[2]" IOSTANDARD = "LVCMOS33";
##-------------------
##-- Configuration Switches
##
##-- Schematics name EXTRA_SWITCH_*
##---- renamed to EXTRA_SWITCH[*]
##-------------------
NET "EXTRA_SWITCH[1]" LOC = F22;
NET "EXTRA_SWITCH[1]" IOSTANDARD = "LVTTL";
NET "EXTRA_SWITCH[2]" LOC = G22;
NET "EXTRA_SWITCH[2]" IOSTANDARD = "LVTTL";
NET "EXTRA_SWITCH[3]" LOC = H21;
NET "EXTRA_SWITCH[3]" IOSTANDARD = "LVTTL";
NET "switch_i" LOC = F22;
NET "switch_i" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[2]" LOC = G22;
# NET "EXTRA_SWITCH[2]" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[3]" LOC = H21;
# NET "EXTRA_SWITCH[3]" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[4]" LOC = H22;
# NET "EXTRA_SWITCH[4]" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[4]" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[5]" LOC = J22;
# NET "EXTRA_SWITCH[5]" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[5]" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[6]" LOC = K21;
# NET "EXTRA_SWITCH[6]" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[6]" IOSTANDARD = "LVTTL";
# NET "EXTRA_SWITCH[7]" LOC = K22;
# NET "EXTRA_SWITCH[7]" IOSTANDARD = "LVTTL";
NET "TTL" LOC = L22;
NET "TTL" IOSTANDARD = "LVTTL";
##-------------------
##-- ROM memory
##-------------------
# NET "FPGA_PROM_CCLK" LOC = Y20;
# NET "FPGA_PROM_CCLK" IOSTANDARD = "LVCMOS33";
# NET "FPGA_PROM_CSO_B_N" LOC = AA3;
# NET "FPGA_PROM_CSO_B_N" IOSTANDARD = "LVCMOS33";
# NET "FPGA_PROM_DIN" LOC = AA20;
# NET "FPGA_PROM_DIN" IOSTANDARD = "LVCMOS33";
# NET "FPGA_PROM_MOSI" LOC = AB20;
# NET "FPGA_PROM_MOSI" IOSTANDARD = "LVCMOS33";
# NET "EXTRA_SWITCH[7]" IOSTANDARD = "LVTTL";
NET "level" LOC = L22;
NET "level" IOSTANDARD = "LVTTL";
-------------------
-- ROM memory
-------------------
NET "FPGA_PROM_CCLK" LOC = Y20;
NET "FPGA_PROM_CCLK" IOSTANDARD = "LVCMOS33";
NET "FPGA_PROM_CSO_B_N" LOC = AA3;
NET "FPGA_PROM_CSO_B_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_PROM_DIN" LOC = AA20;
NET "FPGA_PROM_DIN" IOSTANDARD = "LVCMOS33";
NET "FPGA_PROM_MOSI" LOC = AB20;
NET "FPGA_PROM_MOSI" IOSTANDARD = "LVCMOS33";
##-------------------
##-- General purpose
##--
......@@ -407,15 +417,15 @@ NET "CLK20_VCXO" LOC = E16;
## NET "FPGA_HEADER_IN[5]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN[6]" LOC = B20;
## NET "FPGA_HEADER_IN[6]" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT[1]" LOC = F15;
NET "FPGA_HEADER_OUT[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT[2]" LOC = F16;
NET "FPGA_HEADER_OUT[2]" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT[3]" LOC = F17;
NET "FPGA_HEADER_OUT[3]" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT[4]" LOC = F14;
NET "FPGA_HEADER_OUT[4]" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT[5]" LOC = H14;
NET "FPGA_HEADER_OUT[5]" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT[6]" LOC = H13;
NET "FPGA_HEADER_OUT[6]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT[1]" LOC = F15;
## NET "FPGA_HEADER_OUT[1]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT[2]" LOC = F16;
## NET "FPGA_HEADER_OUT[2]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT[3]" LOC = F17;
## NET "FPGA_HEADER_OUT[3]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT[4]" LOC = F14;
## NET "FPGA_HEADER_OUT[4]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT[5]" LOC = H14;
## NET "FPGA_HEADER_OUT[5]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT[6]" LOC = H13;
## NET "FPGA_HEADER_OUT[6]" IOSTANDARD = "LVCMOS33";
hdl/IMAGES/image1/project/image1.xise 0 → 100644
View file @ a8566fda
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../rtl/image1_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_debounce.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_clk_divider.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/wb_xbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/wb_xbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/wb_xbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../constraints/FPGAbank.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../rtl/image1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
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<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="image1" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-11-21T17:40:19" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5445B05288FBBDDF0B997F95368EC1BD" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/image1_top" xil_pn:name="../constraints/FPGAbank.ucf"/>
</bindings>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
hdl/IMAGES/image1/rtl/image1_pkg.vhd 0 → 100644
View file @ a8566fda
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package image1_pkg is
component basic_trigger_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (
FPGA_CLK_P : in STD_LOGIC;
FPGA_CLK_N : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
--! WR LEDs not to let them ON
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1));
end component;
component i2c_slave_top
generic(g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns
port(sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_master_we_o : out STD_LOGIC;
wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_we_i : in STD_LOGIC;
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
pf_wb_addr_o : out STD_LOGIC;
rd_done_o : out STD_LOGIC;
wr_done_o : out STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0));
end component;
component m25p32_top
generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
port(wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
miso_word_rcv : out STD_LOGIC;
op_finished_o : out STD_LOGIC;
prom_mosi_o : out STD_LOGIC;
prom_cclk_o : out STD_LOGIC;
prom_cs0_b_n_o : out STD_LOGIC;
prom_din_i : in STD_LOGIC);
end component;
end image1_pkg;
package body image1_pkg is
end image1_pkg;
hdl/IMAGES/image1/rtl/image1_top.vhd
View file @ a8566fda
---------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 15:27:55 02/08/2012
-- Design Name: CONV_TTL_BLO image 1
-- Module Name: image1_top - Behavioral
-- Project Name: CONV_TTL_BLO
-- Target Devices: Spartan 6 SLX45T
-- Tool versions:
-- Description: image1_top.vhd comprises the integration of four vhdl modules:
-- 1.- Trigger
-- 2.- i2c_slave_wb_master
-- 3.- multiboot
-- 4.- wb_addr_decoder
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.image1_pkg.ALL;
entity image1_top is
generic(
g_NUMBER_OF_CHANNELS : INTEGER := 6
);
port(
LED_SYS_PW : out STD_LOGIC;
LED_SYS_ERROR : out STD_LOGIC;
LED_TTL : out STD_LOGIC;
LED_LINK_UP : out STD_LOGIC;
LED_PPS : out STD_LOGIC;
LED_WR_OK : out STD_LOGIC;
---------------------------------------
-- EXTRA_SWITCH
--
-- 1 rst
-- 2 general OE and TTL
-- 3 OE blocking
--------------------------------------
EXTRA_SWITCH : in STD_LOGIC_VECTOR(3 downto 1);
TTL : in STD_LOGIC;
CLK20_VCXO : in STD_LOGIC;
FPGA_OE : out STD_LOGIC;
FPGA_BLO_OE : out STD_LOGIC;
FPGA_TRIG_TTL_OE : out STD_LOGIC;
FPGA_INV_OE : out STD_LOGIC;
FPGA_BLO_IN : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_TRIG_BLO : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
PULSE_REAR_LED : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_INPUT_TTL : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_OUT_TTL : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
PULSE_FRONT_LED : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
INV_OUT : out STD_LOGIC_VECTOR(4 downto 1);
FPGA_HEADER_OUT : out STD_LOGIC_VECTOR(6 downto 1);
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_OE : out STD_LOGIC;
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_OE : out STD_LOGIC
);
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (
FPGA_CLK_P : in STD_LOGIC;
FPGA_CLK_N : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
--! WR LEDs not to let them ON
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_OE : out STD_LOGIC;
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_OE : out STD_LOGIC;
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
--! RTM identifiers, should match with the expected values
--! TODO: add matching
FPGA_RTMM : in STD_LOGIC_VECTOR(3 downto 0);
FPGA_RTMP : in STD_LOGIC_VECTOR(3 downto 0);
--! Pins of the SPI interface to write into the Flash memory
FPGA_PROM_CCLK : out STD_LOGIC;
FPGA_PROM_CSO_B_N : out STD_LOGIC;
FPGA_PROM_DIN : in STD_LOGIC;
FPGA_PROM_MOSI : out STD_LOGIC);
end image1_top;
architecture Behavioral of image1_top is
-------------------------------------------------------------------------------
-- MODULE MAPPING: wishbone slaves
-------------------------------------------------------------------------------
-- ID Device Wishbone wiring
-- 0 I2C wb_slave_*[0]
-- 1 Ch1 wb_slave_*[1]
-- 2 Ch2 wb_slave_*[2]
-- 3 Ch3 wb_slave_*[3]
-- 4 Ch4 wb_slave_*[4]
-- 5 Ch5 wb_slave_*[5]
-- 6 Ch6 wb_slave_*[6]
-- 7 Multiboot wb_slave_*[7]
-- 8 EEPROM wb_slave_*[8]
-- 9 White Rabbit wb_slave_*[9]
-------------------------------------------------------------------------------
constant c_WISHBONE_MODULES : INTEGER := 10;
constant c_WISHBONE_MEMWIDTH : INTEGER := 32;
constant c_WISHBONE_ADDRWIDTH : INTEGER := 16;
constant c_SLAVE_I2C : INTEGER := 0;
constant c_SLAVE_CH1 : INTEGER := 1;
constant c_SLAVE_CH2 : INTEGER := 2;
constant c_SLAVE_CH3 : INTEGER := 3;
constant c_SLAVE_CH4 : INTEGER := 4;
constant c_SLAVE_CH5 : INTEGER := 5;
constant c_SLAVE_CH6 : INTEGER := 6;
constant c_SLAVE_MULTIBOOT : INTEGER := 7;
constant c_SLAVE_EEPROM : INTEGER := 8;
constant c_SLAVE_WR : INTEGER := 9;
component trigger_top is
port (
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
led_o : out STD_LOGIC;
utc_i : in STD_LOGIC_VECTOR(95 downto 0);
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_ack_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR(2 downto 0)
);
end component;
component i2c_slave_top is
port (
sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_master_we_o : out STD_LOGIC;
wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_we_i : in STD_LOGIC;
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
pf_wb_addr_o : out STD_LOGIC;
rd_done_o : out STD_LOGIC;
wr_done_o : out STD_LOGIC;
i2c_addr : in STD_LOGIC_VECTOR(6 downto 0)
);
end component;
component multiboot_top is
port(
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC);
end component;
component wb_addr_decoder is
generic
(
g_WINDOW_SIZE : INTEGER := c_WISHBONE_ADDRWIDTH;
g_WB_SLAVES_NB : INTEGER := c_WISHBONE_MODULES
);
port
(
clk_i : in STD_LOGIC;
rst_n_i : in STD_LOGIC;
wbm_adr_i : in STD_LOGIC_VECTOR(31 downto 0);
wbm_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wbm_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wbm_stb_i : in STD_LOGIC;
wbm_we_i : in STD_LOGIC;
wbm_cyc_i : in STD_LOGIC;
wbm_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wbm_ack_o : out STD_LOGIC;
wbm_stall_o : out STD_LOGIC;
wb_adr_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_stb_o : out STD_LOGIC;
wb_we_o : out STD_LOGIC;
wb_cyc_o : out STD_LOGIC_VECTOR(g_WB_SLAVES_NB - 1 downto 0);
wb_dat_i : in STD_LOGIC_VECTOR((32*g_WB_SLAVES_NB) - 1 downto 0);
wb_ack_i : in STD_LOGIC_VECTOR(g_WB_SLAVES_NB - 1 downto 0);
wb_stall_i : in STD_LOGIC_VECTOR(g_WB_SLAVES_NB - 1 downto 0)
);
end component;
signal s_pulse_i : STD_LOGIC_VECTOR(6 downto 1);
signal s_pulse_o : STD_LOGIC_VECTOR(6 downto 1);
signal s_led_o : STD_LOGIC_VECTOR(6 downto 1);
signal s_led_sys_error_o : STD_LOGIC;
signal s_wb_i2c_master_stb_o : STD_LOGIC;
signal s_wb_i2c_master_cyc_o : STD_LOGIC;
signal s_wb_i2c_master_sel_o : STD_LOGIC_VECTOR(3 downto 0);
signal s_wb_i2c_master_we_o : STD_LOGIC;
signal s_wb_i2c_master_dat_i : STD_LOGIC_VECTOR(c_WISHBONE_MEMWIDTH - 1 downto 0);
signal s_wb_i2c_master_dat_o : STD_LOGIC_VECTOR(c_WISHBONE_MEMWIDTH - 1 downto 0);
signal s_wb_i2c_master_adr_o : STD_LOGIC_VECTOR(c_WISHBONE_ADDRWIDTH - 1 downto 0);
signal s_wb_i2c_master_ack_i : STD_LOGIC;
signal s_wb_i2c_master_rty_i : STD_LOGIC;
signal s_wb_i2c_master_err_i : STD_LOGIC;
signal s_wb_i2c_master_stall_o: STD_LOGIC;
signal s_pf_wb_adr_o : STD_LOGIC;
signal s_rd_done_o : STD_LOGIC;
signal s_wr_done_o : STD_LOGIC;
signal s_wb_slave_stb_i : STD_LOGIC;
signal s_wb_slave_cyc_i : STD_LOGIC_VECTOR(c_WISHBONE_MODULES - 1 downto 0);
signal s_wb_slave_ack_o : STD_LOGIC_VECTOR(c_WISHBONE_MODULES - 1 downto 0);
-- signal s_wb_slave_err_o : STD_LOGIC_VECTOR(c_WISHBONE_MODULES - 1 downto 0); -- Commented as wb_decoder is
-- signal s_wb_slave_rty_o : STD_LOGIC_VECTOR(c_WISHBONE_MODULES - 1 downto 0); -- not providing that signals
signal s_wb_slave_we_i : STD_LOGIC;
signal s_wb_slave_sel_i : STD_LOGIC_VECTOR(3 downto 0);
signal s_wb_slave_dat_i : STD_LOGIC_VECTOR(c_WISHBONE_MEMWIDTH - 1 downto 0);
signal s_wb_slave_dat_o : STD_LOGIC_VECTOR(c_WISHBONE_MODULES*c_WISHBONE_MEMWIDTH - 1 downto 0);
signal s_wb_slave_adr_i : STD_LOGIC_VECTOR(c_WISHBONE_ADDRWIDTH - 1 downto 0);
architecture Behavioral of image1_top is
-- This is added because a splitted assignation within a port cannot be put to
-- OPEN thanks to the so intuitive VHDL'93 syntax
signal s_wb_slave_adr_AUX93_i : STD_LOGIC_VECTOR(31 downto c_WISHBONE_ADDRWIDTH);
--! i2c_slave signals
signal wb_i2c_master_stb : STD_LOGIC;
signal wb_i2c_master_cyc : STD_LOGIC;
signal wb_i2c_master_sel : STD_LOGIC_VECTOR(xx downto 0);
signal wb_i2c_master_we : STD_LOGIC;
signal wb_i2c_master_data_i : STD_LOGIC_VECTOR(31 downto 0);
signal wb_i2c_master_data_o : STD_LOGIC_VECTOR(31 downto 0);
signal wb_i2c_master_addr_o : STD_LOGIC_VECTOR(xx downto 0);
signal wb_i2c_master_ack : STD_LOGIC;
signal wb_i2c_master_rty : STD_LOGIC;
signal wb_i2c_master_err : STD_LOGIC;
signal wb_i2c_slave_stb : STD_LOGIC;
signal wb_i2c_slave_cyc : STD_LOGIC;
signal wb_i2c_slave_sel : STD_LOGIC_VECTOR(xx downto 0);
signal wb_i2c_slave_we : STD_LOGIC;
signal wb_i2c_slave_data_i : STD_LOGIC_VECTOR(31 downto 0);
signal wb_i2c_slave_data_o : STD_LOGIC_VECTOR(31 downto 0);
signal wb_i2c_slave_addr_i : STD_LOGIC_VECTOR(xx downto 0);
signal wb_i2c_slave_ack : STD_LOGIC;
signal wb_i2c_slave_rty : STD_LOGIC;
signal wb_i2c_slave_err : STD_LOGIC;
--! m25p32 signals
signal wb_m25p32_we : STD_LOGIC;
signal wb_m25p32_stb : STD_LOGIC;
signal wb_m25p32_cyc : STD_LOGIC;
signal wb_m25p32_sel : STD_LOGIC_VECTOR(xx downto 0);
signal wb_m25p32_data_i : STD_LOGIC_VECTOR(31 downto 0);
signal wb_m25p32_data_o : STD_LOGIC_VECTOR(31 downto 0);
signal wb_m25p32_addr_i : STD_LOGIC_VECTOR(xx downto 0);
signal wb_m25p32_ack : STD_LOGIC;
signal wb_m25p32_rty : STD_LOGIC;
signal wb_m25p32_err : STD_LOGIC;
begin
LED_SYS_PW <= '0' ;
LED_SYS_ERROR <= s_led_sys_error_o;
LED_TTL <= '0' ;
LED_LINK_UP <= '1' ;
LED_PPS <= '1' ;
LED_WR_OK <= '1' ;
FPGA_INV_OE <= '0';
s_pulse_i <= not(FPGA_BLO_IN) or not(FPGA_INPUT_TTL);
FPGA_OUT_TTL <= s_pulse_o;
FPGA_TRIG_BLO <= s_pulse_o;
PULSE_REAR_LED <= not(s_led_o);
PULSE_FRONT_LED <= not(s_led_o);
INV_OUT(4 downto 1) <= (others => '1');
FPGA_HEADER_OUT <= (others => '1');
trigger_channels_loop: for i in 1 to g_NUMBER_OF_CHANNELS generate
begin
trigger_inst: trigger_top
port map(
pulse_i => s_pulse_i(i),
pulse_o => s_pulse_o(i),
led_o => s_led_o (i),
utc_i => (others => '0'),
wb_rst_i => EXTRA_SWITCH(1),
wb_clk => CLK20_VCXO,
wb_stb_i => s_wb_slave_stb_i,
wb_cyc_i => s_wb_slave_cyc_i ( i),
wb_ack_o => s_wb_slave_ack_o ( i),
wb_err_o => open,
wb_rty_o => open,
-- wb_err_o => s_wb_slave_err_o ( i),
-- wb_rty_o => s_wb_slave_rty_o ( i),
wb_we_i => s_wb_slave_we_i,
wb_sel_i => s_wb_slave_sel_i,
wb_data_i => s_wb_slave_dat_i,
wb_data_o => s_wb_slave_dat_o (c_WISHBONE_MEMWIDTH*(i+1) - 1 downto c_WISHBONE_MEMWIDTH*(i)),
wb_addr_i => s_wb_slave_adr_i(2 downto 0)
);
end generate trigger_channels_loop;
i2c_slave_wb_master_inst: i2c_slave_top
port map(
sda_oen => SDA_OE,
sda_i => SDA_I,
sda_o => SDA_O,
scl_oen => SCL_OE,
scl_i => SCL_I,
scl_o => SCL_O,
wb_clk => CLK20_VCXO,
wb_rst_i => EXTRA_SWITCH(1),
wb_master_stb_o => s_wb_i2c_master_stb_o,
wb_master_cyc_o => s_wb_i2c_master_cyc_o,
wb_master_sel_o => s_wb_i2c_master_sel_o,
wb_master_we_o => s_wb_i2c_master_we_o,
wb_master_data_i => s_wb_i2c_master_dat_i,
wb_master_data_o => s_wb_i2c_master_dat_o,
wb_master_addr_o => s_wb_i2c_master_adr_o,
wb_master_ack_i => s_wb_i2c_master_ack_i,
wb_master_rty_i => s_wb_i2c_master_rty_i,
wb_master_err_i => s_wb_i2c_master_err_i,
wb_slave_stb_i => s_wb_slave_stb_i,
wb_slave_cyc_i => s_wb_slave_cyc_i ( c_SLAVE_I2C),
wb_slave_sel_i => s_wb_slave_sel_i,
wb_slave_we_i => s_wb_slave_we_i,
wb_slave_data_i => s_wb_slave_dat_i((c_SLAVE_I2C+1)*c_WISHBONE_MEMWIDTH - 1 downto c_SLAVE_I2C*c_WISHBONE_MEMWIDTH),
wb_slave_data_o => s_wb_slave_dat_o((c_SLAVE_I2C+1)*c_WISHBONE_MEMWIDTH - 1 downto c_SLAVE_I2C*c_WISHBONE_MEMWIDTH),
wb_slave_addr_i => s_wb_slave_adr_i((c_SLAVE_I2C)*c_WISHBONE_ADDRWIDTH + 3 downto c_SLAVE_I2C*c_WISHBONE_ADDRWIDTH),
wb_slave_ack_o => s_wb_slave_ack_o ( c_SLAVE_I2C),
wb_slave_rty_o => open,
wb_slave_err_o => open,
pf_wb_addr_o => s_pf_wb_adr_o,
rd_done_o => s_rd_done_o,
wr_done_o => s_wr_done_o,
i2c_addr(4 downto 0) => FPGA_GA,
i2c_addr(6 downto 5) => (others => '0')
);
multiboot_inst: multiboot_top
port map(
wb_rst_i => EXTRA_SWITCH(1),
wb_clk => CLK20_VCXO,
wb_we_i => s_wb_slave_we_i,
wb_stb_i => s_wb_slave_stb_i,
wb_cyc_i => s_wb_slave_cyc_i(c_SLAVE_MULTIBOOT),
wb_sel_i => s_wb_slave_sel_i,
wb_data_i => s_wb_slave_dat_i,
wb_data_o => s_wb_slave_dat_o((c_SLAVE_MULTIBOOT+1)*c_WISHBONE_MEMWIDTH - 1 downto c_SLAVE_MULTIBOOT*c_WISHBONE_MEMWIDTH),
wb_addr_i => s_wb_slave_adr_i(3 downto 0),
wb_ack_o => s_wb_slave_ack_o(c_SLAVE_MULTIBOOT),
wb_rty_o => open,
wb_err_o => open
);
wb_addr_decoder_inst: wb_addr_decoder
port map(
clk_i => CLK20_VCXO,
rst_n_i => EXTRA_SWITCH(1),
wbm_stb_i => s_wb_i2c_master_stb_o,
wbm_cyc_i => s_wb_i2c_master_cyc_o,
wbm_sel_i => s_wb_i2c_master_sel_o,
wbm_we_i => s_wb_i2c_master_we_o,
wbm_dat_o => s_wb_i2c_master_dat_i,
wbm_dat_i => s_wb_i2c_master_dat_o,
wbm_adr_i(c_WISHBONE_ADDRWIDTH - 1 downto 0) => s_wb_i2c_master_adr_o,
wbm_adr_i(31 downto c_WISHBONE_ADDRWIDTH) => (others => '0'),
wbm_ack_o => s_wb_i2c_master_ack_i,
wbm_stall_o => s_wb_i2c_master_stall_o,
wb_stb_o => s_wb_slave_stb_i,
wb_cyc_o => s_wb_slave_cyc_i,
wb_sel_o => s_wb_slave_sel_i,
wb_we_o => s_wb_slave_we_i ,
wb_dat_i(c_SLAVE_EEPROM*c_WISHBONE_MEMWIDTH - 1 downto c_SLAVE_I2C*c_WISHBONE_MEMWIDTH) => s_wb_slave_dat_o(c_SLAVE_EEPROM*c_WISHBONE_MEMWIDTH - 1 downto c_SLAVE_I2C*c_WISHBONE_MEMWIDTH),
wb_dat_i((c_SLAVE_WR + 1)*c_WISHBONE_MEMWIDTH - 1 downto c_SLAVE_EEPROM*c_WISHBONE_MEMWIDTH) => (others => '0'),--open,
wb_dat_o => s_wb_slave_dat_i,
wb_adr_o(c_WISHBONE_ADDRWIDTH - 1 downto 0) => s_wb_slave_adr_i,
wb_adr_o(31 downto c_WISHBONE_ADDRWIDTH) => s_wb_slave_adr_AUX93_i,
wb_ack_i => s_wb_slave_ack_o,
wb_stall_i => (others => '0')
);
ttl_out: process (CLK20_VCXO)
begin
if rising_edge (CLK20_VCXO) then
if EXTRA_SWITCH(2) = '1' then
FPGA_OE <= '0';
FPGA_TRIG_TTL_OE <= '0';
else
FPGA_OE <= '1';
FPGA_TRIG_TTL_OE <= '1';
end if;
else
end if;
end process;
blo_out: process(CLK20_VCXO)
begin
if rising_edge (CLK20_VCXO) then
if EXTRA_SWITCH(3) = '1' then
FPGA_BLO_OE <= '1';
else
FPGA_BLO_OE <= '0';
end if;
else
end if;
end process;
gap_check: process(CLK20_VCXO)
variable parity : STD_LOGIC;
begin
if rising_edge (CLK20_VCXO) then
parity := FPGA_GA(0) XOR FPGA_GA(1) XOR FPGA_GA(2) XOR FPGA_GA(3) XOR FPGA_GA(4);
if (parity = FPGA_GAP) then
s_led_sys_error_o <= '0';
else
s_led_sys_error_o <= '1';
end if;
else
end if;
end process;
inst_basic_trigger: basic_trigger_top
port map(FPGA_CLK_P => FPGA_CLK_P,
FPGA_CLK_N => FPGA_CLK_N,
led_pw_o => led_pw_o,
led_err_o => led_err_o,
led_ttl_o => led_ttl_o,
fpga_o_en => fpga_o_en,
fpga_o_ttl_en => fpga_o_ttl_en,
fpga_o_inv_en => fpga_o_inv_en,
fpga_o_blo_en => fpga_o_blo_en,
level => level,
switch_i => switch_i,
manual_rst_n_o => manual_rst_n_o,
pulse_i_front => pulse_i_front,
pulse_o_front => pulse_o_front,
pulse_i_rear => pulse_i_rear,
pulse_o_rear => pulse_o_rear,
led_o_front => led_o_front,
led_o_rear => led_o_rear,
led_link_up_o => led_link_up_o,
led_pps_o => led_pps_o,
led_wr_ok_o => led_wr_ok_o,
inv_i => inv_i,
inv_o => inv_o);
--! We are always the slave so we disable writes into SCL pin
SCL_OEN <= '0';
inst_i2c_slave: i2c_slave_top
port map(sda_oen => SDA_OE,
sda_i => SDA_I,
sda_o => SDA_O,
scl_oen => open,
scl_i => SCL_I,
scl_o => SCL_O,
wb_clk => clk_i,
wb_rst_i => FPGA_SYSRESET_N,
wb_master_stb_o => wb_i2c_master_stb,
wb_master_cyc_o => wb_i2c_master_cyc,
wb_master_sel_o => wb_i2c_master_sel,
wb_master_we_o => wb_i2c_master_we,
wb_master_data_i => wb_i2c_master_data_i,
wb_master_data_o => wb_i2c_master_data_o,
wb_master_addr_o => wb_i2c_master_addr_o,
wb_master_ack_i => wb_i2c_master_ack,
wb_master_rty_i => wb_i2c_master_rty,
wb_master_err_i => wb_i2c_master_err,
wb_slave_stb_i => wb_i2c_slave_stb,
wb_slave_cyc_i => wb_i2c_slave_cyc,
wb_slave_sel_i => wb_i2c_slave_sel,
wb_slave_we_i => wb_i2c_slave_we,
wb_slave_data_i => wb_i2c_slave_data_i,
wb_slave_data_o => wb_i2c_slave_data_o,
wb_slave_addr_i => wb_i2c_slave_addr_i,
wb_slave_ack_o => wb_i2c_slave_ack,
wb_slave_rty_o => wb_i2c_slave_rty,
wb_slave_err_o => wb_i2c_slave_err,
pf_wb_addr_o => open,
rd_done_o => open,
wr_done_o => open,
i2c_addr_i => "00"&FPGA_GAP);
inst_m25p32: m25p32_top
port map(wb_rst_i => FPGA_SYSRESET_N,
wb_clk => clk_i,
wb_we_i => wb_m25p32_we,
wb_stb_i => wb_m25p32_stb,
wb_cyc_i => wb_m25p32_cyc,
wb_sel_i => wb_m25p32_sel,
wb_data_i => wb_m25p32_data_i,
wb_data_o => wb_m25p32_data_o,
wb_addr_i => wb_m25p32_addr_i,
wb_ack_o => wb_m25p32_ack,
wb_rty_o => wb_m25p32_rty,
wb_err_o => wb_m25p32_err,
miso_word_rcv => open,
op_finished_o => open,
prom_mosi_o => FPGA_PROM_MOSI,
prom_cclk_o => FPGA_PROM_CCLK,
prom_cs0_b_n_o => FPGA_PROM_CSO_B_N,
prom_din_i => FPGA_PROM_DIN);
end Behavioral;
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