Skip to content

C
Conv TTL Blocking
Commit a9e62b25 authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
Browse files
Options

Committed last modification on IP cores for remote programming before merging:… 

Committed last modification on IP cores for remote programming before merging: ctdah_lib, i2c_slave_wb_master, m25p32, multiboot, spi_master_multifield
parent 078498ba
Hide whitespace changes
Inline Side-by-side
Showing with 1046 additions and 1113 deletions
hdl/i2c_slave_wb_master/rtl/i2c_bit.vhd
View file @ a9e62b25
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 00:47:34 10/26/2011
--
-- Create Date: 00:47:34 10/26/2011
-- Design Name: i2c bit recognition fsm
-- Module Name: i2c_bit - Behavioral
-- Module Name: i2c_bit - Behavioral
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Tool versions:
-- Description: This is the fsm for the recognition of a bit. It offers some
-- interrupting lines to the upper level (i2c_slave_core.vhd)
-- which is responsible for managing byte level transactions
--
-- Dependencies: The inputs should be debounced: i2c_debouncer.vhd
--
-- Revision:
-- Revision:
-- Revision 0.01 - File Created
-- 0.1 - Module works with no reported issues.
-- 1.0 - Code revamped. Now is clearer and easier to read.
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
......@@ -57,7 +57,7 @@ architecture Behavioral of i2c_bit is
--! It specifies the maximum number of stages that will be employed for
--! deglitching. Clocked with wb_clk_i
constant c_MAX_GLITCH_DELAY : NATURAL := 6;
constant c_MAX_GLITCH_DELAY : NATURAL := 6;
--! Three delay stages out of six
constant c_GLITCH_MASK : STD_LOGIC_VECTOR (5 downto 0) := "000111";
......@@ -126,8 +126,8 @@ begin
s_scl_rising <= '1';
end if;
else
s_scl_rising <= '0';
s_scl_falling <= '0';
s_scl_rising <= '0';
s_scl_falling <= '0';
end if;
else
end if;
......
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
View file @ a9e62b25
--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:56:55 10/25/2011
--
-- Create Date: 11:56:55 10/25/2011
-- Design Name: I2C slave register HDL
-- Module Name: i2c_regs - Behavioral
-- Module Name: i2c_regs - Behavioral
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Tool versions:
-- Description: This is the HDL that holds all the register of the I2C slave
-- core
--
......@@ -15,10 +15,10 @@
-- 1.- CTR0 Sets up the control register: enable, start, i2c address
-- 2.- CTR1 Sets up the threshold for detection signals in RX and TX buffers
--
-- Revision:
-- Revision:
-- Revision 0.01 - File Created
-- 1.0 - Stable version
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
......@@ -129,7 +129,7 @@ begin
if rising_edge(wb_clk) then
if i2c_master_WB_BASIC_fsm = S3_WB_ACK then
s_wb_master_ack_retries(0) <= '1';
for i in 1 to c_RETRY_LENGTH - 1 loop
for i in 1 to c_RETRY_LENGTH - 1 loop
s_wb_master_ack_retries(i) <= s_wb_master_ack_retries(i-1);
end loop;
else
......@@ -147,11 +147,11 @@ begin
--! @param i2c_master_WB_BASIC_fsm fsm of the wishone master interface
wbmaster_comb_proc: process(i2c_master_WB_BASIC_fsm)
begin
s_wb_master_we_o <= '0';
wb_master_stb_o <= '0';
wb_master_cyc_o <= '0';
s_wb_master_we_o <= '0';
wb_master_stb_o <= '0';
wb_master_cyc_o <= '0';
wb_master_sel_o <= (others => '0');
wb_master_data_o <= (others => '0');
wb_master_data_o <= (others => '0');
wb_master_addr_o <= (others => '0');
-- s_DRXA <= (others => '0');
-- s_DRXB <= (others => '0');
......@@ -224,7 +224,7 @@ begin
and s_wb_slave_ack = '0'
and s_wb_slave_rty = '0'
and s_wb_slave_err = '0' then
case wb_slave_we_i is
case wb_slave_we_i is
when '1' =>
s_wb_slave_ack <= '1';
case s_wb_slave_addr is
......@@ -278,7 +278,7 @@ begin
when S0_IDLE =>
if pf_wb_addr_i = '1' then
i2c_master_WB_BASIC_fsm <= S1P_WB_RD_RQT;
elsif rd_done_i = '1' then
elsif rd_done_i = '1' then
i2c_master_WB_BASIC_fsm <= S2P_WB_WR_RQT;
end if;
when S1P_WB_RD_RQT =>
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
View file @ a9e62b25
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:29:56 10/25/2011
-- Design Name: I2C Slave to Wishbone bridge
-- Module Name: i2c_slave_core - Behavioral
--
-- Create Date: 11:29:56 10/25/2011
-- Design Name: I2C Slave to Wishbone bridge
-- Module Name: i2c_slave_core - Behavioral
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Tool versions:
-- Description: This is a bridge from I2C to Wishbone.
-- The module consist on the following interfaces:
-- - I2C interface
......@@ -37,17 +37,17 @@
-- Both the Wishbone master and slave interface access control
-- and all configuration registers can be found in:
-- --> ./i2c_regs.vhd
--
--
-- Dependencies: i2c_bit.vhd, FIFO_stack.vhd, FIFO_dispatcher.vhd, gc_ff.vhd
--
-- Revision:
-- Revision:
-- Revision 0.01 - File Created
-- 0.1 - Initial submission. I2C instructions for Read and Write work.
-- 1.0 - Code completely revamped. Code tested with a code coverage of
-- 81.5% with the testbench provided in:
-- ../test/i2c_slave_test_top_tb.vhd
--
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
......@@ -142,7 +142,7 @@ signal s_i2c_addr_ctr0 : STD_LOGIC_VECTOR(7 downto 0);
signal s_i2c_addr : STD_LOGIC_VECTOR(7 downto 0);
-------------------------------------------------------------------------------
-- i2c signals
-- i2c signals
-------------------------------------------------------------------------------
signal s_sda_o : STD_LOGIC;
signal s_sda_oen : STD_LOGIC;
......@@ -164,7 +164,7 @@ signal s_byte_cnt_en : STD_LOGIC := '0';
signal s_tx_fifo_load_TX : STD_LOGIC;
signal s_tx_fifo_flush : STD_LOGIC;
signal s_tx_fifo_oen : STD_LOGIC;
signal s_tx_fifo_reg_o : STD_LOGIC_VECTOR (c_DATA_WIDTH -1 downto 0);
signal s_tx_fifo_reg_o : STD_LOGIC_VECTOR (c_DATA_WIDTH -1 downto 0);
-- Interrupting signals (i2c_bit.vhd)
signal s_start_o : STD_LOGIC;
......@@ -281,9 +281,9 @@ begin
procedure shift_DRX is
begin
s_DRX_slv(s_DRX_slv'length - 1) <= s_rcved_o;
s_DRX_slv(s_DRX_slv'length - 1) <= s_rcved_o;
for i in 1 to s_DRX_slv'length - 1 loop
s_DRX_slv(i-1) <= s_DRX_slv(i);
s_DRX_slv(i-1) <= s_DRX_slv(i);
end loop;
end procedure;
......@@ -315,7 +315,7 @@ begin
s_i2c_addr_ctr0(7 downto 1) <= STD_LOGIC_VECTOR(s_CTR0.I2C_ADDR);
s_i2c_addr(0) <= '0';
gen_i2c: for i in 1 to 7 generate
gen_i2c: for i in 1 to 7 generate
s_i2c_addr(8-i) <= s_i2c_addr_ctr0(i);
end generate gen_i2c;
......@@ -360,7 +360,7 @@ begin
begin
if rising_edge(clk) then
wr_done_o <= '0';
if i2c_SLA_fsm = S6_WAIT_START_PAUSE
if i2c_SLA_fsm = S6_WAIT_START_PAUSE
and i2c_SLA_fsm_d0 = S5W3_NACK then
wr_done_o <= '1';
end if;
......@@ -474,7 +474,7 @@ begin
end if;
when S7_PAUSE_DETECT =>
null;
when others =>
when others =>
s_bit_cnt_rst <= '1';
s_byte_cnt_rst <= '1';
end case;
......@@ -614,7 +614,7 @@ begin
check_start_stop;
end if;
end if;
when S4_DETECT_OPERATION =>
when S4_DETECT_OPERATION =>
if s_bit_done = '1' then
if s_start_o = '1' then
i2c_SLA_fsm <= S5W0_RESTART;
......@@ -668,7 +668,7 @@ begin
i2c_SLA_fsm <= S6_WAIT_START_PAUSE;
check_start_stop;
end if;
when S5W2_WRITE_SDA =>
when S5W2_WRITE_SDA =>
if s_bit_done = '1' then
if s_bit_cnt = 7 then
i2c_SLA_fsm <= S5W2A_WRITE_SDA_ACK;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd
View file @ a9e62b25
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:03:11 06/19/2012
-- Design Name:
-- Module Name: i2c_slave_pkg - Behavioral
--
-- Create Date: 11:03:11 06/19/2012
-- Design Name:
-- Module Name: i2c_slave_pkg - Behavioral
-- Project Name: CTDAH/SVEC
-- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description: Package for the i2c_slave
--
-- Dependencies:
-- Dependencies:
--
-- Revision: 0.1
-- 0.01 + File Created
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
......@@ -38,10 +38,10 @@ package i2c_slave_pkg is
-------------------------------------------------------------------------------
-- This is the declaration area of the constants used in other components:
-- c_COUNTER_WIDTH bit length of the gc_counter
-- c_DATA_WIDTH width of the data to be stored in FIFO_stack
-- c_DATA_WIDTH width of the data to be stored in FIFO_stack
-- and FIFO_dispatchers.
-- c_RX_STACK_DEPTH depth of FIFO_stack
-- c_TX_STACK_DEPTH depth of FIFO_dispatch
-- c_TX_STACK_DEPTH depth of FIFO_dispatch
-------------------------------------------------------------------------------
constant c_COUNTER_WIDTH : NATURAL := 8;
constant c_DATA_WIDTH : NATURAL := 8;
......@@ -76,7 +76,7 @@ package i2c_slave_pkg is
type r_CTR0 is
record
I2C_OP : STD_LOGIC;
I2C_ADDR : UNSIGNED( 7 downto 1);
I2C_ADDR : UNSIGNED( 7 downto 1);
BIA : UNSIGNED(11 downto 8);
BRD : UNSIGNED(19 downto 12);
BWR : UNSIGNED(27 downto 20);
......@@ -89,7 +89,7 @@ package i2c_slave_pkg is
-- LT register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-only
-- Wishbone access: Read-only
------------------------------------
-- BIT NAME Description
-- 7-0 WBCP WishBone Clock Period
......@@ -282,7 +282,7 @@ package body i2c_slave_pkg is
variable v_return : STD_LOGIC_VECTOR(31 downto 0);
begin
v_return(7 downto 0) := STD_LOGIC_VECTOR(r_register.WBCP);
v_return(31 downto 8) := STD_LOGIC_VECTOR(r_register.SCLP);
v_return(31 downto 8) := STD_LOGIC_VECTOR(r_register.SCLP);
return v_return;
end function;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
View file @ a9e62b25
--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT CHANGED
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 18:15:56 11/09/2011
--
-- Create Date: 18:15:56 11/09/2011
-- Design Name: A I2C slave with wishbone slave output and interrupt for MCU
-- Module Name: i2c_slave_top - Behavioral
-- Project Name: CTDAH
-- Target Devices:
-- Tool versions:
-- Description:
-- Module Name: i2c_slave_top - Behavioral
-- Project Name: CTDAH
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
-- Dependencies:
--
-- Revision:
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
......@@ -120,21 +120,21 @@ begin
port map(pf_wb_addr_i => s_pf_wb_addr,
pf_wb_data_o => s_pf_wb_data,
rd_done_i => s_rd_done,
wr_done_i => s_wr_done,
wr_done_i => s_wr_done,
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_master_we_o => wb_master_we_o,
wb_master_stb_o => wb_master_stb_o,
wb_master_cyc_o => wb_master_cyc_o,
wb_master_sel_o => wb_master_sel_o,
wb_master_data_i => wb_master_data_i,
wb_master_data_o => wb_master_data_o,
wb_master_addr_o => wb_master_addr_o,
wb_master_ack_i => wb_master_ack_i,
wb_master_rty_i => wb_master_rty_i,
wb_master_err_i => wb_master_err_i,
wb_master_we_o => wb_master_we_o,
wb_master_stb_o => wb_master_stb_o,
wb_master_cyc_o => wb_master_cyc_o,
wb_master_sel_o => wb_master_sel_o,
wb_master_data_i => wb_master_data_i,
wb_master_data_o => wb_master_data_o,
wb_master_addr_o => wb_master_addr_o,
wb_master_ack_i => wb_master_ack_i,
wb_master_rty_i => wb_master_rty_i,
wb_master_err_i => wb_master_err_i,
wb_slave_we_i => wb_slave_we_i,
wb_slave_stb_i => wb_slave_stb_i,
......
hdl/i2c_slave_wb_master/test/i2c_bit_tb.vhd
View file @ a9e62b25
--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 12:07:51 10/26/2011
......@@ -7,22 +7,22 @@
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_bit_tb.vhd
-- Project Name: CTDAH
-- Target Device: Spartan 6
-- Tool versions:
-- Description:
--
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: i2c_bit
--
--
-- Dependencies:
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
......@@ -30,18 +30,18 @@ library work;
USE ieee.std_logic_1164.ALL;
USE work.i2c_slave_pkg.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY i2c_bit_tb IS
END i2c_bit_tb;
ARCHITECTURE behavior OF i2c_bit_tb IS
ARCHITECTURE behavior OF i2c_bit_tb IS
-- Component Declaration for the Unit Under Test (UUT)
component i2c_bit
port(
rst_i : IN std_logic;
......@@ -56,7 +56,7 @@ ARCHITECTURE behavior OF i2c_bit_tb IS
rcved_o : OUT std_logic
);
end component;
--Inputs
signal rst_i : std_logic := '0';
signal wb_clk_i : std_logic := '0';
......@@ -70,12 +70,12 @@ ARCHITECTURE behavior OF i2c_bit_tb IS
signal rcved_o : std_logic;
signal done_o : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant wb_clk_i_period : time := 50 ns; -- @ 20 MHz
constant scl_i_period : time := 2500 ns; -- @ 400 KHz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: i2c_bit
PORT MAP (rst_i => rst_i,
......@@ -104,7 +104,7 @@ BEGIN
scl_i <= '0';
wait for scl_i_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure init_cond is
......@@ -140,7 +140,7 @@ BEGIN
end loop;
end addr_send;
procedure pause is
procedure pause is
begin
sda_i <= '0';
wait until rising_edge(scl_i);
......@@ -150,7 +150,7 @@ BEGIN
wait for scl_i_period/4;
end pause;
begin
begin
init_cond;
rst;
......
hdl/i2c_slave_wb_master/test/i2c_master_driver.vhd
View file @ a9e62b25
......@@ -16,11 +16,11 @@ entity i2c_master_driver is
g_WB_ADDR_LENGTH : NATURAL := 16;
g_SCL_PERIOD : TIME := 250 us);
port(tb_clk : in STD_LOGIC;
sda_master_i : in STD_LOGIC;
sda_master_o : out STD_LOGIC;
scl_master_o : out STD_LOGIC;
i2c_addr_op_i : in STD_LOGIC_VECTOR(7 downto 0);
wishbone_addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0);
wr_data_i : in STD_LOGIC_VECTOR(g_WR_DATA_LENGTH - 1 downto 0);
......@@ -36,7 +36,7 @@ entity i2c_master_driver is
read_done_o : out STD_LOGIC);
end i2c_master_driver;
architecture Behavioral of i2c_master_driver is
architecture Behavioral of i2c_master_driver is
type i2c_byte_field is (ADDRESS_0,
ADDRESS_1,
......@@ -76,7 +76,7 @@ begin
start_done_o <= s_start_done;
pause_done_o <= s_pause_done;
write_done_o <= s_write_done;
read_done_o <= s_read_done;
read_done_o <= s_read_done;
scl_clk_process: process
begin
......@@ -91,7 +91,7 @@ begin
--! @brief Function that returns strings for the acked field to be
--! logged.
--! @param byte_type i2c_byte_field type to be translated into a string
--! @param byte_type i2c_byte_field type to be translated into a string
function get_field(byte_type : i2c_byte_field) return STRING is
variable v_return : STRING (16 downto 1) := (others => ' ');
begin
......@@ -234,7 +234,7 @@ begin
variable v_bit_rcv : STD_LOGIC;
begin
wait until rising_edge(s_scl_clk);
v_bit_rcv := sda_master_i;
v_bit_rcv := sda_master_i;
for i in 0 to (g_SCL_PERIOD/2)/(1 ns) - 1 loop
if v_bit_rcv /= sda_master_i then
--! Here we report an error
......@@ -292,10 +292,10 @@ begin
v_i2c_addr_op(0) := '0';
send_byte(order_i2c_addr_op(v_i2c_addr_op));
check_ack(s_test_id, "WRITE", ADDRESS_0);
--! 2.- Send wishbone address high
--! 2.- Send wishbone address high
send_byte(wishbone_addr_i(15 downto 8));
check_ack(s_test_id, "WRITE", WISHBONE_HIGH);
--! 3.- Send wishbone address low
--! 3.- Send wishbone address low
send_byte(wishbone_addr_i(7 downto 0));
check_ack(s_test_id, "WRITE", WISHBONE_LOW);
--! 4.- Send DATA0
......@@ -322,10 +322,10 @@ begin
v_i2c_addr_op(0) := '0';
send_byte(order_i2c_addr_op(v_i2c_addr_op));
check_ack(s_test_id, " READ", ADDRESS_0);
--! 2.- Send wishbone address high
--! 2.- Send wishbone address high
send_byte(wishbone_addr_i(15 downto 8));
check_ack(s_test_id, " READ", WISHBONE_HIGH);
--! 3.- Send wishbone address low
--! 3.- Send wishbone address low
send_byte(wishbone_addr_i(7 downto 0));
check_ack(s_test_id, " READ", WISHBONE_LOW);
--! 4.- We have to place a start condition
......
hdl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd
View file @ a9e62b25
......@@ -3,27 +3,27 @@
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 10:59:15 10/31/2011
-- Design Name:
-- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd
-- Project Name: i2c_slave_wb_master
-- Target Device: Spartan 6
-- Tool versions:
-- Description:
--
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: i2c_slave_top
--
--
-- Dependencies:
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.1 - File Modified. Now the sda_i line is more acurately accessed.
-- Additional Comments:
--
-- Notes:
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
......@@ -34,11 +34,11 @@ use IEEE.NUMERIC_STD.ALl;
use std.textio.ALL;
use work.i2c_tb_pkg.ALL;
use work.wishbone_driver_pkg.ALL;
entity i2c_slave_top_tb is
end i2c_slave_top_tb;
architecture behavior of i2c_slave_top_tb is
architecture behavior of i2c_slave_top_tb is
--! Connections for i2c_slave_top
signal sda_slave_oen : STD_LOGIC;
......@@ -95,13 +95,13 @@ architecture behavior of i2c_slave_top_tb is
signal s_wb_driver_data_i : STD_LOGIC_VECTOR(31 downto 0)
:= (others => '0');
signal s_wb_driver_data_o : STD_LOGIC_VECTOR(31 downto 0);
signal s_wb_driver_addr_i : STD_LOGIC_VECTOR(3 downto 0)
signal s_wb_driver_addr_i : STD_LOGIC_VECTOR(3 downto 0)
:= (others => '0');
signal s_wb_driver_write_i : STD_LOGIC := '0';
signal s_wb_driver_write_done_o : STD_LOGIC;
signal s_wb_driver_read_i : STD_LOGIC := '0';
signal s_wb_driver_read_done_o : STD_LOGIC;
signal s_wb_driver_write_i : STD_LOGIC := '0';
signal s_wb_driver_write_done_o : STD_LOGIC;
signal s_wb_driver_read_i : STD_LOGIC := '0';
signal s_wb_driver_read_done_o : STD_LOGIC;
signal s_i2c_addr_op : STD_LOGIC_VECTOR(7 downto 0)
......@@ -127,7 +127,7 @@ architecture behavior of i2c_slave_top_tb is
type i2c_start_op is (S0_READ,
S1_WRITE);
begin
begin
......@@ -147,16 +147,16 @@ begin
wb_clk => wb_clk,
wb_rst_i => wb_rst_i,
wb_master_stb_o => wb_master_stb_o,
wb_master_cyc_o => wb_master_cyc_o,
wb_master_sel_o => wb_master_sel_o,
wb_master_we_o => wb_master_we_o,
wb_master_data_i => wb_master_data_i,
wb_master_data_o => wb_master_data_o,
wb_master_addr_o => wb_master_addr_o,
wb_master_ack_i => wb_master_ack_i,
wb_master_rty_i => wb_master_rty_i,
wb_master_err_i => wb_master_err_i,
wb_master_stb_o => wb_master_stb_o,
wb_master_cyc_o => wb_master_cyc_o,
wb_master_sel_o => wb_master_sel_o,
wb_master_we_o => wb_master_we_o,
wb_master_data_i => wb_master_data_i,
wb_master_data_o => wb_master_data_o,
wb_master_addr_o => wb_master_addr_o,
wb_master_ack_i => wb_master_ack_i,
wb_master_rty_i => wb_master_rty_i,
wb_master_err_i => wb_master_err_i,
wb_slave_stb_i => wb_slave_stb_i,
wb_slave_cyc_i => wb_slave_cyc_i,
......@@ -177,24 +177,24 @@ begin
i2c_driver: i2c_master_driver
port map(tb_clk => wb_clk,
sda_master_i => sda_slave_o,
sda_master_o => sda_slave_i,
scl_master_o => scl_slave_i,
i2c_addr_op_i => s_i2c_addr_op,
wishbone_addr_i => s_wishbone_addr,
wr_data_i => s_wr_data,
sda_master_i => sda_slave_o,
sda_master_o => sda_slave_i,
scl_master_o => scl_slave_i,
i2c_addr_op_i => s_i2c_addr_op,
wishbone_addr_i => s_wishbone_addr,
wr_data_i => s_wr_data,
rd_data_o => s_rd_data,
start_i => s_i2c_driver_start,
start_done_o => s_i2c_driver_start_done,
pause_i => s_i2c_driver_pause,
pause_done_o => s_i2c_driver_pause_done,
write_i => s_i2c_driver_write,
write_done_o => s_i2c_driver_write_done,
read_i => s_i2c_driver_read,
read_done_o => s_i2c_driver_read_done);
start_i => s_i2c_driver_start,
start_done_o => s_i2c_driver_start_done,
pause_i => s_i2c_driver_pause,
pause_done_o => s_i2c_driver_pause_done,
write_i => s_i2c_driver_write,
write_done_o => s_i2c_driver_write_done,
read_i => s_i2c_driver_read,
read_done_o => s_i2c_driver_read_done);
wb_driver: wishbone_driver
......@@ -206,7 +206,7 @@ begin
wb_stb_o => wb_driver_stb_o,
wb_cyc_o => wb_driver_cyc_o,
wb_sel_o => wb_driver_sel_o,
wb_we_o => wb_driver_we_o,
wb_we_o => wb_driver_we_o,
wb_data_i => wb_driver_data_i,
wb_data_o => wb_driver_data_o,
wb_addr_o => wb_driver_addr_o,
......@@ -225,7 +225,7 @@ begin
wb_slave_cyc_i <= wb_master_cyc_o when s_feedback_wb_bus = '1'
else wb_driver_cyc_o;
wb_slave_stb_i <= wb_master_stb_o when s_feedback_wb_bus = '1'
wb_slave_stb_i <= wb_master_stb_o when s_feedback_wb_bus = '1'
else wb_driver_stb_o;
wb_slave_sel_i <= wb_master_sel_o when s_feedback_wb_bus = '1'
else wb_driver_sel_o;
......@@ -265,7 +265,7 @@ begin
s_feedback_wb_bus <= '1';
wait until rising_edge(wb_clk);
end procedure;
procedure unset_i2c_wb_feedback is
begin
s_feedback_wb_bus <= '0';
......
hdl/i2c_slave_wb_master/test/i2c_tb_pkg.vhd
View file @ a9e62b25
......@@ -65,11 +65,11 @@ package i2c_tb_pkg is
g_WB_ADDR_LENGTH : NATURAL := c_WB_ADDR_LENGTH;
g_SCL_PERIOD : TIME := c_SCL_I_PERIOD);
port(tb_clk : in STD_LOGIC;
sda_master_i : in STD_LOGIC;
sda_master_o : out STD_LOGIC;
scl_master_o : out STD_LOGIC;
i2c_addr_op_i : in STD_LOGIC_VECTOR(7 downto 0);
wishbone_addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0);
wr_data_i : in STD_LOGIC_VECTOR(g_WR_DATA_LENGTH - 1 downto 0);
......
hdl/m25p32/rtl/m25p32_core.vhd
View file @ a9e62b25
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
......@@ -15,23 +15,23 @@
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 23:57:51 06/10/2012
--
-- Create Date: 23:57:51 06/10/2012
-- Design Name: m25p32 wishbone access
-- Module Name: m25p32_core - Behavioral
-- Module Name: m25p32_core - Behavioral
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Tool versions:
-- Description: This is the logic that governs the access to the m25p32 Non
-- volatile Flash memory
--
-- Dependencies:
-- Dependencies:
--
-- Revision:
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
......@@ -51,10 +51,10 @@ entity m25p32_core is
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
mosi_o : out STD_LOGIC;
miso_i : in STD_LOGIC;
sclk_o : out STD_LOGIC;
ss_n_o : out STD_LOGIC;
mosi_o : out STD_LOGIC;
miso_i : in STD_LOGIC;
sclk_o : out STD_LOGIC;
ss_n_o : out STD_LOGIC;
wr_data_i : in STD_LOGIC_VECTOR(g_PAGE_SIZE*8 - 1 downto 0);
rd_data_o : out STD_LOGIC_VECTOR(r_SPI3'a_length - 1 downto 0);
......@@ -127,12 +127,12 @@ begin
g_data_length => c_PAGE_SIZE,
g_clk_i_period => c_CLK_I_PERIOD
) port map(
rst_i => wb_rst_i,
clk_i => wb_clk,
rst_i => wb_rst_i,
clk_i => wb_clk,
inst_i => s_inst_spi,
addr_i => s_addr_spi,
data_i => s_data_i_spi,
inst_i => s_inst_spi,
addr_i => s_addr_spi,
data_i => s_data_i_spi,
SPI0_i => s_SPI0_slv,
SPI1_i => s_SPI1_slv,
......@@ -144,7 +144,7 @@ begin
spi_mosi_o => mosi_o,
spi_miso_i => miso_i,
spi_clk_o => sclk_o,
spi_cs_n_o => ss_n_o
spi_cs_n_o => ss_n_o
);
p_delays : process (wb_clk)
......@@ -161,7 +161,7 @@ begin
--! @brief Combinational process that sets a SPI operation thanks
--! to SPI0 and SPI1.
--! @param s_MEM_fsm Current state of the m25p32 SPI handler
--! s_MEM_fsm_d0 One clock delay of s_MEM_fsm
--! s_MEM_fsm_d0 One clock delay of s_MEM_fsm
p_comb_SPIx : process (s_MEM_fsm, s_MEM_fsm_d0)
procedure setup_SPI0 (operation : t_operations) is
......@@ -342,21 +342,21 @@ begin
when R0_RESET =>
s_MEM_fsm <= S0_IDLE;
when S0_IDLE =>
if s_FMI.OPR = '1' then
if s_FMI.OPR = '1' then
s_MEM_fsm <= S1B_WREN;
end if;
when S1B_WREN =>
when S1B_WREN =>
s_MEM_fsm <= S1_WREN;
when S1_WREN =>
if s_SPI2.SENT_OP = '1' then
s_MEM_fsm <= S2B_SPI_INST;
end if;
when S2B_SPI_INST =>
when S2B_SPI_INST =>
s_MEM_fsm <= S2_SPI_INST;
--! We add this assignment here for being less verbose
--! Easiest way to add concurrency while performing an SPI
--! operation.
when S2_SPI_INST =>
when S2_SPI_INST =>
if s_SPI2.SENT_OP = '1' then
s_MEM_fsm <= S3B_WRDI;
end if;
......
hdl/m25p32/rtl/m25p32_pkg.vhd
View file @ a9e62b25
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
......@@ -15,13 +15,13 @@
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 12:00:00 15-06-2012
--
-- Create Date: 12:00:00 15-06-2012
-- Design Name:
-- Module Name: m25p32_pkg
-- Project Name: Level Conversion Circuits
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description: This package holds the definition of the register used along
......@@ -29,12 +29,12 @@
-- following modules:
-- - m25p32_core.vhd
-- - m25p32_regs.vhd
-- Dependencies: spi_master_pkg.vhd (SPI master multifield)
-- Dependencies: spi_master_pkg.vhd (SPI master multifield)
--
-- Revision: 0.1
-- 0.01 + File Created
--
-- Additional Comments: enjoy it! ;)
--
-- Additional Comments: enjoy it! ;)
--
----------------------------------------------------------------------------------
......@@ -51,7 +51,7 @@ package m25p32_pkg is
type r_SPI_CFG is
record
CPOL : STD_LOGIC;
CPOL : STD_LOGIC;
CPHA : STD_LOGIC;
CLK_DIV : UNSIGNED(15 downto 12);-- Taken from spi
end record;
......@@ -60,7 +60,7 @@ package m25p32_pkg is
--! - {CPOL = '0', CPHA = '0'}
--! - {CPOL = '1', CPHA = '1'}
constant c_SPI_CFG : r_SPI_CFG := (CPOL => '0',
constant c_SPI_CFG : r_SPI_CFG := (CPOL => '0',
CPHA => '0',
CLK_DIV => to_unsigned(4, 4));
......@@ -84,7 +84,7 @@ package m25p32_pkg is
constant c_ADDR_HEADER_PAD_SIZE : NATURAL := c_M25P32_ADDR_SIZE*8
- c_SECTOR_BITS
- c_PAGES_PER_SECTOR_BITS
- c_BYTES_PER_PAGE_BITS;
- c_BYTES_PER_PAGE_BITS;
constant c_ADDR_HEADER_PAD : STD_LOGIC_VECTOR(c_ADDR_HEADER_PAD_SIZE - 1
downto 0) := (others => '0');
constant c_ADDR_FOOTER_PAD : STD_LOGIC_VECTOR(c_BYTES_PER_PAGE_BITS - 1
......@@ -98,16 +98,16 @@ package m25p32_pkg is
-- WBits
----------------------------------------
-- [POSITION] [CONTENT]
-- 0[WBits-2]00 FMI
-- 0[WBits-2]00 FMI
-- 0[WBits-2]01 SR
-- 0[WBits-2]10 READ_DATA
-- 1[WBits-2]00 WR_DATA
-- ... ...
-- ... ...
-- 1[WBits-2]11 WR_DATA
----------------------------------------
constant c_FMI_addr :STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0) :=
'0' & c_WB_ADDR_PADDING & "00";
'0' & c_WB_ADDR_PADDING & "00";
constant c_SR_m25p32_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0) :=
'0' & c_WB_ADDR_PADDING & "01";
......@@ -124,7 +124,7 @@ package m25p32_pkg is
----------------------------------------
-- Operation Status Register
----------------------------------------
-- BIT NAME DESCRIPTION
-- BIT NAME DESCRIPTION
-- 0 OPA OPeration Attended
-- 1 OPF Operation Finished
--
......@@ -143,18 +143,18 @@ package m25p32_pkg is
-- 16 bits
-- Wishbone access: Write-read
----------------------------------------
-- BIT NAME DESCRIPTION
-- BIT NAME DESCRIPTION
-- 0 OPR OPeration Requested
-- 2-1 x Reserved (It will be appended here OP)
-- 5-3 OP OPeration
-- 13-6 PG PaGe number
-- 19-14 SCT SeCTor number
-- 23-20 y Reserved
-- 2-1 x Reserved (It will be appended here OP)
-- 5-3 OP OPeration
-- 13-6 PG PaGe number
-- 19-14 SCT SeCTor number
-- 23-20 y Reserved
----------------------------------------
-- List of operations:
-- 0b000 x Reserved
-- 0b001 RDID ReaD IDentification
-- 0b010 RDSR ReaD Status Register
-- 0b010 RDSR ReaD Status Register
-- 0b011 WRSR WRite Status Register
-- 0b100 READ ReaD Page
-- 0b101 PP Page Program
......@@ -162,7 +162,7 @@ package m25p32_pkg is
-- 0b111 BE Block Erase
----------------------------------------
type t_operations is (x, RDID, RDSR, WRSR,
READ, PP, SE, BE);
READ, PP, SE, BE);
type r_FMI is
record
......@@ -187,9 +187,9 @@ package m25p32_pkg is
-- Wishbone access: Write-read
----------------------------------------
-- BIT NAME DESCRIPTION
-- 0 WIP Write In Progress
-- 0 WIP Write In Progress
-- 1 WEL Write Enable Latch
-- 2 BP0 Block Protect bit 0
-- 2 BP0 Block Protect bit 0
-- 3 BP1 Block Protect bit 1
-- 4 BP2 Block Protect bit 2
-- 6-5 x Reserved
......@@ -203,7 +203,7 @@ package m25p32_pkg is
BP1 : STD_LOGIC;
BP2 : STD_LOGIC;
x : STD_LOGIC_VECTOR(6 downto 5);
SRWD : STD_LOGIC;
SRWD : STD_LOGIC;
end record;
attribute a_length of r_SR_m25p32 : type is 8;
......@@ -231,12 +231,12 @@ package m25p32_pkg is
y => (others => '0'));
--! Default: SR_m25p32 no protection in the memory by default
constant c_SR_m25p32_default : r_SR_m25p32 := (WIP => '0',
WEL => '0',
BP0 => '0',
BP1 => '0',
BP2 => '0',
x => (others => '0'),
constant c_SR_m25p32_default : r_SR_m25p32 := (WIP => '0',
WEL => '0',
BP0 => '0',
BP1 => '0',
BP2 => '0',
x => (others => '0'),
SRWD => '0');
------------------------------------------------------------------------------
......@@ -443,7 +443,7 @@ package m25p32_pkg is
CPHA => c_SPI_CFG.CPHA,
BREAD => (others => '0'),
BDATA => (others => '0'),
BADDR => to_unsigned( 3 , 9),
BADDR => to_unsigned( 3 , 9),
BINST => to_unsigned( 1 , 9));
constant c_SPI1_SE : r_SPI1 := (PUSH_DATA => '0', PUSH_ADDR => '1',
......@@ -462,7 +462,7 @@ package m25p32_pkg is
CPHA => c_SPI_CFG.CPHA,
BREAD => (others => '0'),
BDATA => (others => '0'),
BADDR => (others => '0'),
BADDR => (others => '0'),
BINST => to_unsigned( 1 , 9));
constant c_SPI1_BE : r_SPI1 := (PUSH_DATA => '0', PUSH_ADDR => '0',
......@@ -531,7 +531,7 @@ package m25p32_pkg is
return r_word;
function f_page (signal page : in STD_LOGIC_VECTOR(c_PAGE_SIZE*8 -1 downto 0))
return r_page;
function f_spi_instruction
function f_spi_instruction
(signal spi_inst_slv : STD_LOGIC_VECTOR(7 downto 0))
return t_spi_instruction;
......@@ -550,17 +550,17 @@ package body m25p32_pkg is
case operation is
when RDID =>
v_return := STD_LOGIC_VECTOR(to_unsigned(1, 3));
when RDSR =>
when RDSR =>
v_return := STD_LOGIC_VECTOR(to_unsigned(2, 3));
when WRSR =>
when WRSR =>
v_return := STD_LOGIC_VECTOR(to_unsigned(3, 3));
when READ =>
when READ =>
v_return := STD_LOGIC_VECTOR(to_unsigned(4, 3));
when PP =>
when PP =>
v_return := STD_LOGIC_VECTOR(to_unsigned(5, 3));
when SE =>
when SE =>
v_return := STD_LOGIC_VECTOR(to_unsigned(6, 3));
when BE =>
when BE =>
v_return := STD_LOGIC_VECTOR(to_unsigned(7, 3));
when others =>
v_return := STD_LOGIC_VECTOR(to_unsigned(0, 3));
......@@ -602,8 +602,8 @@ package body m25p32_pkg is
function f_STD_LOGIC_VECTOR (r_register : r_OP) return STD_LOGIC_VECTOR is
begin
return r_register.OPF
& r_register.OPA;
return r_register.OPF
& r_register.OPA;
end f_STD_LOGIC_VECTOR;
function f_OP(r_register : STD_LOGIC_VECTOR(1 downto 0)) return r_OP is
......@@ -619,7 +619,7 @@ package body m25p32_pkg is
--! @brief Procedure for translating r_FMI GROUP A write bits into a signal
--! @param r_register r_FMI record type to be translated, bounded to group A
--! write bits.
--! @param s_out_A Singal in which to be updated the r_FMI bits
--! @param s_out_A Singal in which to be updated the r_FMI bits
-----------------------------------------------------------------------------
function f_STD_LOGIC_VECTOR (r_register : r_FMI) return STD_LOGIC_VECTOR is
variable v_OP_slv : STD_LOGIC_VECTOR(2 downto 0);
......@@ -627,7 +627,7 @@ package body m25p32_pkg is
v_OP_slv := f_STD_LOGIC_VECTOR(r_register.OP);
return r_register.y
& STD_LOGIC_VECTOR(r_register.SCT)
& STD_LOGIC_VECTOR(r_register.PG)
& STD_LOGIC_VECTOR(r_register.PG)
& v_OP_slv
& r_register.x
& r_register.OPR;
......@@ -643,9 +643,9 @@ package body m25p32_pkg is
begin
v_FMI.OPR := r_register(0);
v_FMI.x := r_register(r_OP'a_length - 1 + 1 downto 1);
v_FMI.OP := f_operations(r_register(5 downto 3));
v_FMI.OP := f_operations(r_register(5 downto 3));
v_FMI.PG := UNSIGNED(r_register(c_PAGES_PER_SECTOR_BITS - 1 + 6 downto
6));
6));
v_FMI.SCT := UNSIGNED(r_register(c_SECTOR_BITS + c_PAGES_PER_SECTOR_BITS
- 1 + 6 downto
c_PAGES_PER_SECTOR_BITS + 6));
......@@ -661,8 +661,8 @@ package body m25p32_pkg is
function f_STD_LOGIC_VECTOR (r_register : r_SR_m25p32)
return STD_LOGIC_VECTOR is
begin
return ( r_register.SRWD & std_logic_vector(r_register.x) &
r_register.BP2 & r_register.BP1 &
return ( r_register.SRWD & std_logic_vector(r_register.x) &
r_register.BP2 & r_register.BP1 &
r_register.BP0 & r_register.WEL &
r_register.WIP );
end f_STD_LOGIC_VECTOR;
......@@ -743,21 +743,21 @@ package body m25p32_pkg is
case spi_inst_slv is
when c_WREN_inst =>
v_return := WREN;
when c_WRDI_inst =>
when c_WRDI_inst =>
v_return := WRDI;
when c_RDID_inst =>
when c_RDID_inst =>
v_return := RDID;
when c_RDSR_inst =>
when c_RDSR_inst =>
v_return := RDSR;
when c_WRSR_inst =>
when c_WRSR_inst =>
v_return := WRSR;
when c_READ_inst =>
when c_READ_inst =>
v_return := READ;
when c_PP_inst =>
when c_PP_inst =>
v_return := PP;
when c_SE_inst =>
when c_SE_inst =>
v_return := SE;
when c_BE_inst =>
when c_BE_inst =>
v_return := BE;
when others =>
v_return := NULL_INST;
......
hdl/m25p32/rtl/m25p32_regs.vhd
View file @ a9e62b25
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
......@@ -15,23 +15,23 @@
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 23:55:10 06/10/2012
--
-- Create Date: 23:55:10 06/10/2012
-- Design Name: m25p32 wishbone access
-- Module Name: m25p32_regs - Behavioral
-- Module Name: m25p32_regs - Behavioral
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Tool versions:
-- Description: This is a wishbone slave able to access m25p32 Non volatile
-- Flash devices and manage the write and read to the memory.
--
-- Dependencies:
-- Dependencies:
--
-- Revision:
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
......@@ -44,22 +44,22 @@ use work.spi_master_pkg.ALL;
entity m25p32_regs is
generic(
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH;
g_READ_LENGTH : NATURAL := c_READ_LENGTH;
g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
......@@ -115,9 +115,9 @@ begin
s_SR_m25p32 <= c_SR_m25p32_default;
wb_data_o <= (others => '0');
s_wb_ack_o <= '0';
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
s_wb_ack_o <= '0';
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
s_rd_data <= (others => '0');
else
--! We never retry
......@@ -129,8 +129,8 @@ begin
if (wb_stb_i = '1' and wb_cyc_i = '1') then
if (s_wb_ack_o or s_wb_rty_o or s_wb_err_o) = '1' then
s_wb_ack_o <= '0';
s_wb_err_o <= '0';
s_wb_ack_o <= '0';
s_wb_err_o <= '0';
else
s_wb_ack_o <= '1';
s_wb_err_o <= '0';
......@@ -141,7 +141,7 @@ begin
--! FMI address
when "00" =>
if s_OP.OPA = '0' then
s_FMI <= f_FMI(wb_data_i(23 downto 0));
s_FMI <= f_FMI(wb_data_i(23 downto 0));
else
s_wb_ack_o <= '0';
s_wb_err_o <= '1';
......@@ -150,7 +150,7 @@ begin
when "01" =>
s_SR_m25p32 <= f_SR_m25p32(wb_data_i(
r_SR_m25p32'a_length-1 downto 0));
--! READ_DATA address
--! READ_DATA address
when others =>
s_wb_ack_o <= '0';
s_wb_err_o <= '1';
......@@ -177,7 +177,7 @@ begin
<= f_STD_LOGIC_VECTOR(s_SR_m25p32);
wb_data_o(31 downto r_SR_m25p32'a_length)
<= (others => '0');
when "10" =>
when "10" =>
wb_data_o <= s_rd_data;
when others =>
s_wb_ack_o <= '0';
......@@ -193,7 +193,7 @@ begin
end if;
end if;
if s_OP.OPF = '1' then
if s_OP.OPF = '1' then
s_FMI.OPR <= '0';
end if;
......
hdl/m25p32/rtl/m25p32_top.vhd
View file @ a9e62b25
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
......@@ -15,22 +15,22 @@
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 01:22:27 06/11/2012
--
-- Create Date: 01:22:27 06/11/2012
-- Design Name: m25p32 top level
-- Module Name: m25p32_top - Behavioral
-- Module Name: m25p32_top - Behavioral
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Description:
-- Tool versions:
-- Description:
--
-- Dependencies:
-- Dependencies:
--
-- Revision:
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
......@@ -43,7 +43,7 @@ use work.spi_master_pkg.ALL;
entity m25p32_top is
generic(
g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
port (
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
......@@ -51,11 +51,11 @@ entity m25p32_top is
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
miso_word_rcv : out STD_LOGIC;
......@@ -107,8 +107,8 @@ architecture Behavioral of m25p32_top is
component m25p32_regs is
generic(
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH;
g_READ_LENGTH : NATURAL := c_READ_LENGTH;
g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
......@@ -145,17 +145,17 @@ begin
inst_m25p32_core: m25p32_core
port map (
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
mosi_o => prom_mosi_o,
miso_i => prom_din_i,
sclk_o => prom_cclk_o,
mosi_o => prom_mosi_o,
miso_i => prom_din_i,
sclk_o => prom_cclk_o,
ss_n_o => prom_cs0_b_n_o,
wr_data_i => s_wr_data,
rd_data_o => s_rd_data,
SR_m25p32_i => s_SR_m25p32,
wr_data_i => s_wr_data,
rd_data_o => s_rd_data,
SR_m25p32_i => s_SR_m25p32,
rd_SPI3_o => s_rd_SPI3,
......@@ -165,13 +165,13 @@ begin
inst_m25p32_regs: m25p32_regs
port map (
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
......@@ -181,9 +181,9 @@ begin
rd_SPI3_i => s_rd_SPI3,
wr_data_o => s_wr_data,
rd_data_i => s_rd_data,
SR_m25p32_o => s_SR_m25p32,
wr_data_o => s_wr_data,
rd_data_i => s_rd_data,
SR_m25p32_o => s_SR_m25p32,
OP_i => s_OP,
FMI_o => s_FMI
......
hdl/m25p32/test/m25p32_top_tb.vhd
View file @ a9e62b25
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO
-- Company: CERN, BE-CO
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 01:22:27 07/26/2012
--
-- Create Date: 01:22:27 07/26/2012
-- Design Name: m25p32 top_tp level
-- Module Name: m25p32_top_tp - RTL
-- Module Name: m25p32_top_tp - RTL
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Description:
-- Tool versions:
-- Description:
--
-- Dependencies:
-- Dependencies:
--
-- Revision:
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
......@@ -35,7 +35,7 @@ use std.textio.ALL;
entity m25p32_top_tb is
end m25p32_top_tb;
architecture Behavioral of m25p32_top_tb is
architecture Behavioral of m25p32_top_tb is
file s_file_handler : TEXT;
constant c_log_path : STRING := "../test/log/m25p32_top_tb.log";
......@@ -57,12 +57,12 @@ architecture Behavioral of m25p32_top_tb is
signal s_wb_stb : STD_LOGIC;
signal s_wb_cyc : STD_LOGIC;
signal s_wb_sel : STD_LOGIC_VECTOR (3 downto 0);
signal s_wb_data_i : STD_LOGIC_VECTOR (31 downto 0);
signal s_wb_data_o : STD_LOGIC_VECTOR (31 downto 0);
signal s_wb_data_i : STD_LOGIC_VECTOR (31 downto 0);
signal s_wb_data_o : STD_LOGIC_VECTOR (31 downto 0);
signal s_wb_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS downto 0);
signal s_wb_ack : STD_LOGIC;
signal s_wb_rty : STD_LOGIC;
signal s_wb_ack : STD_LOGIC;
signal s_wb_rty : STD_LOGIC;
signal s_wb_err : STD_LOGIC;
signal s_spi_mosi : STD_LOGIC;
......@@ -76,11 +76,11 @@ architecture Behavioral of m25p32_top_tb is
--! Signals for the spi_analyser
signal s_SPI0 : r_SPI0;
signal s_SPI0 : r_SPI0;
signal s_SPI0_slv : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI1 : r_SPI1;
signal s_SPI1 : r_SPI1;
signal s_SPI1_slv : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI2 : r_SPI2;
signal s_SPI2 : r_SPI2;
signal s_SPI2_slv : STD_LOGIC_VECTOR (15 downto 0);
signal s_SPI3 : r_SPI3;
signal s_SPI3_slv : STD_LOGIC_VECTOR (31 downto 0);
......@@ -97,8 +97,8 @@ architecture Behavioral of m25p32_top_tb is
signal s_read_check : STD_LOGIC_VECTOR(c_READ_LENGTH*8 - 1 downto 0)
:= (others => '0');
signal s_end_inst_flag : STD_LOGIC;
signal s_end_addr_flag : STD_LOGIC;
signal s_end_inst_flag : STD_LOGIC;
signal s_end_addr_flag : STD_LOGIC;
signal s_end_data_flag : STD_LOGIC;
--! Signals for the spi_slave_writer
......@@ -112,7 +112,7 @@ architecture Behavioral of m25p32_top_tb is
signal s_page : r_page;
signal s_op_finished : STD_LOGIC;
signal s_spi_addr : STD_LOGIC_VECTOR(c_M25P32_ADDR_SIZE*8 - 1
downto 0);
signal test_id : NATURAL := 0;
......@@ -140,29 +140,29 @@ begin
"s_STATUS", 1);
wait;
end process p_sig_spy;
--! Connections for the m25p32
--! Connections for the m25p32
uut: m25p32_top port map(
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => s_wb_we,
wb_stb_i => s_wb_stb,
wb_cyc_i => s_wb_cyc,
wb_sel_i => s_wb_sel,
wb_data_i => s_wb_data_i,
wb_data_o => s_wb_data_o,
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => s_wb_we,
wb_stb_i => s_wb_stb,
wb_cyc_i => s_wb_cyc,
wb_sel_i => s_wb_sel,
wb_data_i => s_wb_data_i,
wb_data_o => s_wb_data_o,
wb_addr_i => s_wb_addr,
wb_ack_o => s_wb_ack,
wb_rty_o => s_wb_rty,
wb_err_o => s_wb_err,
wb_ack_o => s_wb_ack,
wb_rty_o => s_wb_rty,
wb_err_o => s_wb_err,
miso_word_rcv => s_miso_word_rcv,
op_finished_o => s_op_finished,
op_finished_o => s_op_finished,
prom_mosi_o => s_spi_mosi,
prom_cclk_o => s_spi_clk,
prom_mosi_o => s_spi_mosi,
prom_cclk_o => s_spi_clk,
prom_cs0_b_n_o => s_spi_cs_n,
prom_din_i => s_spi_miso);
......@@ -174,21 +174,21 @@ begin
mosi_tester : spi_analyser port map(
rst_i => s_rst_spi_analyser,
SPI0_i => s_SPI0,
SPI1_i => s_SPI1,
spi_mosi_o => s_spi_mosi,
spi_miso_i => s_spi_miso,
spi_clk_o => s_spi_clk,
spi_cs_n_o => s_spi_cs_n,
inst_check_o => s_inst_check_slv,
addr_check_o => s_addr_check,
rst_i => s_rst_spi_analyser,
SPI0_i => s_SPI0,
SPI1_i => s_SPI1,
spi_mosi_o => s_spi_mosi,
spi_miso_i => s_spi_miso,
spi_clk_o => s_spi_clk,
spi_cs_n_o => s_spi_cs_n,
inst_check_o => s_inst_check_slv,
addr_check_o => s_addr_check,
data_check_o => s_data_check,
end_inst_flag_o => s_end_inst_flag,
end_addr_flag_o => s_end_addr_flag,
end_inst_flag_o => s_end_inst_flag,
end_addr_flag_o => s_end_addr_flag,
end_data_flag_o => s_end_data_flag);
......@@ -199,17 +199,17 @@ begin
or s_SPI2.SENT_OP;
miso_tester : spi_slave_writer port map(
rst_i => s_rst_spi_slave_writer,
SPI0_i => s_SPI0,
SPI1_i => s_SPI1,
STATUS_i => s_STATUS,
rst_i => s_rst_spi_slave_writer,
SPI0_i => s_SPI0,
SPI1_i => s_SPI1,
STATUS_i => s_STATUS,
bytes_to_wr_i => s_bytes_to_wr,
read_i => s_read,
bytes_to_wr_i => s_bytes_to_wr,
read_i => s_read,
end_read_flag_o => s_end_read_flag,
end_read_flag_o => s_end_read_flag,
spi_miso_o => s_spi_miso,
spi_miso_o => s_spi_miso,
spi_clk_i => s_spi_clk);
--! @brief Process that generates the wb_clk
......@@ -236,22 +236,22 @@ begin
begin
--! We reset the wishbone bus
wait until rising_edge(wb_clk);
s_wb_we <= '0';
s_wb_stb <= '0';
s_wb_cyc <= '0';
s_wb_sel <= (others => '0');
s_wb_data_i <= (others => '0');
s_wb_addr <= (others => '0');
s_wb_we <= '0';
s_wb_stb <= '0';
s_wb_cyc <= '0';
s_wb_sel <= (others => '0');
s_wb_data_i <= (others => '0');
s_wb_addr <= (others => '0');
end procedure;
procedure wishbone_write_SR (reg_data : r_SR_m25p32) is
variable v_reg_data : STD_LOGIC_VECTOR(31 downto 0);
variable v_reg_data : STD_LOGIC_VECTOR(31 downto 0);
begin
v_reg_data( 7 downto 0) := f_STD_LOGIC_VECTOR(reg_data);
v_reg_data(31 downto 8) := (others => '0');
wishbone_write(wb_clk, s_wb_we,
s_wb_stb, s_wb_cyc, s_wb_sel,
s_wb_data_i, s_wb_addr,
s_wb_data_i, s_wb_addr,
v_reg_data, c_SR_m25p32_addr);
end procedure;
......@@ -261,11 +261,11 @@ begin
variable v_word: STD_LOGIC_VECTOR(31 downto 0);
variable v_pos : UNSIGNED (c_WORDS_PER_PAGE_BITS downto 0);
begin
v_word := f_STD_LOGIC_VECTOR(word);
v_pos := '1' & to_unsigned(pos,c_WORDS_PER_PAGE_BITS);
v_word := f_STD_LOGIC_VECTOR(word);
v_pos := '1' & to_unsigned(pos,c_WORDS_PER_PAGE_BITS);
wishbone_write(wb_clk, s_wb_we,
s_wb_stb, s_wb_cyc, s_wb_sel,
s_wb_data_i, s_wb_addr,
s_wb_data_i, s_wb_addr,
v_word, STD_LOGIC_VECTOR(v_pos));
end procedure;
......@@ -275,7 +275,7 @@ begin
begin
wishbone_read (wb_clk, s_wb_we,
s_wb_stb, s_wb_cyc, s_wb_sel,
s_wb_data_o, s_wb_addr, read_data,
s_wb_data_o, s_wb_addr, read_data,
c_SR_m25p32_addr);
end procedure;
......@@ -285,7 +285,7 @@ begin
begin
wishbone_read (wb_clk, s_wb_we,
s_wb_stb, s_wb_cyc, s_wb_sel,
s_wb_data_o, s_wb_addr, read_data,
s_wb_data_o, s_wb_addr, read_data,
c_DATA_READ_addr);
end procedure;
......@@ -295,11 +295,11 @@ begin
page : NATURAL) is
variable v_FMI : r_FMI;
begin
v_FMI.OPR := '1';
v_FMI.x := (others => '0');
v_FMI.OP := operation;
v_FMI.PG := to_unsigned(page, c_PAGES_PER_SECTOR_BITS);
v_FMI.SCT := to_unsigned(sector, c_SECTOR_BITS);
v_FMI.OPR := '1';
v_FMI.x := (others => '0');
v_FMI.OP := operation;
v_FMI.PG := to_unsigned(page, c_PAGES_PER_SECTOR_BITS);
v_FMI.SCT := to_unsigned(sector, c_SECTOR_BITS);
v_FMI.y := (others => '0');
s_spi_addr <= c_ADDR_HEADER_PAD
& STD_LOGIC_VECTOR(v_FMI.SCT)
......@@ -307,7 +307,7 @@ begin
& c_ADDR_FOOTER_PAD;
wishbone_write(wb_clk, s_wb_we,
s_wb_stb, s_wb_cyc, s_wb_sel,
s_wb_data_i, s_wb_addr,
s_wb_data_i, s_wb_addr,
X"00" & f_STD_LOGIC_VECTOR(v_FMI), c_FMI_addr);
end procedure;
......@@ -342,60 +342,60 @@ begin
v_operation(4 downto 1) := "RDID";
if s_inst_check_slv /= c_RDID_inst then
v_fail := true;
v_msg(42 downto 1) := "Bad instruction code for RDID instruction.";
v_msg(42 downto 1) := "Bad instruction code for RDID instruction.";
else
v_check := " OK";
v_msg(47 downto 1) := "RDID instruction received matches with expected";
v_msg(47 downto 1) := "RDID instruction received matches with expected";
end if;
when RDSR =>
v_operation(4 downto 1) := "RDSR";
if s_inst_check_slv /= c_RDSR_inst then
v_fail := true;
v_msg(42 downto 1) := "Bad instruction code for RDSR instruction.";
v_msg(42 downto 1) := "Bad instruction code for RDSR instruction.";
else
v_check := " OK";
v_msg(47 downto 1) := "RDSR instruction received matches with expected";
v_msg(47 downto 1) := "RDSR instruction received matches with expected";
end if;
when WRSR =>
v_operation(4 downto 1) := "WRSR";
if s_inst_check_slv /= c_WRSR_inst then
v_msg(42 downto 1) := "Bad instruction code for WRSR instruction.";
v_msg(42 downto 1) := "Bad instruction code for WRSR instruction.";
else
v_check := " OK";
v_msg(47 downto 1) := "WRSR instruction received matches with expected";
v_msg(47 downto 1) := "WRSR instruction received matches with expected";
end if;
when READ =>
v_operation(4 downto 1) := "READ";
if s_inst_check_slv /= c_READ_inst then
v_msg(42 downto 1) := "Bad instruction code for READ instruction.";
v_msg(42 downto 1) := "Bad instruction code for READ instruction.";
else
v_check := " OK";
v_msg(47 downto 1) := "READ instruction received matches with expected";
v_msg(47 downto 1) := "READ instruction received matches with expected";
end if;
when PP =>
v_operation(2 downto 1) := "PP";
if s_inst_check_slv /= c_PP_inst then
v_msg(40 downto 1) := "Bad instruction code for PP instruction.";
v_msg(40 downto 1) := "Bad instruction code for PP instruction.";
else
v_check := " OK";
v_msg(45 downto 1) := "PP instruction received matches with expected";
v_msg(45 downto 1) := "PP instruction received matches with expected";
end if;
when SE =>
v_operation(2 downto 1) := "SE";
if s_inst_check_slv /= c_SE_inst then
v_msg(40 downto 1) := "Bad instruction code for SE instruction.";
v_msg(40 downto 1) := "Bad instruction code for SE instruction.";
else
v_check := " OK";
v_msg(45 downto 1) := "SE instruction received matches with expected";
v_msg(45 downto 1) := "SE instruction received matches with expected";
end if;
when BE =>
v_operation(2 downto 1) := "BE";
if s_inst_check_slv /= c_BE_inst then
v_msg(40 downto 1) := "Bad instruction code for BE instruction.";
v_msg(40 downto 1) := "Bad instruction code for BE instruction.";
else
v_check := " OK";
v_msg(45 downto 1) := "BE instruction received matches with expected";
v_msg(45 downto 1) := "BE instruction received matches with expected";
end if;
when others =>
null;
......@@ -515,7 +515,7 @@ begin
& v_operation & sep
& v_field & sep
& v_msg));
writeline(s_file_handler, v_line_buffer);
writeline(s_file_handler, v_line_buffer);
end if;
if v_ocurreance = false then
v_fail := false;
......@@ -623,10 +623,10 @@ begin
variable v_operation : STRING ( 4 downto 1);
variable v_msg : STRING ( 9 downto 1);
begin
v_field := "[Stat]";
v_check := "[Check]";
v_operation := "[OP]";
v_msg := "[Message]";
v_field := "[Stat]";
v_check := "[Check]";
v_operation := "[OP]";
v_msg := "[Message]";
write(v_line_buffer,string'( "[Test]" & sep
& v_check & sep
& v_operation & sep
......@@ -722,20 +722,20 @@ begin
-------------------------------------------------------------------------------
--! Test Target
--! 0 WRSR
--! 1 PP
--! 2 SE
--! 3 BE
--! 4 RDSR
--! 5 RDID
--! 6 READ
--! 1 PP
--! 2 SE
--! 3 BE
--! 4 RDSR
--! 5 RDID
--! 6 READ
-------------------------------------------------------------------------------
s_SR_m25p32 <= (WIP => '0',
s_SR_m25p32 <= (WIP => '0',
WEL => '0',
BP0 => '1',
BP1 => '1',
BP2 => '1',
x => (others => '0'),
BP0 => '1',
BP1 => '1',
BP2 => '1',
x => (others => '0'),
SRWD => '0');
wait until rising_edge(wb_clk);
......
hdl/m25p32/test/m25p32_top_tb_pkg.vhd
View file @ a9e62b25
--------------------------------------------------------------------------------
-- Company:
-- Company:
-- Engineer:
--
-- Create Date: 12:31:47 06/20/2012
-- Design Name:
-- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name: spi_master_multifield
-- Target Device:
-- Tool versions:
-- Description:
--
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: spi_master_core
--
--
-- Dependencies:
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
......@@ -36,34 +36,31 @@ use work.m25p32_pkg.ALL;
package m25p32_top_tb_pkg is
--! Constant only used in simulation
constant c_WISHBONE_PERIOD : TIME := 50 ns; --! Working at 20MHz
constant c_WISHBONE_PERIOD : TIME := 50 ns; --! Working at 20MHz
component m25p32_top is
generic(
g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
miso_word_rcv : out STD_LOGIC;
op_finished_o : out STD_LOGIC;
prom_mosi_o : out STD_LOGIC;
prom_cclk_o : out STD_LOGIC;
prom_cs0_b_n_o : out STD_LOGIC;
prom_din_i : in STD_LOGIC
);
generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
port (wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
miso_word_rcv : out STD_LOGIC;
op_finished_o : out STD_LOGIC;
prom_mosi_o : out STD_LOGIC;
prom_cclk_o : out STD_LOGIC;
prom_cs0_b_n_o : out STD_LOGIC;
prom_din_i : in STD_LOGIC);
end component;
procedure wishbone_write (
......@@ -73,10 +70,10 @@ package m25p32_top_tb_pkg is
signal wb_cyc : out STD_LOGIC;
signal wb_sel : out STD_LOGIC_VECTOR (3 downto 0);
signal wb_data : out STD_LOGIC_VECTOR (31 downto 0);
signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0);
reg_data : STD_LOGIC_VECTOR (31 downto 0);
reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0));
procedure wishbone_read (
......@@ -86,10 +83,10 @@ package m25p32_top_tb_pkg is
signal wb_cyc : out STD_LOGIC;
signal wb_sel : out STD_LOGIC_VECTOR (3 downto 0);
signal wb_data : in STD_LOGIC_VECTOR (31 downto 0);
signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0);
signal read_data : out STD_LOGIC_VECTOR (31 downto 0);
reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0));
function fill_page return r_page;
......@@ -101,7 +98,7 @@ package body m25p32_top_tb_pkg is
--! @brief Procedure to place wishbone writes at a given address.
--! @param wb_clk Wishbone clock signal
--! wb_we Write enable signal
--! wb_we Write enable signal
--! wb_stb Strobe signal
--! wb_cyc Cycle signal
--! wb_sel Addres select signal
......@@ -116,31 +113,31 @@ package body m25p32_top_tb_pkg is
signal wb_cyc : out STD_LOGIC;
signal wb_sel : out STD_LOGIC_VECTOR (3 downto 0);
signal wb_data : out STD_LOGIC_VECTOR (31 downto 0);
signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0);
reg_data : STD_LOGIC_VECTOR (31 downto 0);
reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0)) is
begin
wait until rising_edge(wb_clk);
wb_we <= '1';
wb_stb <= '1';
wb_cyc <= '1';
wb_sel <= X"F";
wb_data <= reg_data;
wb_we <= '1';
wb_stb <= '1';
wb_cyc <= '1';
wb_sel <= X"F";
wb_data <= reg_data;
wb_addr <= reg_addr;
wait until rising_edge(wb_clk);
--! Here we wait for the ack and keep till operation is finished
wait until rising_edge(wb_clk);
wb_we <= '0';
wb_stb <= '0';
wb_cyc <= '0';
wb_sel <= X"F";
wb_we <= '0';
wb_stb <= '0';
wb_cyc <= '0';
wb_sel <= X"F";
end procedure;
--! @brief Procedure to place wishbone reads at a given address.
--! @param wb_clk Wishbone clock signal
--! wb_we Write enable signal
--! wb_we Write enable signal
--! wb_stb Strobe signal
--! wb_cyc Cycle signal
--! wb_sel Addres select signal
......@@ -155,34 +152,34 @@ package body m25p32_top_tb_pkg is
signal wb_cyc : out STD_LOGIC;
signal wb_sel : out STD_LOGIC_VECTOR (3 downto 0);
signal wb_data : in STD_LOGIC_VECTOR (31 downto 0);
signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0);
signal read_data : out STD_LOGIC_VECTOR (31 downto 0);
reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0)) is
begin
wait until rising_edge(wb_clk);
wb_we <= '0';
wb_stb <= '1';
wb_cyc <= '1';
wb_sel <= X"F";
wb_we <= '0';
wb_stb <= '1';
wb_cyc <= '1';
wb_sel <= X"F";
wb_addr <= reg_addr;
wait until rising_edge(wb_clk);
wait until wb_data'event;
--! Here we wait for the ack and keep till operation is finished
read_data <= wb_data;
read_data <= wb_data;
wait until rising_edge(wb_clk);
wb_stb <= '0';
wb_cyc <= '0';
wb_sel <= X"F";
wb_stb <= '0';
wb_cyc <= '0';
wb_sel <= X"F";
end procedure;
--! @brief Funtion to fill a page with predefined words.
function fill_page return r_page is
variable v_var0 : r_word := (word_slv => X"DEADBEEF");
variable v_var1 : r_word := (word_slv => X"8BADF00D");
variable v_var2 : r_word := (word_slv => X"C001F007");
variable v_var0 : r_word := (word_slv => X"DEADBEEF");
variable v_var1 : r_word := (word_slv => X"8BADF00D");
variable v_var2 : r_word := (word_slv => X"C001F007");
variable v_var3 : r_word := (word_slv => X"B16B00B5");
variable v_return : r_page;
begin
......
hdl/multiboot/test/multiboot_core_tb.vhd
View file @ a9e62b25
-- TestBench Template
-- TestBench Template
library IEEE;
library work;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use STD.TEXTIO.ALL;
use work.multiboot_pkg.ALL;
ENTITY multiboot_core_tb IS
END multiboot_core_tb;
entity multiboot_core_tb is
end multiboot_core_tb;
ARCHITECTURE behavior OF multiboot_core_tb IS
architecture behavior of multiboot_core_tb is
component multiboot_core
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
CTRL0_i : in STD_LOGIC_VECTOR (15 downto 0);
CTRL1_o : out STD_LOGIC_VECTOR (15 downto 0);
STAT_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL1_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL2_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL3_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL4_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL1_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL2_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL3_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL4_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
constant c_CLK_PERIOD : TIME := 50 ns;
signal rst : STD_LOGIC;
signal clk : STD_LOGIC;
signal CTRL0_i : STD_LOGIC_VECTOR (15 downto 0);
signal CTRL1_o : STD_LOGIC_VECTOR (15 downto 0);
signal STAT_ICAP_o : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL1_i : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL2_i : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL3_i : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL4_i : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL1_ICAP_o : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL2_ICAP_o : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL3_ICAP_o : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL4_ICAP_o : STD_LOGIC_VECTOR (15 downto 0);
signal rst : STD_LOGIC;
signal clk : STD_LOGIC;
signal CTR0_o : r_CTR0;
signal CTR1_i : r_CTR1;
signal STAT_i : r_STAT;
signal MBA_i : r_BAR;
signal GBA_i : r_BAR;
signal MBA_ICAP_o : STD_LOGIC_VECTOR (23 downto 0);
signal GBA_ICAP_o : STD_LOGIC_VECTOR (23 downto 0));
constant clk_period : TIME := 200 ns;
constant OP_FULLMULTIBOOT : STD_LOGIC_VECTOR(3 downto 0) := X"0";
constant OP_WR_GENERAL1 : STD_LOGIC_VECTOR(3 downto 0) := X"1";
constant OP_WR_GENERAL2 : STD_LOGIC_VECTOR(3 downto 0) := X"2";
constant OP_WR_GENERAL3 : STD_LOGIC_VECTOR(3 downto 0) := X"3";
constant OP_WR_GENERAL4 : STD_LOGIC_VECTOR(3 downto 0) := X"4";
constant OP_RD_GENERAL1 : STD_LOGIC_VECTOR(3 downto 0) := X"5";
constant OP_RD_GENERAL2 : STD_LOGIC_VECTOR(3 downto 0) := X"6";
constant OP_RD_GENERAL3 : STD_LOGIC_VECTOR(3 downto 0) := X"7";
constant OP_RD_GENERAL4 : STD_LOGIC_VECTOR(3 downto 0) := X"8";
constant OP_IPROG : STD_LOGIC_VECTOR(3 downto 0) := X"C";
constant OP_STAT : STD_LOGIC_VECTOR(3 downto 0) := X"D";
file file_handler : TEXT;
constant log_path : STRING := "../test/log/multiboot_core_tb.log";
constant sep : CHARACTER := ht;
file file_handler : TEXT;
constant c_LOG_PATH : STRING := "../test/log/multiboot_core_tb.log";
constant sep : CHARACTER := ht;
begin
uut: multiboot_core
port map(
clk => clk,
rst => rst,
CTRL0_i => CTRL0_i,
CTRL1_o => CTRL1_o,
STAT_ICAP_o => STAT_ICAP_o,
GENERAL1_i => GENERAL1_i,
GENERAL2_i => GENERAL2_i,
GENERAL3_i => GENERAL3_i,
GENERAL4_i => GENERAL4_i,
GENERAL1_ICAP_o => GENERAL1_ICAP_o,
GENERAL2_ICAP_o => GENERAL2_ICAP_o,
GENERAL3_ICAP_o => GENERAL3_ICAP_o,
GENERAL4_ICAP_o => GENERAL4_ICAP_o
);
port map(clk => clk,
rst => rst,
CTR0_o => CTR0_o,
CTR1_i => CTR1_i,
STAT_i => STAT_i,
MBA_i => MBA_i,
GBA_i => GBA_i,
MBA_ICAP_o => MBA_addr_o,
GBA_ICAP_o => GBA_addr_o);
clk_process: process
begin
clk <= '1';
wait for clk_period/2;
wait for c_CLK_PERIOD/2;
clk <= '0';
wait for clk_period/2;
wait for c_CLK_PERIOD/2;
end process;
......@@ -95,201 +55,193 @@ begin
procedure reset_proc is
begin
wait for clk_period;
GENERAL1_i <= (others => '0');
GENERAL2_i <= (others => '0');
GENERAL3_i <= (others => '0');
GENERAL4_i <= (others => '0');
CTRL0_i <= (others => '0');
wait until rising_edge(clk);
rst <= '1';
wait for clk_period;
CTR1_i <= c_CTR1_default;
wait for c_CLK_PERIOD;
rst <= '0';
wait for clk_period*25;
wait for c_CLK_PERIOD*25;
end reset_proc;
procedure assert16_to_file(data : STD_LOGIC_VECTOR(15 downto 0);
reference : STD_LOGIC_VECTOR(15 downto 0);
test_id : STRING;
msg : STRING) is
variable line_buffer : LINE;
begin
if data = reference then
write(line_buffer, string'(test_id&sep&"OK"&sep&msg));
else
write(line_buffer, string'(test_id&sep&"Fail"&sep&msg));
end if;
writeline(file_handler, line_buffer);
assert data = reference report "Bad"&msg;
end procedure;
procedure assert32_to_file(data : STD_LOGIC_VECTOR(31 downto 0);
reference : STD_LOGIC_VECTOR(31 downto 0);
test_id : STRING;
msg : STRING) is
variable line_buffer : LINE;
begin
if data = reference then
write(line_buffer, string'(test_id&sep&"OK"&sep&msg));
else
write(line_buffer, string'(test_id&sep&"Fail"&sep&msg));
end if;
writeline(file_handler, line_buffer);
assert data = reference report "Bad"&msg;
end procedure;
procedure assert16_to_file(data:STD_LOGIC_VECTOR(15 downto 0);
reference:STD_LOGIC_VECTOR(15 downto 0);
test_id :string; msg :string) is
variable line_buffer : LINE;
begin
if data = reference then
write(line_buffer, string'(test_id&sep&"OK"&sep&msg));
else
write(line_buffer, string'(test_id&sep&"Fail"&sep&msg));
end if;
writeline(file_handler, line_buffer);
assert data = reference report "Bad"&msg;
end procedure;
procedure assert32_to_file(data:STD_LOGIC_VECTOR(31 downto 0);
reference:STD_LOGIC_VECTOR(31 downto 0);
test_id :string; msg :string) is
variable header_line_buffer : LINE;
variable line_buffer : LINE;
begin
if data = reference then
write(line_buffer, string'(test_id&sep&"OK"&sep&msg));
else
write(line_buffer, string'(test_id&sep&"Fail"&sep&msg));
end if;
writeline(file_handler, line_buffer);
assert data = reference report "Bad"&msg;
end procedure;
variable header_line_buffer : LINE;
begin
file_open(file_handler, log_path, WRITE_MODE);
write(header_line_buffer, string'("-----------------------------------------"));
writeline(file_handler, header_line_buffer);
write(header_line_buffer, string'("----- multiboot_core_tb.vhd -----"));
writeline(file_handler, header_line_buffer);
write(header_line_buffer, string'("-----------------------------------------"));
writeline(file_handler, header_line_buffer);
write(header_line_buffer, string'(""));
writeline(file_handler, header_line_buffer);
write(header_line_buffer, string'("Test ID"&sep&"Status"&sep&"Description"));
writeline(file_handler, header_line_buffer);
-- Initialization assert
wait for 2*clk_period;
reset_proc;
assert16_to_file(GENERAL1_ICAP_o, X"0000", "0x0", "GENERAL1_ICAP register initialization");
assert16_to_file(GENERAL2_ICAP_o, X"0000", "0x1", "GENERAL2_ICAP register initialization");
assert16_to_file(GENERAL3_ICAP_o, X"0000", "0x2", "GENERAL3_ICAP register initialization");
assert16_to_file(GENERAL4_ICAP_o, X"0000", "0x3", "GENERAL4_ICAP register initialization");
assert16_to_file(STAT_ICAP_o, X"0000", "0x4", "STAT_ICAP register initialization");
GENERAL1_i <= X"1234";
GENERAL2_i <= X"5678";
GENERAL3_i <= X"9ABC";
GENERAL4_i <= X"DEF0";
-- We will test the full multiboot sequence
CTRL0_i(3 downto 0) <= OP_FULLMULTIBOOT;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 13*clk_period;
wait for clk_period/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0x5", "Multiboot sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_WR_GENERAL1;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 5*clk_period;
wait for clk_period/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0x6", "GENERAL1 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_WR_GENERAL2;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 5*clk_period;
wait for clk_period/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0x7", "GENERAL2 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_WR_GENERAL3;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 5*clk_period;
wait for clk_period/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0x8", "GENERAL3 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_WR_GENERAL4;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 5*clk_period;
wait for clk_period/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0x9", "GENERAL4 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_RD_GENERAL1;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 15*clk_period;
wait for clk_period/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0xA", "GENERAL1 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_RD_GENERAL2;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 15*clk_period;
wait for clk_period/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0xB", "GENERAL2 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_RD_GENERAL3;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 15*clk_period;
wait for clk_period/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0xC", "GENERAL3 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_RD_GENERAL4;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 15*clk_period;
wait for clk_period/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0xD", "GENERAL4 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
assert false report "No error. Simulation ends." severity failure;
end process tb;
end;
file_open(file_handler, c_LOG_PATH, WRITE_MODE);
write(header_line_buffer, string'("-----------------------------------------"));
writeline(file_handler, header_line_buffer);
write(header_line_buffer, string'("----- multiboot_core_tb.vhd -----"));
writeline(file_handler, header_line_buffer);
write(header_line_buffer, string'("-----------------------------------------"));
writeline(file_handler, header_line_buffer);
write(header_line_buffer, string'(""));
writeline(file_handler, header_line_buffer);
write(header_line_buffer, string'("Test ID"&sep&"Status"&sep&"Description"));
writeline(file_handler, header_line_buffer);
-- Initialization assert
wait for 2*c_CLK_PERIOD;
reset_proc;
assert16_to_file(GENERAL1_ICAP_o, X"0000", "0x0", "GENERAL1_ICAP register initialization");
assert16_to_file(GENERAL2_ICAP_o, X"0000", "0x1", "GENERAL2_ICAP register initialization");
assert16_to_file(GENERAL3_ICAP_o, X"0000", "0x2", "GENERAL3_ICAP register initialization");
assert16_to_file(GENERAL4_ICAP_o, X"0000", "0x3", "GENERAL4_ICAP register initialization");
assert16_to_file(STAT_ICAP_o, X"0000", "0x4", "STAT_ICAP register initialization");
GENERAL1_i <= X"1234";
GENERAL2_i <= X"5678";
GENERAL3_i <= X"9ABC";
GENERAL4_i <= X"DEF0";
-- We will test the full multiboot sequence
CTR0_i(3 downto 0) <= OP_FULLMULTIBOOT;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 13*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTR1_o, X"0001", "0x5", "Multiboot sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_WR_GENERAL1;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 5*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTR1_o, X"0001", "0x6", "GENERAL1 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_WR_GENERAL2;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 5*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTR1_o, X"0001", "0x7", "GENERAL2 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_WR_GENERAL3;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 5*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTR1_o, X"0001", "0x8", "GENERAL3 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_WR_GENERAL4;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 5*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTR1_o, X"0001", "0x9", "GENERAL4 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_RD_GENERAL1;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 15*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTR1_o, X"0001", "0xA", "GENERAL1 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_RD_GENERAL2;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 15*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTR1_o, X"0001", "0xB", "GENERAL2 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_RD_GENERAL3;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 15*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTR1_o, X"0001", "0xC", "GENERAL3 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_RD_GENERAL4;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 15*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTR1_o, X"0001", "0xD", "GENERAL4 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
assert false report "No error. Simulation ends." severity failure;
end process tb;
end;
hdl/multiboot/test/multiboot_top_tb.vhd
View file @ a9e62b25
-- TestBench Template
-- TestBench Template
library IEEE;
library work;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use STD.TEXTIO.ALL;
use work.multiboot_pkg.ALL;
ENTITY multiboot_tb IS
END multiboot_tb;
entity multiboot_tb is
end multiboot_tb;
ARCHITECTURE behavior OF multiboot_tb IS
architecture behavior of multiboot_tb is
-- Component Declaration
component multiboot_top is
......@@ -28,71 +30,53 @@ ARCHITECTURE behavior OF multiboot_tb IS
wb_err_o : out STD_LOGIC);
end component;
signal wb_rst_i : STD_LOGIC;
signal wb_clk : STD_LOGIC;
signal wb_we_i : STD_LOGIC;
signal wb_stb_i : STD_LOGIC;
signal wb_cyc_i : STD_LOGIC;
signal wb_sel_i : STD_LOGIC;
signal wb_data_i : STD_LOGIC_VECTOR(31 downto 0);
signal wb_data_o : STD_LOGIC_VECTOR(31 downto 0);
signal wb_addr_i : STD_LOGIC_VECTOR(3 downto 0);
signal wb_ack_o : STD_LOGIC;
signal wb_rty_o : STD_LOGIC;
signal wb_err_o : STD_LOGIC;
constant wb_clk_period : TIME := 50 ns;
constant OP_FULLMULTIBOOT : STD_LOGIC_VECTOR(3 downto 0) := X"0";
constant OP_GENERAL1 : STD_LOGIC_VECTOR(3 downto 0) := X"1";
constant OP_GENERAL2 : STD_LOGIC_VECTOR(3 downto 0) := X"2";
constant OP_GENERAL3 : STD_LOGIC_VECTOR(3 downto 0) := X"3";
constant OP_GENERAL4 : STD_LOGIC_VECTOR(3 downto 0) := X"4";
constant OP_IPROG : STD_LOGIC_VECTOR(3 downto 0) := X"7";
constant OP_STAT : STD_LOGIC_VECTOR(3 downto 0) := X"D";
constant CTRL0_addr : STD_LOGIC_VECTOR(3 downto 0) := X"0";
constant CTRL1_addr : STD_LOGIC_VECTOR(3 downto 0) := X"1";
constant STAT_addr : STD_LOGIC_VECTOR(3 downto 0) := X"2";
constant GENERAL1_addr : STD_LOGIC_VECTOR(3 downto 0) := X"4";
constant GENERAL2_addr : STD_LOGIC_VECTOR(3 downto 0) := X"5";
constant GENERAL3_addr : STD_LOGIC_VECTOR(3 downto 0) := X"6";
constant GENERAL4_addr : STD_LOGIC_VECTOR(3 downto 0) := X"7";
signal CTRL_data : STD_LOGIC_VECTOR(31 downto 0);
signal wb_rst_i : STD_LOGIC;
signal wb_clk : STD_LOGIC;
signal wb_we_i : STD_LOGIC;
signal wb_stb_i : STD_LOGIC;
signal wb_cyc_i : STD_LOGIC;
signal wb_sel_i : STD_LOGIC;
signal wb_data_i : STD_LOGIC_VECTOR(31 downto 0);
signal wb_data_o : STD_LOGIC_VECTOR(31 downto 0);
signal wb_addr_i : STD_LOGIC_VECTOR(3 downto 0);
signal wb_ack_o : STD_LOGIC;
signal wb_rty_o : STD_LOGIC;
signal wb_err_o : STD_LOGIC;
constant c_WB_CLK_PERIOD : TIME := 50 ns;
signal CTRL_data : STD_LOGIC_VECTOR(31 downto 0);
signal GENERAL1_data : STD_LOGIC_VECTOR(31 downto 0);
signal GENERAL2_data : STD_LOGIC_VECTOR(31 downto 0);
signal GENERAL3_data : STD_LOGIC_VECTOR(31 downto 0);
signal GENERAL4_data : STD_LOGIC_VECTOR(31 downto 0);
file file_handler : TEXT;
constant log_path : STRING := "../test/log/multiboot_top_tb.log";
constant c_LOG_PATH : STRING := "../test/log/multiboot_top_tb.log";
constant sep : CHARACTER := ht;
begin
uut: multiboot_top
port map(
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o
);
port map(wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o);
wb_clk_process: process
begin
wb_clk <= '1';
wait for wb_clk_period/2;
wait for c_WB_CLK_PERIOD/2;
wb_clk <= '0';
wait for wb_clk_period/2;
wait for c_WB_CLK_PERIOD/2;
end process;
......@@ -100,11 +84,11 @@ begin
procedure rst is
begin
wait for wb_clk_period;
wait for c_WB_CLK_PERIOD;
wb_rst_i <= '1';
wait for wb_clk_period;
wait for c_WB_CLK_PERIOD;
wb_rst_i <= '0';
wait for wb_clk_period*25;
wait for c_WB_CLK_PERIOD*25;
end rst;
procedure read_wishbone(addr: STD_LOGIC_VECTOR(3 downto 0)) is
......@@ -114,7 +98,7 @@ begin
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_addr_i <= addr;
wait for wb_clk_period*3/2;
wait for c_WB_CLK_PERIOD*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
......@@ -130,7 +114,7 @@ begin
wb_cyc_i <= '1';
wb_addr_i <= addr;
wb_data_i <= data;
wait for wb_clk_period*3/2;
wait for c_WB_CLK_PERIOD*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
......@@ -145,12 +129,12 @@ begin
variable line_buffer : LINE;
begin
if data = reference then
write(line_buffer, string'(test_id&sep&"OK"&sep&msg));
write(line_buffer, string'(test_id&sep&"OK"&sep&msg));
else
write(line_buffer, string'(test_id&sep&"Fail"&sep&msg));
write(line_buffer, string'(test_id&sep&"Fail"&sep&msg));
end if;
writeline(file_handler, line_buffer);
assert data = reference report "Bad"&msg;
assert data = reference report "Bad"&msg;
end procedure;
procedure assert32_to_file(data:STD_LOGIC_VECTOR(31 downto 0);
......@@ -160,31 +144,31 @@ begin
variable line_buffer : LINE;
begin
if data = reference then
write(line_buffer, string'(test_id&sep&"OK"&sep&msg));
write(line_buffer, string'(test_id&sep&"OK"&sep&msg));
else
write(line_buffer, string'(test_id&sep&"Fail"&sep&msg));
write(line_buffer, string'(test_id&sep&"Fail"&sep&msg));
end if;
writeline(file_handler, line_buffer);
assert data = reference report "Bad"&msg;
assert data = reference report "Bad"&msg;
end procedure;
variable header_line_buffer : LINE;
begin
file_open(file_handler, log_path, WRITE_MODE);
file_open(file_handler, c_LOG_PATH, WRITE_MODE);
write(header_line_buffer, string'("Test ID"&sep&"Status"&sep&"Description"));
writeline(file_handler, header_line_buffer);
wait for 2*wb_clk_period;
wait for 2*c_WB_CLK_PERIOD;
rst;
GENERAL1_data <= (others => '0');
GENERAL1_data <= (others => '0');
GENERAL2_data <= (others => '0');
GENERAL3_data <= (others => '0');
GENERAL4_data <= (others => '0');
wait for 2*wb_clk_period;
wait for 2*c_WB_CLK_PERIOD;
read_wishbone(CTRL_addr);
assert32_to_file(wb_data_o, X"00000000","0x0","CTRL register initialization");
read_wishbone(STAT_addr);
......
hdl/spi_master_multifield/rtl/spi_master_core.vhd
View file @ a9e62b25
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
......@@ -15,25 +15,25 @@
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 17:34:27 06/14/2012
-- Design Name:
-- Module Name: spi_master_core - Behavioral
--
-- Create Date: 17:34:27 06/14/2012
-- Design Name:
-- Module Name: spi_master_core - Behavioral
-- Project Name: CTDAH/SVEC
-- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description: This is a spi_master with programmable field length and progra
-- mmable setup and hold chip select times.
--
-- Dependencies:
-- Dependencies:
--
-- Revision: 0.1
-- 0.01 + File Created
-- 0.1 - Alpha version. Able to write and output data correctly at
-- different configurations.
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
......@@ -53,7 +53,7 @@ entity spi_master_core is
port(
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
inst_i : in STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
......@@ -124,12 +124,12 @@ signal s_STATUS : r_STATUS;
constant c_STATUS_DEFAULT : r_STATUS := (clk_fsm => S0_IDLE,
spi_clk_fsm => S0_IDLE,
PULL_INST => '0',
PULL_ADDR => '0',
PULL_INST => '0',
PULL_ADDR => '0',
PULL_DATA => '0');
signal s_spi_clk_fsm_d0 : SPI_spi_clk_fsm;
signal s_clk_fsm_d0 : SPI_clk_fsm;
signal s_spi_clk_fsm_d0 : SPI_spi_clk_fsm;
signal s_clk_fsm_d0 : SPI_clk_fsm;
constant c_CS_SU_TICKS : NATURAL := c_CS_SU_SPI/g_CLK_I_PERIOD + 1;
constant c_CS_HOLD_TICKS : NATURAL := c_CS_HOLD_SPI/g_CLK_I_PERIOD + 1;
......@@ -142,7 +142,7 @@ signal s_timing_counter_manual_rst_i : STD_LOGIC;
signal s_timing_counter_rst_i : STD_LOGIC;
signal s_timing_counter_cnt : STD_LOGIC_VECTOR(c_COUNTER_DATA_WIDTH
- 1 downto 0);
signal s_read_edge_counter_clk : STD_LOGIC;
signal s_read_edge_counter_clk : STD_LOGIC;
signal s_read_edge_counter_en : STD_LOGIC;
signal s_read_edge_counter_manual_rst_clk : STD_LOGIC;
signal s_read_edge_counter_rst_i : STD_LOGIC;
......@@ -174,7 +174,7 @@ begin
s_SPI0 <= f_SPI0(SPI0_i);
s_SPI1 <= f_SPI1(SPI1_i);
SPI2_o <= f_STD_LOGIC_VECTOR(s_SPI2);
SPI3_o <= s_spi_miso_data;
SPI3_o <= s_spi_miso_data;
spi_clk_o <= s_spi_clk_d0 when s_SPI0.CPOL = '0'
else s_spi_clk_n_d0;
......@@ -192,7 +192,7 @@ begin
load => s_SPI1_core.PUSH_INST,
flush => rst_i,
oen_i => s_STATUS.PULL_INST,
reg_o => s_inst_reg_o
reg_o => s_inst_reg_o
);
addr_fifo_i2c: FIFO_dispatcher
......@@ -245,11 +245,11 @@ begin
spi_cclk: gc_clk_divider
generic map( g_clk_division_logSize => 4)
port map(
clk_i => clk_i,
rst_i => s_spi_clk_rst_i,
oe_n_i => s_spi_clk_divider_oe_n,
clk_o => s_spi_clk_tmp,
divider_i => s_spi_clk_divider_i
clk_i => clk_i,
rst_i => s_spi_clk_rst_i,
oe_n_i => s_spi_clk_divider_oe_n,
clk_o => s_spi_clk_tmp,
divider_i => s_spi_clk_divider_i
);
s_spi_clk <= s_spi_clk_tmp;
......@@ -257,17 +257,17 @@ begin
ff_spi_clk_d0: gc_ff
port map(
Q => s_spi_clk_d0,
C => clk_i,
CLR => rst_i,
Q => s_spi_clk_d0,
C => clk_i,
CLR => rst_i,
D => s_spi_clk
);
ff_spi_clk_n_d0: gc_ff
port map(
Q => s_spi_clk_n_d0,
C => clk_i,
CLR => rst_i,
Q => s_spi_clk_n_d0,
C => clk_i,
CLR => rst_i,
D => s_spi_clk_n
);
......@@ -276,7 +276,7 @@ begin
-----------------------------------------------------------
--! Counter for spi read edges
-----------------------------------------------------------
s_read_edge_counter_clk <= s_spi_clk_d0 when s_SPI0.CPHA = '0'
s_read_edge_counter_clk <= s_spi_clk_d0 when s_SPI0.CPHA = '0'
else s_spi_clk_n_d0;
s_read_edge_counter_rst_i <= s_read_edge_counter_manual_rst_clk
or rst_i;
......@@ -291,7 +291,7 @@ begin
);
-----------------------------------------------------------
--! Control of the chip select line
--! Control of the chip select line
-----------------------------------------------------------
p_chip_select :process(clk_i)
begin
......@@ -332,7 +332,7 @@ begin
end process p_fsm_delays;
-----------------------------------------------------------
--! HW crop of bad length fields configuration
--! HW crop of bad length fields configuration
-----------------------------------------------------------
p_comb_addr_length_bytes : process(s_SPI0)
begin
......@@ -346,25 +346,25 @@ begin
s_SPI0_core.CPOL <= s_SPI0.CPOL;
s_SPI0_core.CPHA <= s_SPI0.CPHA;
if (to_integer(s_SPI0.BINST) <= to_unsigned(c_INST_LENGTH, 9)) then
if (to_integer(s_SPI0.BINST) <= to_unsigned(c_INST_LENGTH, 9)) then
s_SPI0_core.BINST <= s_SPI0.BINST;
else
s_SPI0_core.BINST <= to_unsigned(c_INST_LENGTH, 9);
end if;
if (to_integer(s_SPI0.BADDR) <= to_unsigned(c_ADDR_LENGTH, 9)) then
s_SPI0_core.BADDR <= s_SPI0.BADDR;
s_SPI0_core.BADDR <= s_SPI0.BADDR;
else
s_SPI0_core.BADDR <= to_unsigned(c_ADDR_LENGTH, 9);
end if;
if (to_integer(s_SPI0.BDATA) <= to_unsigned(c_DATA_LENGTH, 9)) then
if (to_integer(s_SPI0.BDATA) <= to_unsigned(c_DATA_LENGTH, 9)) then
s_SPI0_core.BDATA <= s_SPI0.BDATA;
else
s_SPI0_core.BDATA <= to_unsigned(c_DATA_LENGTH, 9);
end if;
if (to_integer(s_SPI0.BREAD) <= to_unsigned(c_READ_LENGTH, 3)) then
if (to_integer(s_SPI0.BREAD) <= to_unsigned(c_READ_LENGTH, 3)) then
s_SPI0_core.BREAD <= s_SPI0.BREAD;
else
s_SPI0_core.BREAD <= to_unsigned(c_READ_LENGTH, 3);
......@@ -374,7 +374,7 @@ begin
end process p_comb_addr_length_bytes;
-----------------------------------------------------------
--! HW crop of bad instructions
--! HW crop of bad instructions
-----------------------------------------------------------
p_comb_SPI1_ctrl: process(s_SPI0_core, s_SPI1, s_STATUS.clk_fsm)
begin
......@@ -472,12 +472,12 @@ begin
end process p_comb_SPI1_ctrl;
-----------------------------------------------------------
--! Process to control the load of the FIFOs
--! Process to control the load of the FIFOs
-----------------------------------------------------------
p_SPI1_PUSH_ctrl : process(s_STATUS.clk_fsm, s_clk_fsm_d0)
begin
s_SPI1_core.PUSH_INST <= c_SPI1_default.PUSH_INST;
s_SPI1_core.PUSH_ADDR <= c_SPI1_default.PUSH_ADDR;
s_SPI1_core.PUSH_INST <= c_SPI1_default.PUSH_INST;
s_SPI1_core.PUSH_ADDR <= c_SPI1_default.PUSH_ADDR;
s_SPI1_core.PUSH_DATA <= c_SPI1_default.PUSH_DATA;
--! As the S1_SETUP will take one clock at least, we push
--! from SPI1 into internal s_SPI1_core, depending upon the
......@@ -577,11 +577,11 @@ begin
s_STATUS.PULL_DATA <= c_STATUS_default.PULL_DATA;
case s_STATUS.spi_clk_fsm is
when S2P_INST =>
s_STATUS.PULL_INST <= '1';
s_STATUS.PULL_INST <= '1';
when S3P_ADDR =>
s_STATUS.PULL_ADDR <= '1';
s_STATUS.PULL_ADDR <= '1';
when S4P_DATA =>
s_STATUS.PULL_DATA <= '1';
s_STATUS.PULL_DATA <= '1';
when others =>
null;
end case;
......@@ -654,7 +654,7 @@ begin
end process p_comb_SPI2_reg;
-----------------------------------------------------------
--! Combinational process for enable pin of the spi_read_edge_counter
--! Combinational process for enable pin of the spi_read_edge_counter
-----------------------------------------------------------
p_comb_spi_read_edge_counter_en : process(s_STATUS.clk_fsm) is
begin
......@@ -776,7 +776,7 @@ begin
end process p_spi_mosi_output;
-----------------------------------------------------------
--! SPI DUP field
--! SPI DUP field
-----------------------------------------------------------
p_comb_miso : process (rst_i, s_STATUS.spi_clk_fsm,
s_STATUS.clk_fsm) is
......@@ -818,7 +818,7 @@ begin
end process p_miso;
-----------------------------------------------------------
--! fsm to determine access to SPI lines
--! fsm to determine access to SPI lines
-----------------------------------------------------------
p_comb_rd_miso : process(s_STATUS.clk_fsm, s_STATUS.spi_clk_fsm)
begin
......@@ -833,7 +833,7 @@ begin
end process p_comb_rd_miso;
-----------------------------------------------------------
--! fsm to determine access to SPI lines
--! fsm to determine access to SPI lines
-----------------------------------------------------------
p_clk_fsm: process(clk_i)
begin
......@@ -908,7 +908,7 @@ begin
next_fsm_state0 : SPI_spi_clk_fsm;
next_fsm_state1 : SPI_spi_clk_fsm) is
begin
if s_SPI0_core.CPOL = '0' then
if s_SPI0_core.CPOL = '0' then
updater(max_value, next_fsm_state0, next_fsm_state1,
s_spi_clk, s_spi_clk_d0);
else
......@@ -972,13 +972,13 @@ begin
case s_STATUS.spi_clk_fsm is
when S1_START_SPI_CLK =>
if s_SPI1_core.SEND_INST = '1' then
s_STATUS.spi_clk_fsm <= S2P_INST;
s_STATUS.spi_clk_fsm <= S2P_INST;
else
s_STATUS.spi_clk_fsm <= S6_STOP_SPI_CLK;
s_STATUS.spi_clk_fsm <= S6_STOP_SPI_CLK;
end if;
when S6_STOP_SPI_CLK =>
if s_spi_clk_divider_oe_n = '1' then
s_STATUS.spi_clk_fsm <= Q0_END;
s_STATUS.spi_clk_fsm <= Q0_END;
else
end if;
when Q0_END =>
......
hdl/spi_master_multifield/rtl/spi_master_pkg.vhd
View file @ a9e62b25
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
......@@ -15,25 +15,25 @@
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:03:11 06/19/2012
-- Design Name:
-- Module Name: spi_master_pkg - Behavioral
--
-- Create Date: 11:03:11 06/19/2012
-- Design Name:
-- Module Name: spi_master_pkg - Behavioral
-- Project Name: CTDAH/SVEC
-- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description: Package providing all the register configurations for the
-- SPI core.
--
-- Dependencies:
-- Dependencies:
--
-- Revision: 0.1
-- 0.01 + File Created
-- 0.1 - Alpha version. Able to write and output data correctly at
-- different configurations.
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
......@@ -55,18 +55,18 @@ package spi_master_pkg is
-- 0 CPOL Clock POLarity when idle
-- 1 CPHA Clock PHAse
-- 4-2 BREAD Bytes to be READ
-- 13-5 BDATA Bytes of DATA to be sent
-- 22-14 BADDR Bytes of ADDRess to be sent
-- 31-23 BINST Bytes of INSTruction to be sent
-- 13-5 BDATA Bytes of DATA to be sent
-- 22-14 BADDR Bytes of ADDRess to be sent
-- 31-23 BINST Bytes of INSTruction to be sent
----------------------------------------
type r_SPI0 is
record
CPOL : STD_LOGIC;
CPHA : STD_LOGIC;
BREAD : UNSIGNED (4 downto 2);
BDATA : UNSIGNED (13 downto 5);
BADDR : UNSIGNED (22 downto 14);
BINST : UNSIGNED (31 downto 23);
BDATA : UNSIGNED (13 downto 5);
BADDR : UNSIGNED (22 downto 14);
BINST : UNSIGNED (31 downto 23);
end record;
attribute a_length of r_SPI0 : type is 32;
......@@ -79,14 +79,14 @@ package spi_master_pkg is
----------------------------------------
-- BIT NAME DESCRIPTION
-- 0 PUSH_DATA PUSH DATA bytes into internal SPI
-- core memory
-- core memory
-- 1 PUSH_ADDR PUSH ADDRess bytes into internal SPI
-- core memory
-- core memory
-- 2 PUSH_INST PUSH INSTruction bytes into internal
-- SPI core memory
-- SPI core memory
-- 5-3 x Reserved
-- 6 READ_MISO READ from MISO line
-- 7 SEND_DATA DATA bytes will be sent in a write operation
-- 7 SEND_DATA DATA bytes will be sent in a write operation
-- 8 SEND_ADDR ADDR bytes will be sent in a write operation
-- 9 SEND_INST INST bytes will be sent in a write operation
-- 10 SEND_OP perform a SEND OPeration
......@@ -96,8 +96,8 @@ package spi_master_pkg is
----------------------------------------
type r_SPI1 is
record
PUSH_DATA : STD_LOGIC;
PUSH_ADDR : STD_LOGIC;
PUSH_DATA : STD_LOGIC;
PUSH_ADDR : STD_LOGIC;
PUSH_INST : STD_LOGIC;
x : STD_LOGIC_VECTOR(5 downto 3);
READ_MISO : STD_LOGIC;
......@@ -121,8 +121,8 @@ package spi_master_pkg is
-- BIT NAME DESCRIPTION
-- 0 MISO_DUP MOSI Data UPdate
-- 1 READ_DONE READ process DONE
-- 2 SENT_DATA DATA was SENT
-- 3 SENT_ADDR ADDRess was SENT
-- 2 SENT_DATA DATA was SENT
-- 3 SENT_ADDR ADDRess was SENT
-- 4 SENT_INST INSTruction was SENT
-- 5 SENT_OP OPeration was SENT
-- 11-6 x Reserved
......@@ -148,7 +148,7 @@ package spi_master_pkg is
-- Wishbone access: Read-only
----------------------------------------
-- BIT NAME DESCRIPTION
-- 31-0 MOSI_DATA DATA received from MOSI pin.
-- 31-0 MOSI_DATA DATA received from MOSI pin.
----------------------------------------
type r_SPI3 is
record
......@@ -163,7 +163,7 @@ package spi_master_pkg is
S1_SETUP,
S2_SPI_ACTIVITY,
S3_HOLD);
type SPI_spi_clk_fsm is (S0_IDLE,
S1_START_SPI_CLK,
S2P_INST,
......@@ -176,7 +176,7 @@ package spi_master_pkg is
S5U_READ,
S6_STOP_SPI_CLK,
Q0_END);
type r_STATUS is
record
clk_fsm : SPI_clk_fsm;
......@@ -188,8 +188,8 @@ package spi_master_pkg is
constant c_INST_LENGTH : NATURAL := 1;
constant c_ADDR_LENGTH : NATURAL := 3;
constant c_INST_LENGTH : NATURAL := 1;
constant c_ADDR_LENGTH : NATURAL := 3;
constant c_DATA_LENGTH : NATURAL := 256;
constant c_READ_LENGTH : NATURAL := 4;
......@@ -221,16 +221,16 @@ package spi_master_pkg is
y => '0',
CLK_DIV => c_CLK_DIV,
z => (others => '0'));
constant c_SPI2_default : r_SPI2 := (SENT_DATA => '0',
SENT_ADDR => '0',
SENT_INST => '0',
constant c_SPI2_default : r_SPI2 := (SENT_DATA => '0',
SENT_ADDR => '0',
SENT_INST => '0',
SENT_OP => '0',
MISO_DUP => '0',
READ_DONE => '0',
x => (others => '0'),
x => (others => '0'),
CLK_DIV => (others => '0'));
constant c_CLK_DIVISION_LOGSIZE : NATURAL := 2;
constant c_COUNTER_DATA_WIDTH : NATURAL := 12;
......@@ -240,10 +240,10 @@ package spi_master_pkg is
constant c_CS_HOLD_SPI : NATURAL := 100; --! ns
-- constant c_CS_HOLD_TICKS : NATURAL := c_CS_HOLD_SPI/c_CLK_I_PERIOD + 1;
constant c_SPI0_addr : STD_LOGIC_VECTOR (3 downto 0) := X"0";
constant c_SPI1_addr : STD_LOGIC_VECTOR (3 downto 0) := X"1";
constant c_SPI2_addr : STD_LOGIC_VECTOR (3 downto 0) := X"2";
constant c_SPI3_addr : STD_LOGIC_VECTOR (3 downto 0) := X"3";
constant c_SPI0_addr : STD_LOGIC_VECTOR (3 downto 0) := X"0";
constant c_SPI1_addr : STD_LOGIC_VECTOR (3 downto 0) := X"1";
constant c_SPI2_addr : STD_LOGIC_VECTOR (3 downto 0) := X"2";
constant c_SPI3_addr : STD_LOGIC_VECTOR (3 downto 0) := X"3";
function f_SPI0 (signal r_register : in STD_LOGIC_VECTOR(31 downto 0))
return r_SPI0;
......@@ -268,21 +268,21 @@ package spi_master_pkg is
spi_clk : in STD_LOGIC;
spi_clk_d0 : in STD_LOGIC) return STD_LOGIC;
function f_min(a: NATURAL; b: NATURAL) return NATURAL;
function f_min(a: NATURAL; b: NATURAL) return NATURAL;
end spi_master_pkg;
package body spi_master_pkg is
function f_min(a: NATURAL; b: NATURAL) return NATURAL is
variable ret: NATURAL;
begin
if a < b then
ret := a;
else
ret := b;
function f_min(a: NATURAL; b: NATURAL) return NATURAL is
variable ret: NATURAL;
begin
if a < b then
ret := a;
else
ret := b;
end if;
return ret;
end f_min;
end f_min;
-----------------------------------------------------------------------------
--! @brief SPI0 record type translation to STD_LOGIC_VECTOR
......@@ -294,8 +294,8 @@ package body spi_master_pkg is
& std_logic_vector(r_register.BADDR)
& std_logic_vector(r_register.BDATA)
& std_logic_vector(r_register.BREAD)
& r_register.CPHA
& r_register.CPOL);
& r_register.CPHA
& r_register.CPOL);
end f_STD_LOGIC_VECTOR;
......@@ -306,12 +306,12 @@ package body spi_master_pkg is
function f_SPI0 (signal r_register : in STD_LOGIC_VECTOR(31 downto 0)) return r_SPI0 is
variable v_SPI0 : r_SPI0;
begin
v_SPI0.CPOL := r_register(0);
v_SPI0.CPHA := r_register(1);
v_SPI0.BREAD := unsigned(r_register( 4 downto 2));
v_SPI0.BDATA := unsigned(r_register(13 downto 5));
v_SPI0.BADDR := unsigned(r_register(22 downto 14));
v_SPI0.BINST := unsigned(r_register(31 downto 23));
v_SPI0.CPOL := r_register(0);
v_SPI0.CPHA := r_register(1);
v_SPI0.BREAD := unsigned(r_register( 4 downto 2));
v_SPI0.BDATA := unsigned(r_register(13 downto 5));
v_SPI0.BADDR := unsigned(r_register(22 downto 14));
v_SPI0.BINST := unsigned(r_register(31 downto 23));
return v_SPI0;
end f_SPI0;
......@@ -326,11 +326,11 @@ package body spi_master_pkg is
& r_register.y
& r_register.SEND_OP
& r_register.SEND_INST & r_register.SEND_ADDR
& r_register.SEND_DATA & r_register.READ_MISO
& r_register.SEND_DATA & r_register.READ_MISO
& r_register.x
& r_register.PUSH_INST & r_register.PUSH_ADDR
& r_register.PUSH_DATA
);
);
end f_STD_LOGIC_VECTOR;
......@@ -341,18 +341,18 @@ package body spi_master_pkg is
function f_SPI1 (signal r_register : in STD_LOGIC_VECTOR(31 downto 0)) return r_SPI1 is
variable v_SPI1 : r_SPI1;
begin
v_SPI1.PUSH_DATA := r_register(0);
v_SPI1.PUSH_ADDR := r_register(1);
v_SPI1.PUSH_INST := r_register(2);
v_SPI1.x := r_register(5 downto 3);
v_SPI1.PUSH_DATA := r_register(0);
v_SPI1.PUSH_ADDR := r_register(1);
v_SPI1.PUSH_INST := r_register(2);
v_SPI1.x := r_register(5 downto 3);
v_SPI1.READ_MISO := r_register(6);
v_SPI1.SEND_DATA := r_register(7);
v_SPI1.SEND_ADDR := r_register(8);
v_SPI1.SEND_INST := r_register(9);
v_SPI1.SEND_DATA := r_register(7);
v_SPI1.SEND_ADDR := r_register(8);
v_SPI1.SEND_INST := r_register(9);
v_SPI1.SEND_OP := r_register(10);
v_SPI1.y := r_register(11);
v_SPI1.CLK_DIV := unsigned(r_register(15 downto 12));
v_SPI1.z := r_register(31 downto 16);
v_SPI1.y := r_register(11);
v_SPI1.CLK_DIV := unsigned(r_register(15 downto 12));
v_SPI1.z := r_register(31 downto 16);
return v_SPI1;
end f_SPI1;
......@@ -370,7 +370,7 @@ package body spi_master_pkg is
& r_register.SENT_OP
& r_register.SENT_INST
& r_register.SENT_ADDR
& r_register.SENT_DATA);
& r_register.SENT_DATA);
end f_STD_LOGIC_VECTOR;
......@@ -382,14 +382,14 @@ package body spi_master_pkg is
return r_SPI2 is
variable v_SPI2 : r_SPI2;
begin
v_SPI2.SENT_DATA := r_register(0);
v_SPI2.SENT_ADDR := r_register(1);
v_SPI2.SENT_INST := r_register(2);
v_SPI2.SENT_DATA := r_register(0);
v_SPI2.SENT_ADDR := r_register(1);
v_SPI2.SENT_INST := r_register(2);
v_SPI2.SENT_OP := r_register(3);
v_SPI2.MISO_DUP := r_register(4);
v_SPI2.READ_DONE := r_register(5);
v_SPI2.x := r_register(11 downto 6);
v_SPI2.CLK_DIV := unsigned(r_register(15 downto 12));
v_SPI2.CLK_DIV := unsigned(r_register(15 downto 12));
return v_SPI2;
end f_SPI2;
......@@ -401,7 +401,7 @@ package body spi_master_pkg is
function f_STD_LOGIC_VECTOR (r_register : in r_SPI3)
return STD_LOGIC_VECTOR is
begin
return ( std_logic_vector(r_register.MOSI_DATA));
return ( std_logic_vector(r_register.MOSI_DATA));
end f_STD_LOGIC_VECTOR;
......@@ -413,14 +413,14 @@ package body spi_master_pkg is
return r_SPI3 is
variable v_SPI3 : r_SPI3;
begin
v_SPI3.MOSI_DATA := r_register;
v_SPI3.MOSI_DATA := r_register;
return v_SPI3;
end f_SPI3;
-----------------------------------------------------------------------------
--! @brief Function that determines a read edge depending upon
--! CPOL and CPHA values.
--! @param r_register SPI0 register containing CPOL and CPHA
--! @param r_register SPI0 register containing CPOL and CPHA
--! spi_clk STD_LOGIC containing currently sampled spi clock value
--! spi_clk_d0 STD_LOGIC containing previously sampled spi clock value
-----------------------------------------------------------------------------
......@@ -447,7 +447,7 @@ package body spi_master_pkg is
-----------------------------------------------------------------------------
--! @brief Function that determines a write edge depending upon
--! CPOL and CPHA values.
--! @param r_register SPI0 register containing CPOL and CPHA
--! @param r_register SPI0 register containing CPOL and CPHA
--! spi_clk STD_LOGIC containing currently sampled spi clock value
--! spi_clk_d0 STD_LOGIC containing previously sampled spi clock value
-----------------------------------------------------------------------------
......
hdl/spi_master_multifield/rtl/spi_master_regs.vhd
View file @ a9e62b25
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
......@@ -15,24 +15,24 @@
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 17:34:08 06/14/2012
-- Design Name:
-- Module Name: spi_master_core - Behavioral
--
-- Create Date: 17:34:08 06/14/2012
-- Design Name:
-- Module Name: spi_master_core - Behavioral
-- Project Name: CTDAH/SVEC
-- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description: Wishbone access for SPI core.
-- Description: Wishbone access for SPI core.
--
-- Dependencies:
-- Dependencies:
--
-- Revision: 0.1
-- 0.01 + File Created
-- 0.1 - Alpha version. Able to write and output data correctly at
-- different configurations.
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
......@@ -44,22 +44,22 @@ use work.spi_master_pkg.ALL;
entity spi_master_regs is
port(
wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_we_i : in STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
SPI0_o : out STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
SPI1_o : out STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
SPI0_o : out STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
SPI1_o : out STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
SPI2_i : in STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
SPI3_i : in STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0);
......@@ -73,16 +73,16 @@ architecture Behavioral of spi_master_regs is
signal s_SPI2 : STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
signal s_wb_ack : STD_LOGIC;
signal s_wb_rty : STD_LOGIC;
signal s_wb_err : STD_LOGIC;
signal s_wb_rty : STD_LOGIC;
signal s_wb_err : STD_LOGIC;
begin
wb_ack_o <= s_wb_ack;
wb_rty_o <= s_wb_rty;
wb_err_o <= s_wb_err;
wb_ack_o <= s_wb_ack;
wb_rty_o <= s_wb_rty;
wb_err_o <= s_wb_err;
SPI0_o <= s_SPI0;
SPI0_o <= s_SPI0;
SPI1_o <= s_SPI1;
s_SPI2 <= SPI2_i;
......@@ -106,21 +106,21 @@ begin
case wb_addr_i is
when c_SPI0_addr =>
s_SPI0 <= wb_data_i;
s_wb_ack <= '1';
s_wb_ack <= '1';
when c_SPI1_addr =>
s_SPI1 <= wb_data_i;
s_wb_ack <= '1';
s_wb_ack <= '1';
when others =>
s_wb_err <= '1';
s_wb_err <= '1';
end case;
when others =>
case wb_addr_i is
when c_SPI0_addr =>
wb_data_o <= s_SPI0;
s_wb_ack <= '1';
s_wb_ack <= '1';
when c_SPI1_addr =>
wb_data_o <= s_SPI1;
s_wb_ack <= '1';
s_wb_ack <= '1';
when c_SPI2_addr =>
wb_data_o(15 downto 0) <= s_SPI2;
wb_data_o(31 downto 16) <= (others => '0');
......
hdl/spi_master_multifield/rtl/spi_master_top.vhd
View file @ a9e62b25
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
......@@ -15,25 +15,25 @@
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 17:10:27 06/15/2012
-- Design Name:
-- Module Name: spi_master_top - Behavioral
--
-- Create Date: 17:10:27 06/15/2012
-- Design Name:
-- Module Name: spi_master_top - Behavioral
-- Project Name: CTDAH/SVEC
-- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description: This is a spi_master with programable field length and progra
-- mable setup and hold chip select times.
--
-- Dependencies:
-- Dependencies:
--
-- Revision: 0.1
-- 0.01 + File Created
-- 0.1 - Alpha version. Able to write and output data correctly at
-- different configurations.
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
......@@ -48,7 +48,7 @@ entity spi_master_top is
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH;
g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD);
g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD);
port(
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
......@@ -108,7 +108,7 @@ architecture Behavioral of spi_master_top is
port(
wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
......@@ -119,7 +119,7 @@ architecture Behavioral of spi_master_top is
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
SPI0_o : out STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
SPI1_o : out STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
SPI2_i : in STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
......@@ -128,52 +128,52 @@ architecture Behavioral of spi_master_top is
end component;
signal s_SPI0 : STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
signal s_SPI1 : STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
signal s_SPI2 : STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
signal s_SPI3 : STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0);
signal s_SPI0 : STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
signal s_SPI1 : STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
signal s_SPI2 : STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
signal s_SPI3 : STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0);
begin
inst_spi_master_core: spi_master_core
inst_spi_master_core: spi_master_core
port map(
rst_i => wb_rst_i,
clk_i => wb_clk,
inst_i => inst_i,
addr_i => addr_i,
data_i => data_i,
SPI0_i => s_SPI0,
SPI1_i => s_SPI1,
SPI2_o => s_SPI2,
SPI3_o => s_SPI3,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
spi_clk_o => spi_clk_o,
spi_cs_n_o => spi_cs_n_o
rst_i => wb_rst_i,
clk_i => wb_clk,
inst_i => inst_i,
addr_i => addr_i,
data_i => data_i,
SPI0_i => s_SPI0,
SPI1_i => s_SPI1,
SPI2_o => s_SPI2,
SPI3_o => s_SPI3,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
spi_clk_o => spi_clk_o,
spi_cs_n_o => spi_cs_n_o
);
inst_spi_master_regs: spi_master_regs
port map(
wb_rst_i => wb_rst_i,
wb_rst_i => wb_rst_i,
wb_clk_i => wb_clk,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_we_i => wb_we_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
SPI0_o => s_SPI0,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_we_i => wb_we_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
SPI0_o => s_SPI0,
SPI1_o => s_SPI1,
SPI2_i => s_SPI2,
SPI3_i => s_SPI3,
SPI3_i => s_SPI3,
);
end Behavioral;
......
hdl/spi_master_multifield/test/spi_analyser.vhd
View file @ a9e62b25
--------------------------------------------------------------------------------
-- Company:
-- Company:
-- Engineer:
--
-- Create Date: 12:31:47 06/20/2012
-- Design Name:
-- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name: spi_master_multifield
-- Target Device:
-- Tool versions:
-- Description:
--
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: spi_master_core
--
--
-- Dependencies:
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
......@@ -50,23 +50,23 @@ entity spi_analyser is
inst_check_o : out STD_LOGIC_VECTOR (g_INST_LENGTH*8 - 1 downto 0);
addr_check_o : out STD_LOGIC_VECTOR (g_ADDR_LENGTH*8 - 1 downto 0);
data_check_o : out STD_LOGIC_VECTOR (g_DATA_LENGTH*8 - 1 downto 0);
end_inst_flag_o : out STD_LOGIC;
end_addr_flag_o : out STD_LOGIC;
end_data_flag_o : out STD_LOGIC
);
end spi_analyser;
architecture Behavioral of spi_analyser is
architecture Behavioral of spi_analyser is
signal s_spi_count : NATURAL := 0;
signal s_SPI0 : r_SPI0;
signal s_SPI1 : r_SPI1;
signal s_SPI1_tmp : r_SPI1;
signal s_spi_mosi : STD_LOGIC;
signal s_spi_clk : STD_LOGIC;
signal s_spi_mosi : STD_LOGIC;
signal s_spi_clk : STD_LOGIC;
signal s_inst_check : STD_LOGIC_VECTOR (g_INST_LENGTH*8 - 1 downto 0)
:= (others => '0');
......@@ -87,17 +87,17 @@ begin
inst_check_o <= s_inst_check;
addr_check_o <= s_addr_check;
data_check_o <= s_data_check;
end_inst_flag_o <= s_end_inst_flag;
end_addr_flag_o <= s_end_addr_flag;
end_data_flag_o <= s_end_data_flag;
end_inst_flag_o <= s_end_inst_flag;
end_addr_flag_o <= s_end_addr_flag;
end_data_flag_o <= s_end_data_flag;
s_SPI1_tmp <= SPI1_i;
p_latch : process (s_SPI1_tmp.SEND_OP)
begin
if rising_edge(s_SPI1_tmp.SEND_OP) then
s_SPI0 <= SPI0_i;
s_SPI0 <= SPI0_i;
s_SPI1 <= SPI1_i;
end if;
end process;
......@@ -130,11 +130,11 @@ begin
end if;
else
end if;
if s_SPI1.SEND_ADDR = '1' then
if s_SPI1.SEND_INST = '1' then
if s_spi_count >= (v_inst_length + v_addr_length) then
elsif s_spi_count >= v_inst_length
elsif s_spi_count >= v_inst_length
and s_spi_count < (v_inst_length + v_addr_length) then
s_addr_check(v_addr_length - 1 - (s_spi_count -
v_inst_length)) <= s_spi_mosi;
......@@ -158,7 +158,7 @@ begin
end if;
else
end if;
if s_SPI1.SEND_DATA = '1' then
if s_SPI1.SEND_INST = '1' then
if s_SPI1.SEND_ADDR = '1' then
......@@ -216,9 +216,9 @@ begin
begin
if rst_i = '1' then
s_spi_count <= 0;
s_inst_check <= (others => '0') ;
s_addr_check <= (others => '0') ;
s_data_check <= (others => '0') ;
s_inst_check <= (others => '0') ;
s_addr_check <= (others => '0') ;
s_data_check <= (others => '0') ;
else
if rising_edge(spi_clk_o) then
--! Read cycle
......
hdl/spi_master_multifield/test/spi_analyser_pkg.vhd
View file @ a9e62b25
--------------------------------------------------------------------------------
-- Company:
-- Company:
-- Engineer:
--
-- Create Date: 12:31:47 06/20/2012
-- Design Name:
-- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name: spi_master_multifield
-- Target Device:
-- Tool versions:
-- Description:
--
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: spi_master_core
--
--
-- Dependencies:
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
......@@ -32,7 +32,7 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.spi_master_pkg.ALL;
package spi_analyser_pkg is
package spi_analyser_pkg is
component spi_analyser
port( rst_i : in STD_LOGIC;
......@@ -102,7 +102,7 @@ package spi_analyser_pkg is
signal data_i : out STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0);
inst : in STD_LOGIC_VECTOR(8*c_INST_LENGTH - 1 downto 0);
addr : in STD_LOGIC_VECTOR(8*c_ADDR_LENGTH - 1 downto 0);
data : in STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0));
data : in STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0));
procedure send_SPI_and_wait (signal clk_i : in STD_LOGIC;
signal SPI1 : out r_SPI1;
......@@ -111,12 +111,12 @@ package spi_analyser_pkg is
send_addr: in STD_LOGIC;
send_data: in STD_LOGIC;
read_miso: in STD_LOGIC;
clk_div : in UNSIGNED(3 downto 0));
clk_div : in UNSIGNED(3 downto 0));
procedure set_SPI1 (
signal clk_i : in STD_LOGIC;
signal SPI1 : out r_SPI1;
signal SPI2 : in r_SPI2;
signal SPI1 : out r_SPI1;
signal SPI2 : in r_SPI2;
send_inst : in STD_LOGIC;
send_addr : in STD_LOGIC;
send_data : in STD_LOGIC;
......@@ -151,7 +151,7 @@ package spi_analyser_pkg is
signal data_i : out STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0);
inst : in STD_LOGIC_VECTOR(8*c_INST_LENGTH - 1 downto 0);
addr : in STD_LOGIC_VECTOR(8*c_ADDR_LENGTH - 1 downto 0);
data : in STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0));
data : in STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0));
end spi_analyser_pkg;
......@@ -254,8 +254,8 @@ package body spi_analyser_pkg is
procedure set_SPI1 (
signal clk_i : in STD_LOGIC;
signal SPI1 : out r_SPI1;
signal SPI2 : in r_SPI2;
signal SPI1 : out r_SPI1;
signal SPI2 : in r_SPI2;
send_inst : in STD_LOGIC;
send_addr : in STD_LOGIC;
send_data : in STD_LOGIC;
......@@ -274,7 +274,7 @@ package body spi_analyser_pkg is
inst, addr, data);
send_SPI_and_wait(clk_i, SPI1, SPI2,
send_inst, send_addr, send_data, read_mosi,
v_clk_div);
v_clk_div);
end procedure;
......
hdl/spi_master_multifield/test/spi_master_core_tb.vhd
View file @ a9e62b25
--------------------------------------------------------------------------------
-- Company:
-- Company:
-- Engineer:
--
-- Create Date: 12:31:47 06/20/2012
-- Design Name:
-- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name: spi_master_multifield
-- Target Device:
-- Tool versions:
-- Description:
--
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: spi_master_core
--
--
-- Dependencies:
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
......@@ -32,11 +32,11 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.spi_master_pkg.ALL;
use work.spi_analyser_pkg.ALL;
entity spi_master_core_tb is
end spi_master_core_tb;
architecture Behavioral of spi_master_core_tb is
architecture Behavioral of spi_master_core_tb is
component spi_master_core
generic(
......@@ -47,7 +47,7 @@ architecture Behavioral of spi_master_core_tb is
port(
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
inst_i : in STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
......@@ -67,7 +67,7 @@ architecture Behavioral of spi_master_core_tb is
-- Component Declaration for the Unit Under Test (UUT)
signal rst_i : STD_LOGIC := '0';
signal clk_i : STD_LOGIC := '0';
......@@ -80,11 +80,11 @@ architecture Behavioral of spi_master_core_tb is
signal data_i : STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0) := (others => '0');
--Inputs
signal s_SPI0 : r_SPI0;
signal s_SPI0 : r_SPI0;
signal s_SPI0_slv : STD_LOGIC_VECTOR(r_SPI0'a_length - 1 downto 0);
signal s_SPI1 : r_SPI1;
signal s_SPI1 : r_SPI1;
signal s_SPI1_slv : STD_LOGIC_VECTOR(r_SPI1'a_length - 1 downto 0);
signal s_SPI2 : r_SPI2;
signal s_SPI2 : r_SPI2;
signal s_SPI2_slv : STD_LOGIC_VECTOR(r_SPI2'a_length - 1 downto 0);
signal s_spi_mosi : STD_LOGIC;
......@@ -99,8 +99,8 @@ architecture Behavioral of spi_master_core_tb is
signal s_data_check : STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0) :=
(others => '0');
signal s_end_inst_flag : STD_LOGIC;
signal s_end_addr_flag : STD_LOGIC;
signal s_end_inst_flag : STD_LOGIC;
signal s_end_addr_flag : STD_LOGIC;
signal s_end_data_flag : STD_LOGIC;
--Outputs
......@@ -118,9 +118,9 @@ architecture Behavioral of spi_master_core_tb is
begin
s_SPI0_slv <= f_STD_LOGIC_VECTOR(s_SPI0);
s_SPI1_slv <= f_STD_LOGIC_VECTOR(s_SPI1);
s_SPI2 <= f_SPI2(s_SPI2_slv);
s_SPI0_slv <= f_STD_LOGIC_VECTOR(s_SPI0);
s_SPI1_slv <= f_STD_LOGIC_VECTOR(s_SPI1);
s_SPI2 <= f_SPI2(s_SPI2_slv);
-- Instantiate the Unit Under Test (UUT)
uut: spi_master_core port map (
......@@ -139,21 +139,21 @@ begin
spi_cs_n_o => s_spi_cs_n);
tester : spi_analyser port map(
rst_i => s_rst_spi_analyser,
SPI0_i => s_SPI0,
SPI1_i => s_SPI1,
spi_mosi_o => s_spi_mosi,
spi_miso_i => s_spi_miso,
spi_clk_o => s_spi_clk,
spi_cs_n_o => s_spi_cs_n,
inst_check_o => s_inst_check,
addr_check_o => s_addr_check,
rst_i => s_rst_spi_analyser,
SPI0_i => s_SPI0,
SPI1_i => s_SPI1,
spi_mosi_o => s_spi_mosi,
spi_miso_i => s_spi_miso,
spi_clk_o => s_spi_clk,
spi_cs_n_o => s_spi_cs_n,
inst_check_o => s_inst_check,
addr_check_o => s_addr_check,
data_check_o => s_data_check,
end_inst_flag_o => s_end_inst_flag,
end_addr_flag_o => s_end_addr_flag,
end_inst_flag_o => s_end_inst_flag,
end_addr_flag_o => s_end_addr_flag,
end_data_flag_o => s_end_data_flag);
......@@ -171,11 +171,11 @@ begin
procedure init_cond is
begin
inst_i <= (others => '0');
addr_i <= (others => '0');
data_i <= (others => '0');
s_SPI0 <= c_SPI0_default;
s_SPI1 <= c_SPI1_default;
inst_i <= (others => '0');
addr_i <= (others => '0');
data_i <= (others => '0');
s_SPI0 <= c_SPI0_default;
s_SPI1 <= c_SPI1_default;
end procedure;
procedure set_FIFO_contents(
......@@ -209,13 +209,13 @@ begin
s_SPI0, s_SPI1, s_SPI2,
cpol, cpha, clk_div,
inst_length, addr_length, data_length, read_length,
send_inst, send_addr, send_data, read_mosi,
send_inst, send_addr, send_data, read_mosi,
inst_i, addr_i, data_i,
inst, addr, data);
end procedure;
begin
begin
init_cond;
wait until rising_edge(clk_i);
......
hdl/spi_master_multifield/test/spi_slave_writer.vhd
View file @ a9e62b25
--------------------------------------------------------------------------------
-- Company:
-- Company:
-- Engineer:
--
-- Create Date: 12:31:47 06/20/2012
-- Design Name:
-- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name: spi_master_multifield
-- Target Device:
-- Tool versions:
-- Description:
--
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: spi_master_core
--
--
-- Dependencies:
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
......@@ -50,8 +50,8 @@ entity spi_slave_writer is
);
end spi_slave_writer;
architecture Behavioral of spi_slave_writer is
architecture Behavioral of spi_slave_writer is
signal s_spi_count : NATURAL := 0;
signal s_SPI0 : r_SPI0;
......@@ -59,7 +59,7 @@ architecture Behavioral of spi_slave_writer is
signal s_STATUS : r_STATUS;
signal s_spi_clk : STD_LOGIC;
signal s_spi_clk : STD_LOGIC;
signal s_read : STD_LOGIC_VECTOR (g_READ_LENGTH*8 - 1 downto 0)
:= (others => '0');
......@@ -118,10 +118,10 @@ begin
spi_miso_o <= 'Z';
s_end_read_flag <= '0';
else
if rising_edge(spi_clk_i)
if rising_edge(spi_clk_i)
and (write_on_rise(s_SPI0) = '1') then
write_bit;
elsif falling_edge(spi_clk_i)
elsif falling_edge(spi_clk_i)
and (write_on_rise(s_SPI0) = '0') then
write_bit;
end if;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment