Committed last modification on IP cores for remote programming before merging:…

Committed last modification on IP cores for remote programming before merging: ctdah_lib, i2c_slave_wb_master, m25p32, multiboot, spi_master_multifield

Committed last modification on IP cores for remote programming before merging:…
Committed last modification on IP cores for remote programming before merging: ctdah_lib, i2c_slave_wb_master, m25p32, multiboot, spi_master_multifield
a9e62b25 · Carlos Gil Soriano · 078498ba · a9e62b25 · a9e62b25 · a9e62b25
Commit a9e62b25 authored Nov 16, 2012 by Carlos Gil Soriano
21 changed files
--- a/hdl/ctdah_lib/test/.wishbone_driver.vhd.swo
+++ b/hdl/ctdah_lib/test/.wishbone_driver.vhd.swo
--- a/hdl/ctdah_lib/test/.wishbone_driver.vhd.swp
+++ b/hdl/ctdah_lib/test/.wishbone_driver.vhd.swp
--- a/hdl/ctdah_lib/test/.wishbone_driver_pkg.vhd.swp
+++ b/hdl/ctdah_lib/test/.wishbone_driver_pkg.vhd.swp
--- a/hdl/i2c_slave_wb_master/rtl/i2c_bit.vhd
+++ b/hdl/i2c_slave_wb_master/rtl/i2c_bit.vhd
--- a/hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
+++ b/hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
--- a/hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
+++ b/hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
--- a/hdl/i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd
+++ b/hdl/i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd
--- a/hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
+++ b/hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
--- a/hdl/i2c_slave_wb_master/test/i2c_bit_tb.vhd
+++ b/hdl/i2c_slave_wb_master/test/i2c_bit_tb.vhd
--- a/hdl/i2c_slave_wb_master/test/i2c_master_driver.vhd
+++ b/hdl/i2c_slave_wb_master/test/i2c_master_driver.vhd
--- a/hdl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd
+++ b/hdl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd
--- a/hdl/i2c_slave_wb_master/test/i2c_tb_pkg.vhd
+++ b/hdl/i2c_slave_wb_master/test/i2c_tb_pkg.vhd
--- a/hdl/m25p32/rtl/m25p32_core.vhd
+++ b/hdl/m25p32/rtl/m25p32_core.vhd
--- a/hdl/m25p32/rtl/m25p32_pkg.vhd
+++ b/hdl/m25p32/rtl/m25p32_pkg.vhd
--- a/hdl/m25p32/rtl/m25p32_regs.vhd
+++ b/hdl/m25p32/rtl/m25p32_regs.vhd
--- a/hdl/m25p32/rtl/m25p32_top.vhd
+++ b/hdl/m25p32/rtl/m25p32_top.vhd
--- a/hdl/m25p32/test/m25p32_top_tb.vhd
+++ b/hdl/m25p32/test/m25p32_top_tb.vhd
--- a/hdl/m25p32/test/m25p32_top_tb_pkg.vhd
+++ b/hdl/m25p32/test/m25p32_top_tb_pkg.vhd
@@ -39,10 +39,8 @@ package m25p32_top_tb_pkg is
   constant c_WISHBONE_PERIOD   : TIME      := 50 ns;  --! Working at 20MHz

   component m25p32_top is
-      generic(
-              g_WB_ADDR_LENGTH : NATURAL  := c_WORDS_PER_PAGE_BITS + 1);
-      port ( 
-              wb_rst_i       : in  STD_LOGIC;
+      generic(g_WB_ADDR_LENGTH : NATURAL  := c_WORDS_PER_PAGE_BITS + 1);
+      port (wb_rst_i       : in  STD_LOGIC;
            wb_clk         : in  STD_LOGIC;

            wb_we_i        : in  STD_LOGIC;
@@ -62,8 +60,7 @@ package m25p32_top_tb_pkg is
            prom_mosi_o    : out STD_LOGIC;
            prom_cclk_o    : out STD_LOGIC;
            prom_cs0_b_n_o : out STD_LOGIC;
-              prom_din_i     : in  STD_LOGIC
-           );
+            prom_din_i     : in  STD_LOGIC);
   end component;

   procedure wishbone_write (

--- a/hdl/multiboot/doc/Xilinx/xtp059.pdf
+++ b/hdl/multiboot/doc/Xilinx/xtp059.pdf
--- a/hdl/multiboot/test/multiboot_core_tb.vhd
+++ b/hdl/multiboot/test/multiboot_core_tb.vhd
--- a/hdl/multiboot/test/multiboot_top_tb.vhd
+++ b/hdl/multiboot/test/multiboot_top_tb.vhd
 -- TestBench Template
+library IEEE;
+library work;

-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-USE std.textio.ALL;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use STD.TEXTIO.ALL;
+use work.multiboot_pkg.ALL;


-ENTITY multiboot_tb IS
-   END multiboot_tb;
+entity multiboot_tb is
+   end multiboot_tb;

-ARCHITECTURE behavior OF multiboot_tb IS 
+architecture behavior of multiboot_tb is

  -- Component Declaration
   component multiboot_top is
@@ -41,23 +43,7 @@ ARCHITECTURE behavior OF multiboot_tb IS
   signal  wb_rty_o  : STD_LOGIC;
   signal  wb_err_o  : STD_LOGIC;

-   constant wb_clk_period  : TIME := 50 ns; 
-
-   constant OP_FULLMULTIBOOT : STD_LOGIC_VECTOR(3 downto 0) := X"0";
-   constant OP_GENERAL1      : STD_LOGIC_VECTOR(3 downto 0) := X"1";
-   constant OP_GENERAL2      : STD_LOGIC_VECTOR(3 downto 0) := X"2";
-   constant OP_GENERAL3      : STD_LOGIC_VECTOR(3 downto 0) := X"3";
-   constant OP_GENERAL4      : STD_LOGIC_VECTOR(3 downto 0) := X"4";
-   constant OP_IPROG         : STD_LOGIC_VECTOR(3 downto 0) := X"7";
-   constant OP_STAT          : STD_LOGIC_VECTOR(3 downto 0) := X"D";
-
-   constant CTRL0_addr       : STD_LOGIC_VECTOR(3 downto 0) := X"0";
-   constant CTRL1_addr       : STD_LOGIC_VECTOR(3 downto 0) := X"1";
-   constant STAT_addr        : STD_LOGIC_VECTOR(3 downto 0) := X"2";
-   constant GENERAL1_addr    : STD_LOGIC_VECTOR(3 downto 0) := X"4";
-   constant GENERAL2_addr    : STD_LOGIC_VECTOR(3 downto 0) := X"5";
-   constant GENERAL3_addr    : STD_LOGIC_VECTOR(3 downto 0) := X"6";
-   constant GENERAL4_addr    : STD_LOGIC_VECTOR(3 downto 0) := X"7";
+   constant c_WB_CLK_PERIOD  : TIME := 50 ns;

   signal CTRL_data          : STD_LOGIC_VECTOR(31 downto 0);
   signal GENERAL1_data      : STD_LOGIC_VECTOR(31 downto 0);
@@ -66,14 +52,13 @@ ARCHITECTURE behavior OF multiboot_tb IS
   signal GENERAL4_data      : STD_LOGIC_VECTOR(31 downto 0);

   file file_handler    : TEXT;
-   constant log_path    : STRING := "../test/log/multiboot_top_tb.log";
+   constant c_LOG_PATH  : STRING := "../test/log/multiboot_top_tb.log";
   constant sep         : CHARACTER := ht;

 begin

   uut: multiboot_top
-   port map(
-              wb_rst_i  =>  wb_rst_i,  
+   port map(wb_rst_i  =>  wb_rst_i,
            wb_clk    =>  wb_clk,
            wb_we_i   =>  wb_we_i,
            wb_stb_i  =>  wb_stb_i,
@@ -84,15 +69,14 @@ begin
            wb_addr_i =>  wb_addr_i,
            wb_ack_o  =>  wb_ack_o,
            wb_rty_o  =>  wb_rty_o,
-              wb_err_o  =>  wb_err_o 
-           );
+            wb_err_o  =>  wb_err_o);

   wb_clk_process: process
   begin
      wb_clk <= '1';
-      wait for wb_clk_period/2;
+      wait for c_WB_CLK_PERIOD/2;
      wb_clk <= '0';
-      wait for wb_clk_period/2;
+      wait for c_WB_CLK_PERIOD/2;
   end process;


@@ -100,11 +84,11 @@ begin

      procedure rst is
      begin
-         wait for wb_clk_period;
+         wait for c_WB_CLK_PERIOD;
         wb_rst_i  <= '1';
-         wait for wb_clk_period;
+         wait for c_WB_CLK_PERIOD;
         wb_rst_i  <= '0';
-         wait for wb_clk_period*25;
+         wait for c_WB_CLK_PERIOD*25;
      end rst;

      procedure read_wishbone(addr: STD_LOGIC_VECTOR(3 downto 0)) is
@@ -114,7 +98,7 @@ begin
         wb_stb_i    <= '1';
         wb_cyc_i    <= '1';
         wb_addr_i   <= addr;
-         wait for wb_clk_period*3/2;
+         wait for c_WB_CLK_PERIOD*3/2;
         wait until rising_edge(wb_clk);
         wb_we_i     <= '0';
         wb_stb_i    <= '0';
@@ -130,7 +114,7 @@ begin
      wb_cyc_i    <= '1';
      wb_addr_i   <= addr;
      wb_data_i   <= data;
-      wait for wb_clk_period*3/2;
+      wait for c_WB_CLK_PERIOD*3/2;
      wait until rising_edge(wb_clk);
      wb_we_i     <= '0';
      wb_stb_i    <= '0';
@@ -172,11 +156,11 @@ begin
   variable header_line_buffer : LINE;

 begin
-   file_open(file_handler, log_path, WRITE_MODE);
+   file_open(file_handler, c_LOG_PATH, WRITE_MODE);
   write(header_line_buffer, string'("Test ID"&sep&"Status"&sep&"Description"));
   writeline(file_handler, header_line_buffer);

-   wait for 2*wb_clk_period;
+   wait for 2*c_WB_CLK_PERIOD;
   rst;
   GENERAL1_data <= (others => '0');
   GENERAL2_data <= (others => '0');
@@ -184,7 +168,7 @@ begin
   GENERAL4_data <= (others => '0');


-   wait for 2*wb_clk_period;
+   wait for 2*c_WB_CLK_PERIOD;
   read_wishbone(CTRL_addr);
      assert32_to_file(wb_data_o, X"00000000","0x0","CTRL register initialization");
   read_wishbone(STAT_addr);