Skip to content

C
Conv TTL Blocking
Commit af60d66d authored by gilsoriano's avatar gilsoriano
Browse files
Options

m25p32 looks great now! 

- Synthesizable. Simulations reveals some little bugs in SPI cs_n pin and no loading of the registers.
- The VHDL syntax uses extensively type record entities, translation functions between IOs and records, attributes for defined type records...
- m25p32_core.vhd has now a package for itself m25p32_core_pkg.vhd. This file contains procedures for all the chain of spi instruction to write and read from the memory through SPI. It needs to add more cases.

It still needs work to do.
parent e88dbb88
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1262 additions and 183 deletions
hdl/m25p32/rtl/m25p32_buff.vhd 0 → 100755
View file @ af60d66d
---------------------------------------------------------------------------------
-- Company: CERN, BE-CO
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 08:26:02 06/18/2012
-- Design Name: m25p32 wishbone access
-- Module Name: m25p32_buff - Behavioral
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: Page buffers for storing temporal pages before/after
-- accessing the m25p32
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.m25p32_pkg.ALL;
use work.ctdah_pkg.ALL;
use work.spi_master_pkg.ALL;
entity m25p32_buff is
generic(
g_BUFFER_SIZE : NATURAL := c_NUMBER_OF_BUFFERS;
g_inst_width : NATURAL := c_INST_LENGTH;
g_addr_width : NATURAL := c_ADDR_LENGTH;
g_data_width : NATURAL := c_PAGE_SIZE
); port(
rst_i : in STD_LOGIC;
clk : in STD_LOGIC;
inst_i : in STD_LOGIC_VECTOR (8*g_inst_width - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR (8*g_addr_width - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (31 downto 0);
inst_db_o : out STD_LOGIC_VECTOR (g_BUFFER_SIZE*8*g_inst_width - 1 downto 0);
addr_db_o : out STD_LOGIC_VECTOR (g_BUFFER_SIZE*8*g_addr_width - 1 downto 0);
data_db_o : out STD_LOGIC_VECTOR (g_BUFFER_SIZE*8*g_data_width - 1 downto 0);
CTR1_i : in STD_LOGIC_VECTOR (r_CTR1'a_length - 1 downto 0);
DBUF_o : out STD_LOGIC_VECTOR (r_DBUF'a_length - 1 downto 0)
);
end m25p32_buff;
architecture Behavioral of m25p32_buff is
signal s_CTR1 : r_CTR1;
signal s_DBUF : r_DBUF;
signal s_push : STD_LOGIC_VECTOR (c_NUMBER_OF_BUFFERS - 1 downto 0);
signal s_pull : STD_LOGIC_VECTOR (c_NUMBER_OF_BUFFERS - 1 downto 0);
signal s_active_buffer : STD_LOGIC_VECTOR(1 downto 0);
begin
s_CTR1 <= f_CTR1(CTR1_i);
DBUF_o(23 downto 0) <= f_STD_LOGIC_VECTOR(s_DBUF(0));
DBUF_o(47 downto 24) <= f_STD_LOGIC_VECTOR(s_DBUF(1));
INST_BUFF: for I in 0 to (c_NUMBER_OF_BUFFERS - 1) generate
inst_fifo: FIFO_simple
generic map(
g_data_width => 8)
port map(
reg_i => inst_i,
clk => clk,
push => s_push(I),
flush => rst_i,
reg_o => inst_db_o(8*g_inst_width*(I+1) - 1 downto
8*g_inst_width*I)
);
end generate INST_BUFF;
INST_ADDR: for I in 0 to c_NUMBER_OF_BUFFERS - 1 generate
addr_fifo: FIFO_simple
generic map(
g_data_width => 24)
port map(
reg_i => addr_i,
clk => clk,
push => s_push(I),
flush => rst_i,
reg_o => addr_db_o(8*g_addr_width*(I+1) - 1 downto
8*g_addr_width*I)
);
end generate INST_ADDR;
INST_DATA: for I in 0 to c_NUMBER_OF_BUFFERS - 1 generate
data_fifo_i2c: FIFO_stack
generic map(
g_data_width => 32, g_stack_depth => c_PAGE_SIZE*8/32)
port map(
reg_i => data_i,
clk => clk,
push => s_push(I),
flush => rst_i,
reg_o => data_db_o(8*g_data_width*(I+1) - 1 downto
8*g_data_width*I)
);
end generate INST_DATA;
p_write_buffer: process(clk)
begin
if rising_edge (clk) then
if rst_i = '1' then
s_DBUF(0) <= c_BUF_default;
s_DBUF(1) <= c_BUF_default;
s_push <= (others => '0');
s_pull <= (others => '0');
elsif s_CTR1.WRA = '1' then
s_push <= (others => '0');
case s_CTR1.ABF is
when "01" =>
s_push(0) <= '1';
s_DBUF(0).PAGE <= unsigned(addr_i(15 downto 8));
s_DBUF(0).SECT <= unsigned(addr_i(23 downto 16));
when "10" =>
s_push(1) <= '1';
s_DBUF(1).PAGE <= unsigned(addr_i(15 downto 8));
s_DBUF(1).SECT <= unsigned(addr_i(23 downto 16));
when others =>
end case;
else
end if;
else
end if;
end process;
end Behavioral;
hdl/m25p32/rtl/m25p32_core.vhd
View file @ af60d66d
......@@ -21,66 +21,95 @@
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.m25p32_pkg.ALL;
use work.m25p32_core_pkg.ALL;
use work.spi_master_pkg.ALL;
entity m25p32_core is
generic(g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
mosi_o : out STD_LOGIC;
miso_i : in STD_LOGIC;
sclk_o : out STD_LOGIC;
ss_n_o : out STD_LOGIC;
mosi_o : out STD_LOGIC;
miso_i : in STD_LOGIC;
sclk_o : out STD_LOGIC;
ss_n_o : out STD_LOGIC;
CTR0_o : out STD_LOGIC_VECTOR(7 downto 0);
FMOH_i : in STD_LOGIC_VECTOR(31 downto 0)
inst_db_i : in STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_db_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_db_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
CTR0_o : out STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
FMOH_i : in STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0)
);
end m25p32_core;
architecture Behavioral of m25p32_core is
component spi_master_core is
generic(
g_inst_width := 1;
g_addr_width := 3;
g_data_width := 256
); port(
rst_i : in STD_LOGIC;
clk : in STD_LOGIC
inst_i : in STD_LOGIC_VECTOR (8*g_inst_width - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR (8*g_addr_width - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*g_data_width - 1 downto 0);
push_inst_i : in STD_LOGIC;
push_addr_i : in STD_LOGIC;
push_data_i : in STD_LOGIC;
signal MEM_fsm : t_m25p32_fsm;
signal MEM_fsm_d0 : t_m25p32_fsm;
signal s_CTR0 : r_CTR0;
signal s_CTR1 : r_CTR1;
signal s_CTR1_slv : STD_LOGIC_VECTOR (r_CTR1'a_length - 1 downto 0);
signal s_FMOH : r_FMOH;
data_i : in STD_LOGIC_VECTOR (8*g_data_width - 1 downto 0);
SPI0_i : in STD_LOGIC_VECTOR (31 downto 0)
);
end component;
--! Registers from spi_master_pkg
signal s_SPI0 : r_SPI0;
signal s_SPI0_slv : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI1 : r_SPI1;
signal s_SPI1_slv : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI2 : r_SPI2;
signal s_SPI2_slv : STD_LOGIC_VECTOR (15 downto 0);
signal s_wr_rqt : STD_LOGIC;
type t_m25p32_fsm is (S0_IDLE, S1_WREN, S2_SPI_WRITE, S3_DEL_PROG_CYCLE, S4_WRDI, Q1_ERROR);
begin
signal MEM_fsm : t_m25p32_fsm;
CTR0_o <= f_STD_LOGIC_VECTOR(s_CTR0);
s_CTR1 <= f_CTR1(s_CTR1_slv);
signal s_CTR0 : r_CTR0;
signal s_FMOH : r_FMOH;
s_FMOH <= f_FMOH(FMOH_i);
s_SPI0_slv <= f_STD_LOGIC_VECTOR(s_SPI0);
s_SPI1_slv <= f_STD_LOGIC_VECTOR(s_SPI1);
s_SPI2 <= f_SPI2(s_SPI2_slv);
inst_spi_master_core: spi_master_core
generic map(
g_inst_length => c_INST_LENGTH,
g_addr_length => c_ADDR_LENGTH,
g_data_length => c_DATA_LENGTH
) port map(
rst_i => wb_rst_i,
clk_i => wb_clk,
begin
inst_i => inst_db_i,
addr_i => addr_db_i,
data_i => data_db_i,
SPI0_i => s_SPI0_slv,
SPI1_i => s_SPI1_slv,
SPI2_o => s_SPI2_slv,
spi_mosi_o => mosi_o,
spi_miso_i => miso_i,
spi_clk_o => sclk_o,
spi_cs_n_o => ss_n_o
);
s_FMOH <= f_FMOH(FMOH_i);
CTR0_o <= f_STD_LOGIC_VECTOR(s_CTR0);
p_out: process (wb_clk)
begin
if rising_edge(wb_clk) then
if wb_rst_i = '1' then
s_CTR0 <= c_CTR0_default;
s_CTR0 <= c_CTR0_default;
else
MEM_fsm_d0 <= MEM_fsm;
if s_FMOH.OPP = '1' then
case s_FMOH.OP is
when ERS =>
......@@ -92,7 +121,7 @@ begin
when S2_SPI_WRITE =>
when S3_DEL_PROG_CYCLE =>
when S4_WRDI =>
when Q1_ERROR =>
when Q0_ERROR =>
s_CTR0.OPA <= '1';
s_CTR0.OPF <= '1';
when others =>
......@@ -104,10 +133,9 @@ begin
when S2_SPI_WRITE =>
when S3_DEL_PROG_CYCLE =>
when S4_WRDI =>
when Q1_ERROR =>
when Q0_ERROR =>
when others =>
end case;
when WRP =>
case MEM_fsm is
when S0_IDLE =>
......@@ -115,46 +143,28 @@ begin
when S2_SPI_WRITE =>
when S3_DEL_PROG_CYCLE =>
when S4_WRDI =>
when Q1_ERROR =>
when Q0_ERROR =>
when others =>
end case;
when others =>
end case;
else
s_CTR0.OPA <= '0';
s_CTR0.OPF <= '0';
end if;
end if;
else
end if;
end process;
p_ERS_fsm: process (wb_clk)
begin
if rising_edge(wb_clk) then
if wb_rst_i = '1' then
MEM_fsm <= S0_IDLE;
else
if s_FMOH.OPP = '1' and s_CTR0.OPA = '0' then
case s_FMOH.OP is
when ERS =>
when RDSR =>
case MEM_fsm is
when S0_IDLE =>
when S1_WREN =>
when S2_SPI_WRITE =>
when S3_DEL_PROG_CYCLE =>
when S4_WRDI =>
when Q1_ERROR =>
when Q0_ERROR =>
when others =>
end case;
when RDP =>
when WRP =>
when WRSR =>
proc_WRSR_fsm (s_CTR0,
s_SPI0, s_SPI1, s_SPI2,
MEM_fsm, MEM_fsm_d0);
when others =>
end case;
else
s_CTR0.OPA <= '0';
s_CTR0.OPF <= '0';
end if;
end if;
else
......
hdl/m25p32/rtl/m25p32_core_pkg.vhd 0 → 100755
View file @ af60d66d
This diff is collapsed.
hdl/m25p32/rtl/m25p32_pkg.vhd
View file @ af60d66d
This diff is collapsed.
hdl/m25p32/rtl/m25p32_regs.vhd
View file @ af60d66d
......@@ -21,9 +21,16 @@
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
--! Insert this line for conversion functions
use IEEE.NUMERIC_STD.ALL;
use work.m25p32_pkg.ALL;
use work.spi_master_pkg.ALL;
entity m25p32_regs is
generic(
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
......@@ -39,15 +46,35 @@ entity m25p32_regs is
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
CTR0_i : in STD_LOGIC_VECTOR (7 downto 0);
FMOH_o : out STD_LOGIC_VECTOR (31 downto 0)
inst_db_o : out STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_db_o : out STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_db_o : out STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
FMOH_o : out STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0)
);
end m25p32_regs;
architecture Behavioral of m25p32_regs is
signal s_CTR0 : r_CTR0;
signal s_CTR1 : r_CTR1;
signal s_CTR1_slv : STD_LOGIC_VECTOR (r_CTR1'a_length - 1 downto 0);
signal s_FMOH : r_FMOH;
signal s_SR_m25p32 : r_SR_m25p32;
signal s_DBUF : r_DBUF;
signal s_DBUF_slv : STD_LOGIC_VECTOR (r_DBUF'a_length - 1 downto 0);
signal s_inst_i : STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
signal s_addr_i : STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
signal s_data_i : STD_LOGIC_VECTOR (31 downto 0);
signal s_inst_db_o : STD_LOGIC_VECTOR (c_NUMBER_OF_BUFFERS*8*c_INST_LENGTH - 1
downto 0);
signal s_addr_db_o : STD_LOGIC_VECTOR (c_NUMBER_OF_BUFFERS*8*c_ADDR_LENGTH - 1
downto 0);
signal s_data_db_o : STD_LOGIC_VECTOR (c_NUMBER_OF_BUFFERS*8*c_DATA_LENGTH - 1
downto 0);
signal s_wb_ack_o : STD_LOGIC;
signal s_wb_rty_o : STD_LOGIC;
......@@ -55,15 +82,65 @@ architecture Behavioral of m25p32_regs is
begin
wb_ack_o <= s_wb_ack_o;
wb_rty_o <= s_wb_rty_o;
wb_err_o <= s_wb_err_o;
wb_ack_o <= s_wb_ack_o;
wb_rty_o <= s_wb_rty_o;
wb_err_o <= s_wb_err_o;
s_CTR0 <= f_CTR0(CTR0_i);
s_CTR1_slv <= f_STD_LOGIC_VECTOR(s_CTR1);
FMOH_o <= f_STD_LOGIC_VECTOR(s_FMOH);
s_DBUF(0) <= f_BUF(s_DBUF_slv( r_BUF'a_length - 1 downto 0));
s_DBUF(1) <= f_BUF(s_DBUF_slv(2*r_BUF'a_length - 1 downto
r_BUF'a_length ));
--! It needs to be multiplexed
inst_db_o <= s_inst_db_o(8*c_INST_LENGTH - 1 downto 0)
when (s_CTR1.ABF = "01") else
s_inst_db_o(2*8*c_INST_LENGTH - 1 downto 8*c_INST_LENGTH)
when (s_CTR1.ABF = "10") else
(others => '0');
addr_db_o <= s_addr_db_o(8*c_ADDR_LENGTH - 1 downto 0)
when (s_CTR1.ABF = "01") else
s_addr_db_o(2*8*c_ADDR_LENGTH - 1 downto 8*c_ADDR_LENGTH)
when (s_CTR1.ABF = "10") else
(others => '0');
data_db_o <= s_data_db_o(8*c_DATA_LENGTH - 1 downto 0)
when (s_CTR1.ABF = "01") else
s_data_db_o(2*8*c_DATA_LENGTH - 1 downto 8*c_DATA_LENGTH)
when (s_CTR1.ABF = "10") else
(others => '0');
inst_tbuff : m25p32_buff
generic map (
g_BUFFER_SIZE => c_NUMBER_OF_BUFFERS,
g_inst_width => c_INST_LENGTH,
g_addr_width => c_ADDR_LENGTH,
g_data_width => c_DATA_LENGTH
) port map(
rst_i => wb_rst_i,
clk => wb_clk,
inst_i => s_inst_i,
addr_i => s_addr_i,
data_i => s_data_i,
inst_db_o => s_inst_db_o,
addr_db_o => s_addr_db_o,
data_db_o => s_data_db_o,
CTR1_i => s_CTR1_slv,
DBUF_o => s_DBUF_slv
);
p_wbslave: process (wb_clk)
begin
if rising_edge(wb_clk) then
if wb_rst_i = '1' then
s_CTR0 <= c_CTR0_default;
s_CTR1 <= c_CTR1_default;
s_FMOH <= c_FMOH_default;
s_wb_ack_o <= '0';
s_wb_rty_o <= '0';
......@@ -80,20 +157,36 @@ begin
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
else
s_wb_ack_o <= '1';
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
case wb_we_i is
when '1' =>
case wb_addr_i(3 downto 0) is
when c_FMOH_addr =>
if s_FMOH.OPP = '0' then
s_FMOH <= f_FMOH(wb_data_i);
s_wb_ack_o <= '1';
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
else
s_wb_ack_o <= '0';
s_wb_rty_o <= '0';
s_wb_err_o <= '1';
end if;
when c_ADDR_BUF_addr =>
s_addr_i <= wb_data_i(8*(c_ADDR_LENGTH) - 1
downto 0);
when c_DATA_BUF_addr =>
s_CTR1.CNTA <= to_unsigned(
to_integer(s_CTR1.CNTA) + 1,
s_CTR1.CNTA'length);
if s_CTR1.CNTA = c_PAGE_SIZE/4 - 1 then
s_CTR1.CNTA <= to_unsigned(0,
s_CTR1.CNTA'length);
end if;
s_CTR1.ABF <= f_ACTIVE_BUFFER(s_CTR1);
s_data_i <= wb_data_i;
when c_SR_m25p32_addr =>
s_SR_m25p32 <= f_SR_m25p32(wb_data_i(
r_SR_m25p32'a_length-1 downto 0));
when others =>
s_wb_ack_o <= '0';
s_wb_rty_o <= '0';
......@@ -101,18 +194,24 @@ begin
end case;
when others =>
case wb_addr_i is
when c_CTR0_addr =>
wb_data_o(7 downto 0) <= f_STD_LOGIC_VECTOR(s_CTR0);
wb_data_o(31 downto 8) <= (others => '0');
s_wb_ack_o <= '1';
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
when c_FMOH_addr =>
when c_CTR0_addr =>
wb_data_o(r_CTR0'a_length - 1 downto 0)
<= f_STD_LOGIC_VECTOR(s_CTR0);
wb_data_o(31 downto r_CTR0'a_length)
<= (others => '0');
when c_CTR1_addr =>
wb_data_o(r_CTR1'a_length - 1 downto 0)
<= s_CTR1_slv;
wb_data_o(31 downto r_CTR1'a_length)
<= (others => '0');
when c_FMOH_addr =>
wb_data_o <= f_STD_LOGIC_VECTOR(s_FMOH);
s_wb_ack_o <= '1';
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
when others =>
when c_SR_m25p32_addr =>
wb_data_o(r_SR_m25p32'a_length - 1 downto 0)
<= f_STD_LOGIC_VECTOR(s_SR_m25p32);
wb_data_o(31 downto r_SR_m25p32'a_length)
<= (others => '0');
when others =>
s_wb_ack_o <= '0';
s_wb_rty_o <= '0';
s_wb_err_o <= '1';
......
hdl/m25p32/rtl/m25p32_top.vhd
View file @ af60d66d
......@@ -21,6 +21,7 @@ library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use work.m25p32_pkg.ALL;
use work.spi_master_pkg.ALL;
entity m25p32_top is
port (
......@@ -30,10 +31,10 @@ entity m25p32_top is
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
......@@ -47,25 +48,50 @@ end m25p32_top;
architecture Behavioral of m25p32_top is
signal s_CTR0 : STD_LOGIC_VECTOR(7 downto 0);
signal s_FMOH : STD_LOGIC_VECTOR(31 downto 0);
constant c_CTR0_length : INTEGER := f_STD_LOGIC_VECTOR(
c_CTR0_default)'length;
constant c_FMOH_length : INTEGER := f_STD_LOGIC_VECTOR(
c_FMOH_default)'length;
constant c_DBUF_length : INTEGER := c_NUMBER_OF_BUFFERS *
f_STD_LOGIC_VECTOR(
c_BUF_default)'length;
constant c_SR_m25p32_length : INTEGER := f_STD_LOGIC_VECTOR(
c_SR_m25p32_default)'length;
signal s_CTR0 : STD_LOGIC_VECTOR (c_CTR0_length - 1 downto 0);
signal s_FMOH : STD_LOGIC_VECTOR (c_FMOH_length - 1 downto 0);
signal s_DBUF : STD_LOGIC_VECTOR (c_DBUF_length - 1 downto 0);
signal s_inst_db : STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
signal s_addr_db : STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
signal s_data_db : STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);
-- type t_operations is (x, ERS, RDP, WRP, RDSR, WRSR);
component m25p32_core is
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
mosi_o : out STD_LOGIC;
miso_i : in STD_LOGIC;
sclk_o : out STD_LOGIC;
ss_n_o : out STD_LOGIC;
mosi_o : out STD_LOGIC;
miso_i : in STD_LOGIC;
sclk_o : out STD_LOGIC;
ss_n_o : out STD_LOGIC;
inst_db_i : in STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
addr_db_i : in STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
data_db_i : in STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);
CTR0_o : out STD_LOGIC_VECTOR (7 downto 0);
FMOH_i : in STD_LOGIC_VECTOR (31 downto 0)
CTR0_o : out STD_LOGIC_VECTOR(r_CTR0'a_length - 1 downto 0);
FMOH_i : in STD_LOGIC_VECTOR(r_FMOH'a_length - 1 downto 0)
);
end component;
component m25p32_regs is
generic(
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
......@@ -81,8 +107,12 @@ architecture Behavioral of m25p32_top is
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
CTR0_i : in STD_LOGIC_VECTOR (7 downto 0);
FMOH_o : out STD_LOGIC_VECTOR (31 downto 0)
inst_db_o : out STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_db_o : out STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_db_o : out STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
FMOH_o : out STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0)
);
end component;
......@@ -98,6 +128,10 @@ begin
sclk_o => prom_cclk_o,
ss_n_o => prom_cs0_b_n_o,
inst_db_i => s_inst_db,
addr_db_i => s_addr_db,
data_db_i => s_data_db,
CTR0_o => s_CTR0,
FMOH_i => s_FMOH
);
......@@ -118,6 +152,10 @@ begin
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
inst_db_o => s_inst_db,
addr_db_o => s_addr_db,
data_db_o => s_data_db,
CTR0_i => s_CTR0,
FMOH_o => s_FMOH
);
......
hdl/m25p32/test/m25p32_top_tb.vhd 0 → 100755
View file @ af60d66d
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 01:22:27 07/26/2012
-- Design Name: m25p32 top_tp level
-- Module Name: m25p32_top_tp - RTL
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.m25p32_pkg.ALL;
entity m25p32_top_tb is
end m25p32_top_tb;
architecture Behavioral of m25p32_top_tb is
component m25p32_top is
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
prom_mosi_o : out STD_LOGIC;
prom_cclk_o : out STD_LOGIC;
prom_cs0_b_n_o : out STD_LOGIC;
prom_din_i : in STD_LOGIC
);
end component;
signal wb_rst_i : STD_LOGIC;
signal wb_clk : STD_LOGIC;
signal wb_we_i : STD_LOGIC;
signal wb_stb_i : STD_LOGIC;
signal wb_cyc_i : STD_LOGIC;
signal wb_sel_i : STD_LOGIC_VECTOR (3 downto 0);
signal wb_data_i : STD_LOGIC_VECTOR (31 downto 0);
signal wb_data_o : STD_LOGIC_VECTOR (31 downto 0);
signal wb_addr_i : STD_LOGIC_VECTOR (3 downto 0);
signal wb_ack_o : STD_LOGIC;
signal wb_rty_o : STD_LOGIC;
signal wb_err_o : STD_LOGIC;
signal prom_mosi_o : STD_LOGIC;
signal prom_cclk_o : STD_LOGIC;
signal prom_cs0_b_n_o : STD_LOGIC;
signal prom_din_i : STD_LOGIC;
signal s_FMOH : r_FMOH;
signal s_FMOH_slv : STD_LOGIC_VECTOR (31 downto 0);
begin
s_FMOH_slv <= f_STD_LOGIC_VECTOR(s_FMOH);
uut: m25p32_top port map(
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => wb_we_i ,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
prom_mosi_o => prom_mosi_o,
prom_cclk_o => prom_cclk_o,
prom_cs0_b_n_o => prom_cs0_b_n_o,
prom_din_i => prom_din_i);
clk_i_process :process
begin
wb_clk <= '0';
wait for c_WISHBONE_PERIOD/2;
wb_clk <= '1';
wait for c_WISHBONE_PERIOD/2;
end process;
m25p32_access : process
procedure init_cond is
begin
--! We reset the wishbone bus
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
wb_sel_i <= (others => '0');
wb_data_i <= (others => '0');
wb_addr_i <= (others => '0');
--! And also the miso line
prom_din_i <= '0';
end procedure;
procedure set_FMOH (m25p32_instruction: t_operations;
page : INTEGER;
sector : INTEGER) is
variable v_page : STD_LOGIC_VECTOR (23 downto 16);
variable v_sector : STD_LOGIC_VECTOR (29 downto 24);
begin
v_page := std_logic_vector(to_unsigned(page, 8));
v_sector := std_logic_vector(to_unsigned(sector, 6));
s_FMOH.OP <= m25p32_instruction;
s_FMOH.OPP <= '1';
case m25p32_instruction is
when ERS =>
s_FMOH.PG <= v_page;
s_FMOH.SCT <= v_sector;
when RDP =>
s_FMOH.PG <= v_page;
s_FMOH.SCT <= v_sector;
when WRP =>
s_FMOH.PG <= v_page;
s_FMOH.SCT <= v_sector;
-- when RDSR =>
-- when WRSR =>
when others =>
end case;
end procedure;
procedure wishbone_write (reg_data: STD_LOGIC_VECTOR(31 downto 0);
reg_addr: STD_LOGIC_VECTOR(3 downto 0)) is
begin
wait until rising_edge(wb_clk);
wb_we_i <= '1';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_sel_i <= X"F";
wb_data_i <= reg_data;
wb_addr_i <= reg_addr;
wait until rising_edge(wb_clk);
--! Here we wait for the ack and keep till operation is finished
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
wb_sel_i <= X"F";
end procedure;
procedure wishbone_read (reg_data: STD_LOGIC_VECTOR(31 downto 0);
reg_addr: STD_LOGIC_VECTOR(3 downto 0)) is
begin
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_sel_i <= X"F";
wb_data_i <= reg_data;
wb_addr_i <= reg_addr;
wait until rising_edge(wb_clk);
--! Here we wait for the ack and keep till operation is finished
wait until rising_edge(wb_clk);
wb_stb_i <= '0';
wb_cyc_i <= '0';
wb_sel_i <= X"F";
end procedure;
procedure send_instruction is
begin
wishbone_write(s_FMOH_slv, c_FMOH_addr);
end procedure;
begin
--! This line is cosmetic because this register is not loaded in the
--! core until a call to send_instruction procedure is issued.
s_FMOH <= c_FMOH_default;
--! First we perform the reset to the module
init_cond;
wb_rst_i <= '1';
wait for c_WISHBONE_PERIOD*10;
wb_rst_i <= '0';
wait for c_WISHBONE_PERIOD*10;
--! Test schema:
--! 1.-
set_FMOH(WRSR,
0,
0);
send_instruction;
wait;
end process m25p32_access;
end;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment