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@misc{i2c-spec,
title = {{I2C Bus Specification, version 2.1}},
month = jan,
year = 2000,
note = "{\url{http://www.nxp.com/documents/other/39340011.pdf}}"
}
\ No newline at end of file
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FILE=vme64x_i2c
all:
pdflatex -synctex=1 -interaction=nonstopmode *.tex
bibtex *.aux
pdflatex -synctex=1 -interaction=nonstopmode *.tex
pdflatex -synctex=1 -interaction=nonstopmode *.tex
evince $(FILE).pdf &
clean:
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
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@misc{sysmon-i2c,
author = "{ELMA}",
title = {{Access to board data using SNMP and I2C}},
howpublished = {\url{http://www.ohwr.org/documents/227}}
}
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%==============================================================================
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{rotating}
\usepackage{multirow}
\usepackage{color}
%==============================================================================
% Start of document
%==============================================================================
\begin{document}
\title{VME64x I$^2$C to Wishbone bridge}
\author
{
Theodor-Adrian Stana \\
CERN, BE-CO-HT \\
}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}
\begin{center}
\includegraphics[scale=.25,keepaspectratio]{fig/cern-logo.png}
\end{center}
\end{figure}
% Break page
\pagebreak
% Generate TOC and pagebreak after it
\tableofcontents
\pagebreak
%==============================================================================
% SEC: Intro
%==============================================================================
\section{Introduction}
\label{sec:intro}
This document describes the \textit{vme64x\_i2c} module, an I$^2$C to Wishbone
bridge for the VME64x crates. The module implements an I$^2$C slave and translates
the protocol defined by ELMA in \cite{sysmon-i2c} into Wishbone accesses to a
Wishbone slave device of choice.
%==============================================================================
% SEC: Protocol
%==============================================================================
\section{ELMA I$^2$C Protocol}
\label{sec:elma-i2c}
\textcolor{red}{WRITE THIS THING}
%==============================================================================
% SEC: Implem
%==============================================================================
\section{Implementation}
\label{sec:implem}
In order to perform low-level I$^2$C transfers, the \textit{i2c\_slave} module
is instantiated and used within the \textit{vme64x\_i2c} module. The outputs of
the \textit{i2c\_slave} module \textcolor{red}{REFERENCE?} are used as controls for an eight-state
finite state machine (FSM), shown in Table~\ref{tbl:state-mach}. When the
\textit{i2c\_slave} module finishes a transfer (signaled by a \textit{done\_p\_o}
pulse), the status is checked and if it is as expected (e.g., a \textit{address good}
in the \textit{ST\_IDLE} state), the FSM advances to the next state.
\begin{table}[h]
\caption{\textit{vme64x\_i2c} state machine}
\label{tbl:state-mach}
\centerline
{
\begin{tabular}{l p{.65\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{State}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
ST\_IDLE & Wait for the \textit{i2c\_slave} module to receive the I$^2$C
address and go to \textit{ST\_WB\_ADR}. The starting value at the
\textit{op\_o} output of the \textit{i2c\_slave} module is stored
for checking in \textit{ST\_OP} \\
ST\_WB\_ADR & Shift in the two address bytes sent via I$^2$C and go to
\textit{ST\_SIM\_WB\_TRANSF} \\
ST\_SIM\_WB\_TRANSF & Start a Wishbone read transfer from address received in previous
state and go to \textit{ST\_OP} if Wishbone address exists (Wishbone
\textit{ack} received, or \textit{ST\_IDLE} otherwise (Wishbone \textit{err}
received) \\
ST\_OP & Check the \textit{op\_o} output of the \textit{i2c\_slave} module.
If different from the value at the start, go to \textit{ST\_SYSMON\_RD\_WB} state
(SysMon is reading from CONV-TTL-BLO), otherwise continue shifting
in bytes (SysMon writing to CONV-TTL-BLO) \\
ST\_SYSMON\_WR & Continue reading up to four bytes sent by the SysMon and go to
\textit{ST\_SYSMON\_WR\_WB}\\
ST\_SYSMON\_WR\_WB & Perform a Wishbone write transfer to the register with the address obtained in
\textit{ST\_WB\_ADR} \\
ST\_SYSMON\_RD\_WB & Perform a Wishbone read transfer from the address obtained in
\textit{ST\_WB\_ADR} and go to \textit{ST\_SYSMON\_RD} \\
ST\_SYSMON\_RD & Shift out the four bytes of the Wishbone register when the \textit{i2c\_slave}
module successfully finishes a write \\
\hline
\end{tabular}
}
\end{table}
It should be noted that where the SysMon appears in the state names, it indicates
what the SysMon action is. That is, if the state of the FSM is \textit{ST\_SYSMON\_WR},
this means the SysMon is writing and the CONV-TTL-BLO is reading.
To better understand how the FSM operates, \textcolor{red}{BYTE ORDER FIGURES} can be consulted,
where each I$^2$C transfer is correlated to the current state of the FSM.
When reading from the SysMon, the \textit{vme64x\_i2c} module will wait in the
\textit{ST\_IDLE} state while the I$^2$C address is sent, then go to the
\textit{ST\_WB\_ADR} state to shift in the address. A Wishbone transfer is
simulated and if the address exists (a Wishbone \textit{ack} is received),
the first byte is shifted in while in the \textit{ST\_OP} state, followed
by the next three bytes while in the \textit{ST\_SYSMON\_WR} state. After that,
the register is written to in the \textit{ST\_SYSMON\_WR\_WB} state.
When writing to the SysMon, the first few steps are the same as for reading from it.
The address is shifted in and checked in the Wishbone transfer simulation state.
In the case of a SysMon reading from a board, however, the I$^2$C transfer
is restarted and the order is reversed (SysMon starts reading). Thus, while in
\textit{ST\_OP}, the FSM detects a different value of \textit{op\_o} and goes into
the \textit{ST\_SYSMON\_RD\_WB} state. Here, an actual Wishbone read transfer is
executed, the value of the register is read and sent via I$^2$C in the\\
\textit{ST\_SYSMON\_RD} state.
%==============================================================================
% Bibliography
%==============================================================================
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{vme64x_i2c}
\end{document}
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