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Conv TTL Blocking
Commit c33673ec authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Add PTS P2 Tester Board files. Working TTL p-rep. 

The design files for the tester board are added as part of this commit.
Additional changes to make the TTL pulse repetition test are also part
of the commit. These changes include adding a pulse_gen on CH10 and
additional changes to pulse repeaters, such as enable inputs, etc.
parent 00387791
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Showing with 1742 additions and 143 deletions
hdl/old_rep_test/Manifest.py 0 → 100644
View file @ c33673ec
modules = {"local" : "rtl"}
hdl/old_rep_test/rtl/pulse_gen.vhd
View file @ c33673ec
......@@ -49,6 +49,7 @@ entity pulse_gen is
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
pulse_o : out std_logic
);
end entity pulse_gen;
......@@ -56,10 +57,6 @@ end entity pulse_gen;
architecture behav of pulse_gen is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Function and procedure declarations
--============================================================================
......@@ -73,19 +70,10 @@ architecture behav of pulse_gen is
return(63);
end function f_log2_size;
--============================================================================
-- Constant declarations
--============================================================================
--============================================================================
-- Component declarations
--============================================================================
--============================================================================
-- Signal declarations
--============================================================================
signal freq_cnt : unsigned(f_log2_size(g_freq)-1 downto 0);
signal pulse : std_logic;
--==============================================================================
-- architecture begin
......@@ -93,21 +81,19 @@ architecture behav of pulse_gen is
begin
--============================================================================
-- I/O logic
-- Pulse generation logic
--============================================================================
pulse_o <= pulse;
p_gen_pulse: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
freq_cnt <= (others => '0');
pulse <= '0';
else
pulse_o <= '0';
elsif (en_i = '1') then
freq_cnt <= freq_cnt + 1;
pulse <= '0';
pulse_o <= '0';
if (freq_cnt < g_pwidth) then
pulse <= '1';
pulse_o <= '1';
elsif (freq_cnt = g_freq-1) then
freq_cnt <= (others => '0');
end if;
......
hdl/pts/syn/conv_ttl_blo_v2.gise
View file @ c33673ec
......@@ -72,35 +72,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1366387848">
<transform xil_pn:end_ts="1366636044" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1366636044">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1366387848">
<transform xil_pn:end_ts="1366636044" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1366636044">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1366387848">
<transform xil_pn:end_ts="1366636044" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1366636044">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1366387848">
<transform xil_pn:end_ts="1366636045" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1366636044">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1366387848">
<transform xil_pn:end_ts="1366636045" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1366636045">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1366387848">
<transform xil_pn:end_ts="1366636045" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1366636045">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1366387848">
<transform xil_pn:end_ts="1366636045" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1366636045">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366387909" xil_pn:in_ck="7459507639272444710" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1366387848">
<transform xil_pn:end_ts="1366636105" xil_pn:in_ck="-6557821463175617375" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1366636045">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1366387909" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1366387909">
<transform xil_pn:end_ts="1366636105" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1366636105">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366387921" xil_pn:in_ck="618428940982703508" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1366387909">
<transform xil_pn:end_ts="1366636117" xil_pn:in_ck="618428940982703508" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1366636105">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,9 +131,8 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1366388222" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1366387921">
<transform xil_pn:end_ts="1366636433" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1366636117">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.pcf"/>
......@@ -145,7 +144,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1366388300" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1366388222">
<transform xil_pn:end_ts="1366636513" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1366636433">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -159,7 +158,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1366388336" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1366388300">
<transform xil_pn:end_ts="1366636550" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1366636513">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -171,7 +170,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1366388300" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1366388284">
<transform xil_pn:end_ts="1366636513" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1366636497">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/pts/syn/conv_ttl_blo_v2.xise
View file @ c33673ec
......@@ -353,13 +353,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../rtl/pts_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
......@@ -691,8 +691,8 @@
<file xil_pn:name="../../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../old_rep_test/rtl/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......
hdl/pts/top/Manifest.py
View file @ c33673ec
......@@ -7,6 +7,7 @@ modules = {
"local" : [
"../../../../ip_cores/general-cores",
"../../reset_gen",
"../../old_rep_test"
"../../pulse_generator",
"../../rtm_detector",
"../../bicolor_led_ctrl",
......
hdl/pts/top/conv_ttl_blo_v2.vhd
View file @ c33673ec
......@@ -339,6 +339,24 @@ architecture behav of conv_ttl_blo_v2 is
);
end component pts_regs;
-- Fixed-frequency pulse generator component
-- (use: generate the first pulse that gets replicated from one channel to
-- another, in the TTL pulse test)
component pulse_gen is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 400
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
pulse_o : out std_logic
);
end component pulse_gen;
-- Pulse generator component
-- (use: TTL and BLO pulse tests)
component pulse_generator is
......@@ -365,7 +383,7 @@ architecture behav of conv_ttl_blo_v2 is
pulse_type_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
enable_i : in std_logic;
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
......@@ -835,10 +853,14 @@ begin
led_seq <= (others => '0');
first_pulse_en <= '0';
else
-- Default: pulses not generated
first_pulse_en <= '0';
case pts_state is
when ST_TTLTEST =>
first_pulse_en <= '1';
-- when ST_PLLTEST =>
-- cnt_halfsec <= cnt_halfsec + 1;
-- if (cnt_halfsec = 62499999) then
......@@ -941,48 +963,44 @@ begin
end if;
end process p_oe;
-- Assign registers to outputs
-- Assign output enable registers to chip outputs
fpga_oe_o <= oe;
fpga_blo_oe_o <= blo_oe;
fpga_trig_ttl_oe_o <= ttl_oe;
fpga_inv_oe_o <= inv_oe;
-- Logic to generate the first "pulse" on CH1; the pulse is actually
-- a continuously high signal which is cut by the pulse generator at the
-- output
p_first_pulse: process(clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
first_pulse <= '0';
first_pulse_d0 <= '0';
elsif (first_pulse_en = '1') then
first_pulse <= '1';
first_pulse_d0 <= first_pulse;
end if;
end if;
end process p_first_pulse;
-- The input to the first channel is multiplexed between the first pulse
-- and the input; the selecting input to the mux is the delayed version
-- of the first pulse, after the first pulse is generated, the mux switches
-- to the channel input.
-- ttl_trigs(1) <= first_pulse when (first_pulse_d0 = '0') else
-- not fpga_input_ttl_n_i(1);
-- First, instantiate a pulse generator with fixed frequency and pulse
-- width, to generate the output pulse from CH10 (INV-TTL CH4) to CH1
--
-- 1-us pulses are generated twice a second.
cmp_first_pulse_gen: pulse_gen
generic map
(
g_pwidth => 125,
g_freq => 62*(10**6)
)
port map
(
clk_i => clk125,
rst_n_i => rst_n,
en_i => first_pulse_en,
pulse_o => ttl_pulses(10)
);
-- Assign the rest of the inputs
-- Assign the trigger inputs to internal signals
ttl_trigs(6 downto 1) <= not fpga_input_ttl_n_i;
ttl_trigs(10 downto 7) <= not inv_in_n_i;
-- Now, generate ten pulse generator blocks connected to the TTL outputs
-- Now, generate nine pulse generator blocks connected to the TTL outputs
-- and with the TTL inputs as triggers. External to the FPGA, the inputs of
-- CH2 are expected to be connected to CH1, CH3 to CH2 and so on, until
-- the last INV_TTL output, which is expected to be connected back to the
-- input of CH1.
-- input of CH1. This last INV-TTL output is connected above to the
-- fixed-frequency pulse generator.
--
-- Type 1 pulses (non-glich-filtered) with 1us width will be generated by
-- the generator blocks.
gen_ttl_pulse_gens: for i in 1 to 10 generate
gen_ttl_pulse_gens: for i in 1 to 9 generate
cmp_ttl_pulse_gen: pulse_generator
generic map
(
......@@ -994,7 +1012,7 @@ begin
clk_i => clk125,
rst_n_i => rst_n,
pulse_type_i => '1',
enable_i => '1',
en_i => '1',
trig_i => ttl_trigs(i),
pulse_o => ttl_pulses(i)
);
......@@ -1005,42 +1023,42 @@ begin
fpga_out_ttl_o <= ttl_pulses( 6 downto 1);
inv_out_o <= ttl_pulses(10 downto 7);
-- Generate input and output pulse counters
--gen_ttl_pulse_cntrs: for i in 1 to 10 generate
p_cnt_ttl_pulses: process(clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
cnt_ttl_in <= (others => (others => '0'));
cnt_ttl_out <= (others => (others => '0'));
ttl_trigs_d0 <= (others => '0');
ttl_trigs_d1 <= (others => '0');
ttl_trigs_d2 <= (others => '0');
ttl_pulses_d0 <= (others => '0');
ttl_pulses_d1 <= (others => '0');
ttl_pulses_d2 <= (others => '0');
else
-- Resync each channel input and output pulse and increment the
-- corresponding counter on rising edge of the pulse signal
for i in 1 to 10 loop
ttl_trigs_d0(i) <= ttl_trigs(i);
ttl_trigs_d1(i) <= ttl_trigs_d0(i);
ttl_trigs_d2(i) <= ttl_trigs_d1(i);
if (ttl_trigs_d1(i) = '1') and (ttl_trigs_d2(i) = '0') then
cnt_ttl_in(i) <= cnt_ttl_in(i) + 1;
end if;
ttl_pulses_d0(i) <= ttl_pulses(i);
ttl_pulses_d1(i) <= ttl_pulses_d0(i);
ttl_pulses_d2(i) <= ttl_pulses_d1(i);
if (ttl_pulses_d1(i) = '1') and (ttl_pulses_d2(i) = '0') then
cnt_ttl_out(i) <= cnt_ttl_out(i) + 1;
end if;
end loop;
end if;
-- Process to count input and output pulses. Since the pulses are generated
-- on the rising edge of the input pulse, the outputs from the pulse_generator
-- blocks need to be resynced.
p_cnt_ttl_pulses: process(clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
cnt_ttl_in <= (others => (others => '0'));
cnt_ttl_out <= (others => (others => '0'));
ttl_trigs_d0 <= (others => '0');
ttl_trigs_d1 <= (others => '0');
ttl_trigs_d2 <= (others => '0');
ttl_pulses_d0 <= (others => '0');
ttl_pulses_d1 <= (others => '0');
ttl_pulses_d2 <= (others => '0');
else
-- Resync each channel input and output pulse and increment the
-- corresponding counter on rising edge of the pulse signal
for i in 1 to 10 loop
ttl_trigs_d0(i) <= ttl_trigs(i);
ttl_trigs_d1(i) <= ttl_trigs_d0(i);
ttl_trigs_d2(i) <= ttl_trigs_d1(i);
if (ttl_trigs_d1(i) = '1') and (ttl_trigs_d2(i) = '0') then
cnt_ttl_in(i) <= cnt_ttl_in(i) + 1;
end if;
ttl_pulses_d0(i) <= ttl_pulses(i);
ttl_pulses_d1(i) <= ttl_pulses_d0(i);
ttl_pulses_d2(i) <= ttl_pulses_d1(i);
if (ttl_pulses_d1(i) = '1') and (ttl_pulses_d2(i) = '0') then
cnt_ttl_out(i) <= cnt_ttl_out(i) + 1;
end if;
end loop;
end if;
end process p_cnt_ttl_pulses;
--end generate gen_ttl_pulse_cntrs;
end if;
end process p_cnt_ttl_pulses;
-- Finally, connect a Wishbone slave component containing the regs for the
-- pulse counters
......
hdl/pulse_generator/rtl/pulse_generator.vhd
View file @ c33673ec
......@@ -80,7 +80,7 @@ entity pulse_generator is
pulse_type_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
enable_i : in std_logic;
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
......@@ -183,7 +183,7 @@ begin
if (pulse_rst = '1') then
pulse_type1 <= '0';
elsif rising_edge(trig_i) then
if (enable_i = '1') then
if (en_i = '1') then
pulse_type1 <= '1';
end if;
end if;
......@@ -197,7 +197,7 @@ begin
pulse_type1_d0 <= '0';
pulse_type1_d1 <= '0';
pulse_type1_d2 <= '0';
elsif (enable_i = '1') then
elsif (en_i = '1') then
pulse_type1_d0 <= pulse_type1;
pulse_type1_d1 <= pulse_type1_d0;
pulse_type1_d2 <= pulse_type1_d1;
......@@ -211,7 +211,7 @@ begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
pulse_type2 <= '0';
elsif (enable_i = '1') then
elsif (en_i = '1') then
pulse_type2 <= '0';
if (state = ST_PULSE_TYPE2) then
pulse_type2 <= '1';
......@@ -247,7 +247,7 @@ begin
pulse_rst <= '1';
width_cnt <= (others => '0');
trig_degl_d0 <= '0';
elsif (enable_i = '1') then
elsif (en_i = '1') then
-- Deglitched trigger delay
trig_degl_d0 <= trig_degl;
......
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ c33673ec
This diff is collapsed.
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ c33673ec
......@@ -295,7 +295,7 @@ begin
else
oe <= '1';
if (oe = '1') then
blo_oe <= '0';
blo_oe <= '1';
ttl_oe <= '1';
inv_oe <= '1';
end if;
......
pcb/PTS_P2_Board/PTS_P2_Board.OutJob 0 → 100644
View file @ c33673ec
[OutputJobFile]
Version=1.0
[OutputGroup1]
Name=
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TargetOutputMedium=PDF
VariantName=[No Variations]
VariantScope=0
CurrentConfigurationName=
TargetPrinter=\\CERNPRINTHP\864-1A17-HPCOL
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputMedium1=Print Job
OutputMedium1_Type=Printer
OutputMedium1_Printer=
OutputMedium1_PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputMedium2=PDF
OutputMedium2_Type=Publish
OutputMedium3=Folder Structure
OutputMedium3_Type=GeneratedFiles
OutputMedium4=Video
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[PublishSettings]
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OutputPathMedia2=
OutputPathOutputer2=[Output Type]
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pcb/PTS_P2_Board/PTS_P2_Board.PrjPCB 0 → 100644
View file @ c33673ec
This diff is collapsed.
pcb/PTS_P2_Board/PTS_P2_Board.PrjPCBStructure 0 → 100644
View file @ c33673ec
Record=TopLevelDocument|FileName=PTS_P2_Board.SchDoc
pcb/PTS_P2_Board/Project Logs for PTS_P2_Board/PTS_P2_Board PCB ECO 4-25-2013 11-18-35 AM.LOG 0 → 100644
View file @ c33673ec
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