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Conv TTL Blocking
Commit cf33831c authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Creating i2c-test branch and switching to it, for testing purposes.

parent 271a30e4
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hdl/IMAGES/image1/constraints/V2/BloV2.ucf
View file @ cf33831c
......@@ -7,8 +7,8 @@
##----------------------------------------
NET "RST_N" LOC = N20;
NET "RST_N" IOSTANDARD = LVTTL;
NET "rst_i" LOC = N20;
NET "rst_i" IOSTANDARD = LVTTL;
#NET "FPGA_SYSRESET_N" LOC = L20;
NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = LVTTL;
......@@ -371,18 +371,18 @@ NET "LEVEL" IOSTANDARD = LVCMOS33;
##--
##-- + ACT: CMOS 3.3V input
##-------------------
NET "FPGA_RTMM_N[0]" LOC = V21;
NET "FPGA_RTMM_N[0]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[1]" LOC = V22;
NET "FPGA_RTMM_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[2]" LOC = U22;
NET "FPGA_RTMM_N[2]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[0]" LOC = W22;
NET "FPGA_RTMP_N[0]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[1]" LOC = Y22;
NET "FPGA_RTMP_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[2]" LOC = Y21;
NET "FPGA_RTMP_N[2]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[0]" LOC = V21;
NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[1]" LOC = V22;
NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[2]" LOC = U22;
NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[0]" LOC = W22;
NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[1]" LOC = Y22;
NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[2]" LOC = Y21;
NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
###-------------------
###-- General purpose
###--
......
hdl/IMAGES/image1/project/image1.gise
View file @ cf33831c
......@@ -102,7 +102,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361383048" xil_pn:in_ck="2481835375757340990" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1361383029">
<transform xil_pn:end_ts="1361527497" xil_pn:in_ck="2481835375757340990" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1361527478">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -120,11 +120,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1361359880" xil_pn:in_ck="-6700002251458007206" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1361359880">
<transform xil_pn:end_ts="1361520115" xil_pn:in_ck="-6700002251458007206" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1361520115">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361383079" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1361383072">
<transform xil_pn:end_ts="1361527503" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1361527497">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -134,7 +134,7 @@
<outfile xil_pn:name="image1_top.ngd"/>
<outfile xil_pn:name="image1_top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1361383118" xil_pn:in_ck="-662876564851204569" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1361383079">
<transform xil_pn:end_ts="1361527537" xil_pn:in_ck="-662876564851204569" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1361527503">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -147,7 +147,7 @@
<outfile xil_pn:name="image1_top_summary.xml"/>
<outfile xil_pn:name="image1_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1361383152" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1361383118">
<transform xil_pn:end_ts="1361527577" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1361527537">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -162,7 +162,7 @@
<outfile xil_pn:name="image1_top_pad.txt"/>
<outfile xil_pn:name="image1_top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1361383171" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1361383152">
<transform xil_pn:end_ts="1361527596" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1361527577">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -173,13 +173,13 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1361383284" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1361383284">
<transform xil_pn:end_ts="1361527596" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1361527596">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1361383152" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1361383144">
<transform xil_pn:end_ts="1361527577" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1361527568">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/IMAGES/image1/project/image1.xise
View file @ cf33831c
......@@ -445,8 +445,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb/i2c_driver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.i2c_master_driver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -469,7 +469,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.image1_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.i2c_master_driver" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.image1_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
hdl/IMAGES/image1/rtl/image1_core.vhd
View file @ cf33831c
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- Top level entity of CONV-TTL-BLO V2
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
......@@ -17,6 +17,10 @@
--
-- dependencies:
--
-- references:
-- [1] ELMA Crates Specification: Access to board data using SNMP and I2C
-- available at: http://www.ohwr.org/documents/227
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
......@@ -52,77 +56,63 @@ entity image1_core is
);
port
(
rst_n : in STD_LOGIC;
clk_20MHz_i : in STD_LOGIC;
clk_125MHz_i : in STD_LOGIC;
rst_i : in std_logic;
clk_20_i : in std_logic;
clk_125_i : in std_logic;
--! LEDs
-- LEDs
led_array_o : out t_led_array_o;
led_front_n : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_rear_n : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_front_n : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
led_rear_n : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
--! I/Os for pulses
pulse_i_front_n : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i_n : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1);
-- I/Os for pulses
pulse_i_front_n : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
inv_i_n : in std_logic_vector(4 downto 1);
inv_o : out std_logic_vector(4 downto 1);
--! Lines for the i2c_slave
-- Lines for the i2c_slave
i2c_slave_i : in t_i2c_slave_i;
i2c_slave_o : out t_i2c_slave_o;
--! FPGA Geographical address pins (reused for i2c address)
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
-- FPGA Geographical address pins (reused for i2c address)
FPGA_GA : in std_logic_vector(4 downto 0);
FPGA_GAP : in std_logic;
--! Pins of the SPI interface to write into the Flash memory
-- Pins of the SPI interface to write into the Flash memory
spi_master_i : in t_spi_master_i;
spi_master_o : out t_spi_master_o;
--! Enable signals
fpga_o_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
-- Enable signals
fpga_o_en : out std_logic;
fpga_o_blo_en : out std_logic;
fpga_o_ttl_en : out std_logic;
fpga_o_inv_en : out std_logic;
-- Level and switch inputs
level_i : in STD_LOGIC;
switch_i : in STD_LOGIC;
level_i : in std_logic;
switch_i : in std_logic;
--! Manual reset, allows power sequencing of the
--! 24V rail after a security given delay
manual_rst_n_o : out STD_LOGIC;
-- Manual reset, allows power sequencing of the
-- 24V rail after a security given delay
manual_rst_n_o : out std_logic;
--! RTM identifiers, should match with the expected values
--! TODO: add matching
rtm_i : in t_rtm_i
-- RTM identifiers
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0)
);
end image1_core;
architecture Behavioral of image1_core is
type t_clocks is
record
PLL_IN : STD_LOGIC; --! 125MHz Input clock
PLL_FB_IN : STD_LOGIC;
PLL_FB_OUT : STD_LOGIC;
PLL_SYS_A : STD_LOGIC; --! 50MHz Wishbone clock
PLL_SYS_B : STD_LOGIC; --! 200MHz Pulse sampling
SYS_A : STD_LOGIC;
SYS_B : STD_LOGIC;
end record;
type t_rst is
record
PLL : STD_LOGIC_VECTOR(c_RST_PLL_CLKS - 1 downto 0);
SYS_A : STD_LOGIC_VECTOR(c_RST_A_CLKS - 1 downto 0);
SYS_B : STD_LOGIC_VECTOR(c_RST_B_CLKS - 1 downto 0);
end record;
--============================================================================
-- Component declarations
--============================================================================
-- Trigger leds I2C test component
component test_trigleds_wb is
port
(
......@@ -136,74 +126,131 @@ architecture Behavioral of image1_core is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'Bits' in reg: 'LED'
-- Port for std_logic_vector field: 'Bits' in reg: 'LED'
trigleds_reg_bits_o : out std_logic_vector(5 downto 0)
);
end component test_trigleds_wb;
signal s_clk : t_clocks;
signal s_rst : t_rst := (
PLL => (others => '1'),
SYS_A => (others => '1'),
SYS_B => (others => '1')
);
signal s_rst_n : STD_LOGIC;
signal s_locked : STD_LOGIC;
signal s_ok_RTMM : STD_LOGIC;
signal s_ok_RTMP : STD_LOGIC;
signal s_slave_i : t_wishbone_slave_in_array (c_NUM_MASTERS - 1 downto 0);
signal s_slave_o : t_wishbone_slave_out_array (c_NUM_MASTERS - 1 downto 0);
signal s_master_i : t_wishbone_master_in_array (c_NUM_SLAVES - 1 downto 0);
signal s_master_o : t_wishbone_master_out_array (c_NUM_SLAVES - 1 downto 0);
-- I2C bridge top-level
component i2c_slave_top
generic
(
g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD -- Specify in ns
);
port
(
sda_oen : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_oen : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_master_stb_o : out std_logic;
wb_master_cyc_o : out std_logic;
wb_master_sel_o : out std_logic_vector(3 downto 0);
wb_master_we_o : out std_logic;
wb_master_data_i : in std_logic_vector(31 downto 0);
wb_master_data_o : out std_logic_vector(31 downto 0);
wb_master_addr_o : out std_logic_vector(15 downto 0);
wb_master_ack_i : in std_logic;
wb_master_rty_i : in std_logic;
wb_master_err_i : in std_logic;
wb_slave_stb_i : in std_logic;
wb_slave_cyc_i : in std_logic;
wb_slave_sel_i : in std_logic_vector(3 downto 0);
wb_slave_we_i : in std_logic;
wb_slave_data_i : in std_logic_vector(31 downto 0);
wb_slave_data_o : out std_logic_vector(31 downto 0);
wb_slave_addr_i : in std_logic_vector(3 downto 0);
wb_slave_ack_o : out std_logic;
wb_slave_rty_o : out std_logic;
wb_slave_err_o : out std_logic;
pf_wb_addr_o : out std_logic;
rd_done_o : out std_logic;
wr_done_o : out std_logic;
i2c_addr_i : in std_logic_vector(6 downto 0)
);
end component i2c_slave_top;
-- RTM detector component
component rtm_detector is
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end component rtm_detector;
--============================================================================
-- Signal declarations
--============================================================================
-- Clock and reset signals
signal clk_buf_50 : std_logic;
signal clk_50 : std_logic;
signal clk_buf_200 : std_logic;
signal clk_200 : std_logic;
signal pll_fb_out : std_logic;
signal pll_fb_in : std_logic;
signal rst_n : std_logic;
-- Signal to indicate the lock status of the PLL
signal pll_locked : std_logic;
signal s_i2c_addr : STD_LOGIC_VECTOR(6 downto 0);
-- RTM detection signals
signal rtmm_ok : std_logic;
signal rtmp_ok : std_logic;
signal s_pulse_i_front : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_leds_array_image1 : t_leds_array;
signal s_led_state_array : t_led_state_array(c_NB_ARRAY_LEDS - 1 downto 0);
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_NUM_MASTERS - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_NUM_MASTERS - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_NUM_SLAVES - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array (c_NUM_SLAVES - 1 downto 0);
-- Internal I2C signals
signal i2c_addr : std_logic_vector(6 downto 0);
signal i2c_rd_done : std_logic;
signal i2c_wr_done : std_logic;
signal i2c_up : std_logic;
-- Internal pulse signal
signal pulse_front_in : std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
-- Internal signals for bicolor LED matrix control
signal leds_array : t_leds_array;
signal led_state_array : t_led_state_array(c_NB_ARRAY_LEDS - 1 downto 0);
--
--
-- !!!!!!!!!!!!!!!!!!!
--
--
--
-- !!!!!!!!!!!!!!!!!!!
-- I2C test front panel LED signal
signal trigleds : std_logic_vector(5 downto 0);
signal leds_from_trig : std_logic_vector(5 downto 0);
signal sda_dummy : std_logic;
signal sda_dummy_n : std_logic;
-- signal s_check_cfg : BOOLEAN;
begin
-- s_check_cfg <= check_sys_cfg;
s_i2c_addr <= "10" & FPGA_GA; -- f_RENESAS_I2C_ADDRESSING(UNSIGNED(FPGA_GA));
s_leds_array_image1.top.ERR <= '1' when s_ok_RTMM = '1' AND s_ok_RTMP = '1' else
'0';
s_clk.PLL_IN <= clk_125MHz_i;
s_pulse_i_front <= not(pulse_i_front_n);
s_clk_fb_bufg : BUFG
port map
(
I => s_clk.PLL_FB_OUT,
O => s_clk.PLL_FB_IN
);
--============================================================================
-- General I/O logic
--============================================================================
-- Assign the active low reset signal
rst_n <= not(rst_i);
-- Negate input pulses, due to the Schmitt trigger inverter on the board
pulse_front_in <= not(pulse_i_front_n);
-- Assign the I2C address based on the geographical address lines (see [1])
i2c_addr <= "10" & FPGA_GA;
-- set up the fabric PLL_BASE to drive the BUFPLL
--============================================================================
-- Generation of internal clock signals
--============================================================================
-- set up the fabric PLL_BASE to drive the BUFPLL
pll_base_inst : PLL_BASE
generic map
(
......@@ -211,12 +258,12 @@ begin
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_MULT => 8, -- 1 GHz at FBOUT
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 20,
CLKOUT0_DIVIDE => 20, -- 50 MHz at OUT0
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 5,
CLKOUT1_DIVIDE => 5, -- 200 MHz at OUT1
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => c_CLKIN_PERIOD,
......@@ -225,104 +272,49 @@ begin
port map
(
-- Output clocks
CLKFBOUT => s_clk.PLL_FB_OUT,
CLKOUT0 => s_clk.PLL_SYS_A,
CLKOUT1 => s_clk.PLL_SYS_B,
CLKFBOUT => pll_fb_out,
CLKOUT0 => clk_buf_50,
CLKOUT1 => clk_buf_200,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- Status and control signals
LOCKED => s_locked,
RST => s_rst.PLL(c_RST_PLL_CLKS - 1),
LOCKED => pll_locked,
RST => rst_i, -- s_rst.PLL(c_RST_PLL_CLKS - 1),
-- Input clock control
CLKFBIN => s_clk.PLL_FB_IN,
CLKIN => s_clk.PLL_IN
CLKFBIN => pll_fb_in,
CLKIN => clk_125_i
);
-- Clock buffer on the PLL feedback line
s_clk_fb_bufg : BUFG
port map
(
I => pll_fb_out,
O => pll_fb_in
);
-- Clock buffer for distributing the 50 MHz clock signal
s_clk_50M_bufg : BUFG
port map
(
I => s_clk.PLL_SYS_A,
O => s_clk.SYS_A
I => clk_buf_50,
O => clk_50
);
-- Clock buffer for distributing the 200 MHz clock signal
s_clk_200M_bufg : BUFG
port map
(
I => s_clk.PLL_SYS_B,
O => s_clk.SYS_B
I => clk_buf_200,
O => clk_200
);
--! @brief Reset chain for PLL
--! @param s_clk.PLL Wishbone clock
p_reset_PLL_chain : process(s_clk.PLL_IN) is
begin
if rising_edge(s_clk.PLL_IN) then
s_rst.PLL <= (others => '1');
s_rst.PLL(0) <= '0';
for i in 1 to c_RST_PLL_CLKS - 1 loop
s_rst.PLL(i) <= s_rst.PLL(i-1);
end loop;
-- if s_rst.PLL(c_RST_PLL_CLKS - 1) = '1' then
-- end if;
end if;
end process p_reset_PLL_chain;
--! @brief Reset chain
--! @param s_clk.SYS_A Wishbone clock
p_reset_A_chain : process(s_clk.SYS_A) is
begin
if rising_edge(s_clk.SYS_A) then
if s_locked = '0' then
s_rst.SYS_A <= (others => '1');
else
s_rst.SYS_A(0) <= '0';
for i in 1 to c_RST_A_CLKS - 1 loop
s_rst.SYS_A(i) <= s_rst.SYS_A(i-1);
end loop;
-- if s_rst.SYS_A(c_RST_A_CLKS - 1) = '1' then
-- end if;
end if;
end if;
end process p_reset_A_chain;
--! @brief Reset chain
--! @param s_clk.SYS_B System of clock domain B
p_reset_B_chain : process(s_clk.SYS_B) is
begin
if rising_edge(s_clk.SYS_B) then
if s_locked = '0' then
s_rst.SYS_B <= (others => '1');
else
s_rst.SYS_B(0) <= '0';
for i in 1 to c_RST_B_CLKS - 1 loop
s_rst.SYS_B(i) <= s_rst.SYS_B(i-1);
end loop;
-- if s_rst.SYS_B(c_RST_B_CLKS - 1) = '1' then
-- end if;
end if;
end if;
end process p_reset_B_chain;
-- !!!!!
-- led_front_n <= "111000";
led_front_n <= not trigleds;
inst_basic_trigger: basic_trigger_top
--============================================================================
-- Pulse generation module
--============================================================================
cmp_basic_trigger: basic_trigger_top
generic map
(
g_NUMBER_OF_CHANNELS => c_NUMBER_OF_CHANNELS,
......@@ -332,9 +324,9 @@ begin
)
port map
(
clk_i => s_clk.SYS_B,
rst_i => s_rst.SYS_B(c_RST_B_CLKS - 1),
led_ttl_o => s_leds_array_image1.top.TTL_N,
clk_i => clk_200,
rst_i => rst_i, -- s_rst.SYS_B(c_RST_B_CLKS - 1),
led_ttl_o => leds_array.top.TTL_N,
fpga_o_en => fpga_o_en,
fpga_o_ttl_en => fpga_o_ttl_en,
fpga_o_inv_en => fpga_o_inv_en,
......@@ -342,48 +334,27 @@ begin
level_i => level_i,
switch_i => switch_i,
manual_rst_n_o => manual_rst_n_o,
pulse_i_front => s_pulse_i_front,
pulse_i_front => pulse_front_in,
pulse_o_front => pulse_o_front,
pulse_i_rear => pulse_i_rear,
pulse_o_rear => pulse_o_rear,
-- !!!!!!!!!!!!
led_o_front => leds_from_trig, -- led_front_n,
led_o_front => open, -- led_front_n,
led_o_rear => led_rear_n,
inv_i => inv_i_n,
inv_o => inv_o
);
--
-- -- s_slave_o(c_MASTER_I2C_SLAVE).stall;
-- -- s_slave_o(c_MASTER_I2C_SLAVE).int;
-- -- s_master_i(c_SLAVE_I2C_SLAVE).stall,
-- -- s_master_i(c_SLAVE_I2C_SLAVE).int,
--
--! We are always the slave so we disable writes into SCL pin
-- i2c_slave_o.scl_oe <= '0';
--============================================================================
-- I2C slave module instantiation and connections
--============================================================================
--
-- i2c_slave_o.sda_oe <= '0';
-- i2c_slave_o.sda_o <= '0';
-- i2c_slave_o.scl_o <= '0';
s_slave_i(c_MASTER_I2C_SLAVE).adr(31 downto 16) <= (others => '0');
inst_i2c_slave: i2c_slave_top
-- -- xbar_slave_out(c_MASTER_I2C_SLAVE).stall;
-- -- xbar_slave_out(c_MASTER_I2C_SLAVE).int;
-- -- xbar_master_in(c_SLAVE_I2C_SLAVE).stall,
-- -- xbar_master_in(c_SLAVE_I2C_SLAVE).int,
--
cmp_i2c_slave: i2c_slave_top
port map
(
sda_oen => i2c_slave_o.SDA_OE,
......@@ -392,43 +363,44 @@ begin
scl_oen => i2c_slave_o.SCL_OE,
scl_i => i2c_slave_i.SCL_I,
scl_o => i2c_slave_o.SCL_O,
wb_clk_i => s_clk.SYS_A,
wb_rst_i => s_rst.SYS_A(c_RST_A_CLKS - 1),
wb_master_stb_o => s_slave_i(c_MASTER_I2C_SLAVE).stb,
wb_master_cyc_o => s_slave_i(c_MASTER_I2C_SLAVE).cyc,
wb_master_sel_o => s_slave_i(c_MASTER_I2C_SLAVE).sel,
wb_master_we_o => s_slave_i(c_MASTER_I2C_SLAVE).we,
wb_master_data_i => s_slave_o(c_MASTER_I2C_SLAVE).dat,
wb_master_data_o => s_slave_i(c_MASTER_I2C_SLAVE).dat,
wb_master_addr_o => s_slave_i(c_MASTER_I2C_SLAVE).adr(15 downto 0),
wb_master_ack_i => s_slave_o(c_MASTER_I2C_SLAVE).ack,
wb_master_rty_i => s_slave_o(c_MASTER_I2C_SLAVE).rty,
wb_master_err_i => s_slave_o(c_MASTER_I2C_SLAVE).err,
wb_slave_stb_i => s_master_o(c_SLAVE_I2C_SLAVE).stb,
wb_slave_cyc_i => s_master_o(c_SLAVE_I2C_SLAVE).cyc,
wb_slave_sel_i => s_master_o(c_SLAVE_I2C_SLAVE).sel,
wb_slave_we_i => s_master_o(c_SLAVE_I2C_SLAVE).we,
wb_slave_data_i => s_master_o(c_SLAVE_I2C_SLAVE).dat,
wb_slave_data_o => s_master_i(c_SLAVE_I2C_SLAVE).dat,
wb_slave_addr_i => s_master_o(c_SLAVE_I2C_SLAVE).adr( 5 downto 2),
wb_slave_ack_o => s_master_i(c_SLAVE_I2C_SLAVE).ack,
wb_slave_rty_o => s_master_i(c_SLAVE_I2C_SLAVE).rty,
wb_slave_err_o => s_master_i(c_SLAVE_I2C_SLAVE).err,
wb_clk_i => clk_50,
wb_rst_i => rst_i,
wb_master_stb_o => xbar_slave_in(c_MASTER_I2C_SLAVE).stb,
wb_master_cyc_o => xbar_slave_in(c_MASTER_I2C_SLAVE).cyc,
wb_master_sel_o => xbar_slave_in(c_MASTER_I2C_SLAVE).sel,
wb_master_we_o => xbar_slave_in(c_MASTER_I2C_SLAVE).we,
wb_master_data_i => xbar_slave_out(c_MASTER_I2C_SLAVE).dat,
wb_master_data_o => xbar_slave_in(c_MASTER_I2C_SLAVE).dat,
wb_master_addr_o => xbar_slave_in(c_MASTER_I2C_SLAVE).adr(15 downto 0),
wb_master_ack_i => xbar_slave_out(c_MASTER_I2C_SLAVE).ack,
wb_master_rty_i => xbar_slave_out(c_MASTER_I2C_SLAVE).rty,
wb_master_err_i => xbar_slave_out(c_MASTER_I2C_SLAVE).err,
wb_slave_stb_i => xbar_master_out(c_SLAVE_I2C_SLAVE).stb,
wb_slave_cyc_i => xbar_master_out(c_SLAVE_I2C_SLAVE).cyc,
wb_slave_sel_i => xbar_master_out(c_SLAVE_I2C_SLAVE).sel,
wb_slave_we_i => xbar_master_out(c_SLAVE_I2C_SLAVE).we,
wb_slave_data_i => xbar_master_out(c_SLAVE_I2C_SLAVE).dat,
wb_slave_data_o => xbar_master_in(c_SLAVE_I2C_SLAVE).dat,
wb_slave_addr_i => xbar_master_out(c_SLAVE_I2C_SLAVE).adr( 5 downto 2),
wb_slave_ack_o => xbar_master_in(c_SLAVE_I2C_SLAVE).ack,
wb_slave_rty_o => xbar_master_in(c_SLAVE_I2C_SLAVE).rty,
wb_slave_err_o => xbar_master_in(c_SLAVE_I2C_SLAVE).err,
pf_wb_addr_o => open,
rd_done_o => i2c_rd_done,
wr_done_o => i2c_wr_done,
i2c_addr_i => s_i2c_addr
i2c_addr_i => i2c_addr
);
xbar_slave_in(c_MASTER_I2C_SLAVE).adr(31 downto 16) <= (others => '0');
-- Process to set the I2C_UP signal for display on the front panel
-- of the front module. The I2C_UP signal is permanently set once an
-- I2C transfer has successfully completed, as signaled by the RD_DONE
-- and WR_DONE outputs of the I2C slave.
p_i2c_up: process (s_clk.sys_a) is
p_i2c_up: process (clk_50) is
begin
if rising_edge(s_clk.sys_a) then
if (s_rst_n = '0') then
if rising_edge(clk_50) then
if (rst_n = '0') then
i2c_up <= '0';
elsif (i2c_rd_done = '1') or (i2c_wr_done = '1') then
i2c_up <= '1';
......@@ -442,17 +414,17 @@ begin
--
-- inst_m25p32: m25p32_top
-- port map(wb_rst_i => s_rst.SYS_A(c_RST_A_CLKS - 1),
-- wb_clk => s_clk.SYS_A,
-- wb_we_i => s_master_o(c_SLAVE_M25P32).we,
-- wb_stb_i => s_master_o(c_SLAVE_M25P32).stb,
-- wb_cyc_i => s_master_o(c_SLAVE_M25P32).cyc,
-- wb_sel_i => s_master_o(c_SLAVE_M25P32).sel,
-- wb_data_i => s_master_o(c_SLAVE_M25P32).dat,
-- wb_data_o => s_master_i(c_SLAVE_M25P32).dat,
-- wb_addr_i => s_master_o(c_SLAVE_M25P32).adr( 8 downto 2),
-- wb_ack_o => s_master_i(c_SLAVE_M25P32).ack,
-- wb_rty_o => s_master_i(c_SLAVE_M25P32).rty,
-- wb_err_o => s_master_i(c_SLAVE_M25P32).err,
-- wb_clk => clk_50,
-- wb_we_i => xbar_master_out(c_SLAVE_M25P32).we,
-- wb_stb_i => xbar_master_out(c_SLAVE_M25P32).stb,
-- wb_cyc_i => xbar_master_out(c_SLAVE_M25P32).cyc,
-- wb_sel_i => xbar_master_out(c_SLAVE_M25P32).sel,
-- wb_data_i => xbar_master_out(c_SLAVE_M25P32).dat,
-- wb_data_o => xbar_master_in(c_SLAVE_M25P32).dat,
-- wb_addr_i => xbar_master_out(c_SLAVE_M25P32).adr( 8 downto 2),
-- wb_ack_o => xbar_master_in(c_SLAVE_M25P32).ack,
-- wb_rty_o => xbar_master_in(c_SLAVE_M25P32).rty,
-- wb_err_o => xbar_master_in(c_SLAVE_M25P32).err,
-- miso_word_rcv => open,
-- op_finished_o => open,
-- prom_mosi_o => spi_master_o.MOSI,
......@@ -463,111 +435,130 @@ begin
--
-- inst_multiboot: multiboot_top
-- port map(wb_rst_i => s_rst.SYS_A(c_RST_A_CLKS - 1),
-- wb_clk => s_clk.SYS_A,
-- wb_we_i => s_master_o(c_SLAVE_MULTIBOOT).we,
-- wb_stb_i => s_master_o(c_SLAVE_MULTIBOOT).stb,
-- wb_cyc_i => s_master_o(c_SLAVE_MULTIBOOT).cyc,
-- wb_sel_i => s_master_o(c_SLAVE_MULTIBOOT).sel,
-- wb_data_i => s_master_o(c_SLAVE_MULTIBOOT).dat,
-- wb_data_o => s_master_i(c_SLAVE_MULTIBOOT).dat,
-- wb_addr_i => s_master_o(c_SLAVE_MULTIBOOT).adr( 5 downto 2),
-- wb_ack_o => s_master_i(c_SLAVE_MULTIBOOT).ack,
-- wb_rty_o => s_master_i(c_SLAVE_MULTIBOOT).rty,
-- wb_err_o => s_master_i(c_SLAVE_MULTIBOOT).err);
-- wb_clk => clk_50,
-- wb_we_i => xbar_master_out(c_SLAVE_MULTIBOOT).we,
-- wb_stb_i => xbar_master_out(c_SLAVE_MULTIBOOT).stb,
-- wb_cyc_i => xbar_master_out(c_SLAVE_MULTIBOOT).cyc,
-- wb_sel_i => xbar_master_out(c_SLAVE_MULTIBOOT).sel,
-- wb_data_i => xbar_master_out(c_SLAVE_MULTIBOOT).dat,
-- wb_data_o => xbar_master_in(c_SLAVE_MULTIBOOT).dat,
-- wb_addr_i => xbar_master_out(c_SLAVE_MULTIBOOT).adr( 5 downto 2),
-- wb_ack_o => xbar_master_in(c_SLAVE_MULTIBOOT).ack,
-- wb_rty_o => xbar_master_in(c_SLAVE_MULTIBOOT).rty,
-- wb_err_o => xbar_master_in(c_SLAVE_MULTIBOOT).err);
--
--
--============================================================================
-- Instantiation and connection of a Wishbone crossbar module
--============================================================================
xbar_master_in(c_SLAVE_I2C_SLAVE).stall <= '0';
xbar_master_in(c_SLAVE_I2C_SLAVE).int <= '0';
xbar_master_in(c_slave_trigleds_wb).int <= '0';
-- xbar_master_in(c_SLAVE_M25P32).stall <= '0';
-- xbar_master_in(c_SLAVE_M25P32).int <= '0';
-- xbar_master_in(c_SLAVE_MULTIBOOT).stall <= '0';
-- xbar_master_in(c_SLAVE_MULTIBOOT).int <= '0';
s_master_i(c_SLAVE_I2C_SLAVE).stall <= '0';
s_master_i(c_SLAVE_I2C_SLAVE).int <= '0';
s_master_i(c_slave_trigleds_wb).int <= '0';
-- s_master_i(c_SLAVE_M25P32).stall <= '0';
-- s_master_i(c_SLAVE_M25P32).int <= '0';
-- s_master_i(c_SLAVE_MULTIBOOT).stall <= '0';
-- s_master_i(c_SLAVE_MULTIBOOT).int <= '0';
inst_wb_crossbar: xwb_crossbar
cmp_wb_crossbar: xwb_crossbar
generic map
(
g_num_masters => c_NUM_MASTERS,
g_num_slaves => c_NUM_SLAVES,
g_registered => false,
-- Address of the slaves connected
--! It should be noted that the default address length is 32
--! In our project only 16 bits are addressable
-- It should be noted that the default address length is 32
-- In our project only 16 bits are addressable
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => s_clk.SYS_A,
rst_n_i => s_rst_n,
slave_i => s_slave_i ,
slave_o => s_slave_o ,
master_i => s_master_i,
master_o => s_master_o
clk_sys_i => clk_50,
rst_n_i => rst_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- I2C test trigger LEDs instantiation and connections
--============================================================================
cmp_test_trigleds: test_trigleds_wb
port map
(
rst_n_i => s_rst_n,
clk_sys_i => s_clk.sys_a,
wb_dat_i => s_master_o(c_slave_trigleds_wb).dat,
wb_dat_o => s_master_i(c_slave_trigleds_wb).dat,
wb_cyc_i => s_master_o(c_slave_trigleds_wb).cyc,
wb_sel_i => s_master_o(c_slave_trigleds_wb).sel,
wb_stb_i => s_master_o(c_slave_trigleds_wb).stb,
wb_we_i => s_master_o(c_slave_trigleds_wb).we,
wb_ack_o => s_master_i(c_slave_trigleds_wb).ack,
wb_stall_o => s_master_i(c_slave_trigleds_wb).stall,
rst_n_i => rst_n,
clk_sys_i => clk_50,
wb_dat_i => xbar_master_out(c_slave_trigleds_wb).dat,
wb_dat_o => xbar_master_in(c_slave_trigleds_wb).dat,
wb_cyc_i => xbar_master_out(c_slave_trigleds_wb).cyc,
wb_sel_i => xbar_master_out(c_slave_trigleds_wb).sel,
wb_stb_i => xbar_master_out(c_slave_trigleds_wb).stb,
wb_we_i => xbar_master_out(c_slave_trigleds_wb).we,
wb_ack_o => xbar_master_in(c_slave_trigleds_wb).ack,
wb_stall_o => xbar_master_in(c_slave_trigleds_wb).stall,
-- Port for std_logic_vector field: 'Bits' in reg: 'LED'
trigleds_reg_bits_o => trigleds
);
-- !!!!!
led_front_n <= not trigleds;
--============================================================================
-- RTM detection module
--============================================================================
cmp_rtm_detector: rtm_detector
port map
(
rtmm_i => rtmm_i,
rtmp_i => rtmp_i,
rtmm_ok_o => rtmm_ok,
rtmp_ok_o => rtmp_ok
);
s_leds_array_image1.top.pwr <= '1';
s_leds_array_image1.middle.wr_ok <= '0';
s_leds_array_image1.middle.wr_link <= '0';
s_leds_array_image1.middle.wr_addr <= '0';
--============================================================================
-- Bicolor LED matrix controller
--============================================================================
leds_array.top.pwr <= '1';
leds_array.middle.wr_ok <= '0';
leds_array.middle.wr_link <= '0';
leds_array.middle.wr_addr <= '0';
-- !!! Should be OR function on V2 RTMPs
leds_array.top.err <= '1' when (rtmm_ok = '0') and (rtmp_ok = '0') else
'0';
--! Here are organized in the same disposition as in the front panel.
--! Take a look to image1_led_pkg.vhd for the correct order for
--! bicolor_led_ctrl
s_led_state_array(c_LED_NB_PWR) <= f_LED_STATE(c_LED_COLOR_PWR) when s_leds_array_image1.top.PWR = '1' else
f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_ERR) <= f_LED_STATE(c_LED_COLOR_ERR) when s_leds_array_image1.top.ERR = '1' else
f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_TTL_N) <= f_LED_STATE(c_LED_COLOR_TTL_N) when s_leds_array_image1.top.TTL_N = '1' else
f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_I2C) <= f_LED_STATE(c_LED_COLOR_I2C) when i2c_up = '1' else
f_LED_STATE(c_LED_RED);
s_led_state_array(c_LED_NB_WR_OK) <= f_LED_STATE(c_LED_COLOR_WR_OK) when s_leds_array_image1.middle.WR_OK = '1' else
f_LED_STATE(c_LED_RED);
s_led_state_array(c_LED_NB_WR_LINK) <= f_LED_STATE(c_LED_COLOR_WR_LINK) when s_leds_array_image1.middle.WR_LINK = '1' else
f_LED_STATE(c_LED_RED);
s_led_state_array(c_LED_NB_WR_GMT) <= f_LED_STATE(c_LED_COLOR_WR_GMT) when s_leds_array_image1.middle.WR_GMT = '1'else
f_LED_STATE(c_LED_RED);
s_led_state_array(c_LED_NB_WR_ADDR) <= f_LED_STATE(c_LED_COLOR_WR_ADDR) when s_leds_array_image1.middle.WR_ADDR = '1' else
f_LED_STATE(c_LED_RED);
s_led_state_array(c_LED_NB_MULTICAST3) <= f_LED_STATE(c_LED_COLOR_MULTICAST3) when s_leds_array_image1.bottom.MULTICAST(3) = '1' else
f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_MULTICAST2) <= f_LED_STATE(c_LED_COLOR_MULTICAST2) when s_leds_array_image1.bottom.MULTICAST(2) = '1' else
f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_MULTICAST1) <= f_LED_STATE(c_LED_COLOR_MULTICAST1) when s_leds_array_image1.bottom.MULTICAST(1) = '1' else
f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_MULTICAST0) <= f_LED_STATE(c_LED_COLOR_MULTICAST0) when s_leds_array_image1.bottom.MULTICAST(0) = '1' else
f_LED_STATE(c_LED_OFF);
s_rst_n <= not(s_rst.SYS_A(c_RST_A_CLKS - 1));
inst_bicolor_led_ctrl: bicolor_led_ctrl
-- Here are organized in the same disposition as in the front panel.
-- Take a look to image1_led_pkg.vhd for the correct order for
-- bicolor_led_ctrl
led_state_array(c_LED_NB_PWR) <= f_led_state(c_LED_COLOR_PWR) when leds_array.top.PWR = '1' else
f_led_state(c_LED_OFF);
led_state_array(c_LED_NB_ERR) <= f_led_state(c_LED_RED) when leds_array.top.ERR = '1' else
f_led_state(c_LED_OFF);
led_state_array(c_LED_NB_TTL_N) <= f_led_state(c_LED_COLOR_TTL_N) when leds_array.top.TTL_N = '1' else
f_led_state(c_LED_OFF);
led_state_array(c_LED_NB_I2C) <= f_led_state(c_LED_COLOR_I2C) when i2c_up = '1' else
f_led_state(c_LED_RED);
led_state_array(c_LED_NB_WR_OK) <= f_led_state(c_LED_COLOR_WR_OK) when leds_array.middle.WR_OK = '1' else
f_led_state(c_LED_RED);
led_state_array(c_LED_NB_WR_LINK) <= f_led_state(c_LED_COLOR_WR_LINK) when leds_array.middle.WR_LINK = '1' else
f_led_state(c_LED_RED);
led_state_array(c_LED_NB_WR_GMT) <= f_led_state(c_LED_COLOR_WR_GMT) when leds_array.middle.WR_GMT = '1'else
f_led_state(c_LED_RED);
led_state_array(c_LED_NB_WR_ADDR) <= f_led_state(c_LED_COLOR_WR_ADDR) when leds_array.middle.WR_ADDR = '1' else
f_led_state(c_LED_RED);
led_state_array(c_LED_NB_MULTICAST3) <= f_led_state(c_LED_COLOR_MULTICAST3) when leds_array.bottom.MULTICAST(3) = '1' else
f_led_state(c_LED_OFF);
led_state_array(c_LED_NB_MULTICAST2) <= f_led_state(c_LED_COLOR_MULTICAST2) when leds_array.bottom.MULTICAST(2) = '1' else
f_led_state(c_LED_OFF);
led_state_array(c_LED_NB_MULTICAST1) <= f_led_state(c_LED_COLOR_MULTICAST1) when leds_array.bottom.MULTICAST(1) = '1' else
f_led_state(c_LED_OFF);
led_state_array(c_LED_NB_MULTICAST0) <= f_led_state(c_LED_COLOR_MULTICAST0) when leds_array.bottom.MULTICAST(0) = '1' else
f_led_state(c_LED_OFF);
cmp_bicolor_led_ctrl: bicolor_led_ctrl
generic map
(
g_NB_COLUMN => c_NB_COLUMN,
......@@ -577,10 +568,10 @@ begin
)
port map
(
rst_n_i => s_rst_n,
clk_i => clk_20MHz_i,
rst_n_i => rst_n,
clk_i => clk_20_i,
led_intensity_i => c_LED_INTENSITY,
led_state_i => f_STD_LOGIC_VECTOR(s_led_state_array),
led_state_i => f_STD_LOGIC_VECTOR(led_state_array),
column_o(0) => led_array_o.WR_OWNADDR_I2C,
column_o(1) => led_array_o.WR_GMT_TTL_TTLN,
column_o(2) => led_array_o.WR_LINK_SYSERROR,
......@@ -593,13 +584,4 @@ begin
line_oen_o(1) => led_array_o.CTRL1_OEN
);
inst_rtm_detector: rtm_detector
port map
(
RTMM_i => rtm_i.RTMM_N,
RTMP_i => rtm_i.RTMP_N,
ok_RTMM_o => s_ok_RTMM,
ok_RTMP_o => s_ok_RTMP
);
end Behavioral;
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ cf33831c
......@@ -153,46 +153,46 @@ package image1_pkg is
end component;
component i2c_slave_top
generic(g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns
port(sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_master_we_o : out STD_LOGIC;
wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_we_i : in STD_LOGIC;
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
pf_wb_addr_o : out STD_LOGIC;
rd_done_o : out STD_LOGIC;
wr_done_o : out STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
);
end component;
-- component i2c_slave_top
-- generic(g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns
-- port(sda_oen : out STD_LOGIC;
-- sda_i : in STD_LOGIC;
-- sda_o : out STD_LOGIC;
-- scl_oen : out STD_LOGIC;
-- scl_i : in STD_LOGIC;
-- scl_o : out STD_LOGIC;
--
-- wb_clk_i : in STD_LOGIC;
-- wb_rst_i : in STD_LOGIC;
--
-- wb_master_stb_o : out STD_LOGIC;
-- wb_master_cyc_o : out STD_LOGIC;
-- wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
-- wb_master_we_o : out STD_LOGIC;
-- wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
-- wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
-- wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
-- wb_master_ack_i : in STD_LOGIC;
-- wb_master_rty_i : in STD_LOGIC;
-- wb_master_err_i : in STD_LOGIC;
--
-- wb_slave_stb_i : in STD_LOGIC;
-- wb_slave_cyc_i : in STD_LOGIC;
-- wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
-- wb_slave_we_i : in STD_LOGIC;
-- wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
-- wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
-- wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
-- wb_slave_ack_o : out STD_LOGIC;
-- wb_slave_rty_o : out STD_LOGIC;
-- wb_slave_err_o : out STD_LOGIC;
--
-- pf_wb_addr_o : out STD_LOGIC;
-- rd_done_o : out STD_LOGIC;
-- wr_done_o : out STD_LOGIC;
-- i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
-- );
-- end component;
component m25p32_top
generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
......@@ -242,14 +242,14 @@ package image1_pkg is
wb_err_o : out STD_LOGIC);
end component;
component rtm_detector
generic(g_identifier_RTMM : t_RTMM := RTMM_V1;
g_identifier_RTMP : t_RTMP := RTMP_BLOCKING_V1);
port (RTMM_i : in STD_LOGIC_VECTOR(2 downto 0);
RTMP_i : in STD_LOGIC_VECTOR(2 downto 0);
ok_RTMM_o : out STD_LOGIC;
ok_RTMP_o : out STD_LOGIC);
end component;
-- component rtm_detector
-- generic(g_identifier_RTMM : t_RTMM := RTMM_V1;
-- g_identifier_RTMP : t_RTMP := RTMP_BLOCKING_V1);
-- port (RTMM_i : in STD_LOGIC_VECTOR(2 downto 0);
-- RTMP_i : in STD_LOGIC_VECTOR(2 downto 0);
-- ok_RTMM_o : out STD_LOGIC;
-- ok_RTMP_o : out STD_LOGIC);
-- end component;
-- function check_sys_cfg return BOOLEAN;
......
hdl/IMAGES/image1/test/image1_top_tb.vhd
View file @ cf33831c
......@@ -56,7 +56,8 @@ architecture behavior of image1_top_tb is
signal switch_i : STD_LOGIC_VECTOR(1 downto 1);
signal manual_rst_n_o : STD_LOGIC;
signal s_RTM_id_i : t_RTM_id := c_RTM_id_default;
signal rtmp, rtmm : std_logic_vector(2 downto 0);
--! ========================================================================
--! Signals for the i2c_master_driver (Renesasa alike)
--! ========================================================================
......@@ -215,6 +216,8 @@ begin
write_done_o => s_i2c_driver_ctrl_done.WRITE,
read_done_o => s_i2c_driver_ctrl_done.READ);
rtmm <= "001";
rtmp <= "000";
uut: image1_top
-- generic map(g_NUMBER_OF_CHANNELS => work.image1_top_tb_pkg.c_NUMBER_OF_CHANNELS)
port map(RST_N => s_RST_N,
......@@ -258,8 +261,9 @@ begin
LEVEL => level,
EXTRA_SWITCH => switch_i,
MR_N => manual_rst_n_o,
FPGA_RTMM_N => s_RTM_id_i.RTMM,
FPGA_RTMP_N => s_RTM_id_i.RTMP);
fpga_rtmm_n_i => rtmm,
fpga_rtmp_n_i => rtmp
);
--! Stimulus process
......
hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
View file @ cf33831c
......@@ -70,8 +70,8 @@ package image1_top_tb_pkg is
MR_N : out STD_LOGIC;--! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM_N : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP_N : in STD_LOGIC_VECTOR(2 downto 0));
FPGA_RTMM_N_i : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP_N_i : in STD_LOGIC_VECTOR(2 downto 0));
end component;
type t_pulse_vector is
......
hdl/IMAGES/image1/top/image1_top.vhd
View file @ cf33831c
......@@ -30,7 +30,6 @@
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library IEEE;
library unisim;
library work;
......@@ -49,57 +48,62 @@ entity image1_top is
);
port
(
RST_N : in STD_LOGIC;
CLK20_VCXO : in STD_LOGIC;
FPGA_CLK_P : in STD_LOGIC; --Using the 125MHz clock
FPGA_CLK_N : in STD_LOGIC;
--! LEDs
LED_CTRL0 : out STD_LOGIC;
LED_CTRL0_OEN : out STD_LOGIC;
LED_CTRL1 : out STD_LOGIC;
LED_CTRL1_OEN : out STD_LOGIC;
LED_MULTICAST_2_0 : out STD_LOGIC;
LED_MULTICAST_3_1 : out STD_LOGIC;
LED_WR_GMT_TTL_TTLN : out STD_LOGIC;
LED_WR_LINK_SYSERROR : out STD_LOGIC;
LED_WR_OK_SYSPW : out STD_LOGIC;
LED_WR_OWNADDR_I2C : out STD_LOGIC;
--! I/Os for pulses
PULSE_FRONT_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
PULSE_REAR_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_INPUT_TTL_N : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_OUT_TTL : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_BLO_IN : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_TRIG_BLO : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
INV_IN_N : in STD_LOGIC_VECTOR(4 downto 1);
INV_OUT : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_OE : out STD_LOGIC;
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_OE : out STD_LOGIC;
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
--! Pins of the SPI interface to write into the Flash memory
FPGA_PROM_CCLK : out STD_LOGIC;
FPGA_PROM_CSO_B_N : out STD_LOGIC;
FPGA_PROM_DIN : in STD_LOGIC;
FPGA_PROM_MOSI : out STD_LOGIC;
--! RTM identifiers, should match with the expected values
--! TODO: add matching
FPGA_OE : out STD_LOGIC;
FPGA_BLO_OE : out STD_LOGIC;
FPGA_TRIG_TTL_OE : out STD_LOGIC;
FPGA_INV_OE : out STD_LOGIC;
LEVEL : in STD_LOGIC;--!TTL/INV_TTL_N
EXTRA_SWITCH : in STD_LOGIC_VECTOR(1 downto 1);--! General enable
MR_N : out STD_LOGIC;--! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM_N : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP_N : in STD_LOGIC_VECTOR(2 downto 0)
rst_i : in std_logic;
CLK20_VCXO : in std_logic;
FPGA_CLK_P : in std_logic; --Using the 125MHz clock
FPGA_CLK_N : in std_logic;
-- LEDs
LED_CTRL0 : out std_logic;
LED_CTRL0_OEN : out std_logic;
LED_CTRL1 : out std_logic;
LED_CTRL1_OEN : out std_logic;
LED_MULTICAST_2_0 : out std_logic;
LED_MULTICAST_3_1 : out std_logic;
LED_WR_GMT_TTL_TTLN : out std_logic;
LED_WR_LINK_SYSERROR : out std_logic;
LED_WR_OK_SYSPW : out std_logic;
LED_WR_OWNADDR_I2C : out std_logic;
-- I/Os for pulses
PULSE_FRONT_LED_N : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
PULSE_REAR_LED_N : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
FPGA_INPUT_TTL_N : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
FPGA_OUT_TTL : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
FPGA_BLO_IN : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
FPGA_TRIG_BLO : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
INV_IN_N : in std_logic_vector(4 downto 1);
INV_OUT : out std_logic_vector(4 downto 1);
-- Lines for the i2c_slave
SCL_I : in std_logic;
SCL_O : out std_logic;
SCL_OE : out std_logic;
SDA_I : in std_logic;
SDA_O : out std_logic;
SDA_OE : out std_logic;
FPGA_GA : in std_logic_vector(4 downto 0);
FPGA_GAP : in std_logic;
-- Pins of the SPI interface to write into the Flash memory
FPGA_PROM_CCLK : out std_logic;
FPGA_PROM_CSO_B_N : out std_logic;
FPGA_PROM_DIN : in std_logic;
FPGA_PROM_MOSI : out std_logic;
FPGA_OE : out std_logic;
FPGA_BLO_OE : out std_logic;
FPGA_TRIG_TTL_OE : out std_logic;
FPGA_INV_OE : out std_logic;
LEVEL : in std_logic;--TTL/INV_TTL_N
EXTRA_SWITCH : in std_logic_vector(1 downto 1);--! General enable
MR_N : out std_logic;-- It allows power sequencing of the
-- 24V rail after a security given delay
-- RTM identifiers, should match with the expected values
-- TODO: add matching
fpga_rtmm_n_i : in std_logic_vector(2 downto 0);
fpga_rtmp_n_i : in std_logic_vector(2 downto 0)
);
end image1_top;
......@@ -110,59 +114,60 @@ architecture Behavioral of image1_top is
generic
(
g_NUMBER_OF_CHANNELS : NATURAL := 6
);
port
); port
(
rst_n : in STD_LOGIC;
clk_20MHz_i : in STD_LOGIC;
clk_125MHz_i : in STD_LOGIC;
--! LEDs
rst_i : in std_logic;
clk_20_i : in std_logic;
clk_125_i : in std_logic;
-- LEDs
led_array_o : out t_led_array_o;
--! I/Os for pulses
led_front_n : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_rear_n : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_front_n : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i_n : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
-- I/Os for pulses
led_front_n : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
led_rear_n : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_front_n : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
inv_i_n : in std_logic_vector(4 downto 1);
inv_o : out std_logic_vector(4 downto 1);
-- Lines for the i2c_slave
i2c_slave_i : in t_i2c_slave_i;
i2c_slave_o : out t_i2c_slave_o;
--! FPGA Geographical address pins (reused for i2c address)
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
--! Pins of the SPI interface to write into the Flash memory
-- FPGA Geographical address pins (reused for i2c address)
FPGA_GA : in std_logic_vector(4 downto 0);
FPGA_GAP : in std_logic;
-- Pins of the SPI interface to write into the Flash memory
spi_master_i : in t_spi_master_i;
spi_master_o : out t_spi_master_o;
--! RTM identifiers, should match with the expected values
--! TODO: add matching
fpga_o_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
level_i : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
rtm_i : in t_rtm_i
-- RTM identifiers, should match with the expected values
-- TODO: add matching
fpga_o_en : out std_logic;
fpga_o_blo_en : out std_logic;
fpga_o_ttl_en : out std_logic;
fpga_o_inv_en : out std_logic;
level_i : in std_logic;
switch_i : in std_logic; -- General enable
manual_rst_n_o : out std_logic; -- It allows power sequencing of the
-- 24V rail after a security given delay
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0)
);
end component;
signal s_clk_125MHz : STD_LOGIC;
signal clk_125 : std_logic;
signal s_led_array : t_led_array_o := c_led_array_default;
signal s_i2c_slave_i : t_i2c_slave_i;
signal s_i2c_slave_o : t_i2c_slave_o;
signal s_spi_master_i : t_spi_master_i;
signal s_spi_master_o : t_spi_master_o;
signal s_rtm_i : t_rtm_i;
signal s_switch_i : STD_LOGIC_VECTOR(1 downto 1);
signal s_switch_i : std_logic_vector(1 downto 1);
signal rtmm, rtmp : std_logic_vector(2 downto 0);
begin
inst_125m_IBUFGDS : IBUFGDS
cmp_125_diff_buf: IBUFGDS
generic map
(
DIFF_TERM => TRUE,
......@@ -172,7 +177,7 @@ begin
(
I => FPGA_CLK_P,
IB => FPGA_CLK_N,
O => s_clk_125MHz
O => clk_125
);
LED_CTRL0 <= s_led_array.CTRL0;
......@@ -198,18 +203,18 @@ begin
FPGA_PROM_CSO_B_N <= s_spi_master_o.CSO_B_N;
FPGA_PROM_MOSI <= s_spi_master_o.MOSI;
s_rtm_i.RTMM_N <= FPGA_RTMM_N;
s_rtm_i.RTMP_N <= fpga_rtmp_n;
rtmm <= not fpga_rtmm_n_i;
rtmp <= not fpga_rtmp_n_i;
s_switch_i <= EXTRA_SWITCH;
inst_image1_core: image1_core
cmp_image1_core: image1_core
generic map(g_NUMBER_OF_CHANNELS => 6)
port map
(
rst_n => RST_N,
clk_20MHz_i => CLK20_VCXO,
clk_125MHz_i => s_clk_125MHz,
rst_i => rst_i,
clk_20_i => CLK20_VCXO,
clk_125_i => clk_125,
led_array_o => s_led_array,
led_front_n => PULSE_FRONT_LED_N,
led_rear_n => PULSE_REAR_LED_N,
......@@ -232,7 +237,8 @@ begin
level_i => LEVEL,
switch_i => s_switch_i(1),
manual_rst_n_o => MR_N,
rtm_i => s_rtm_i
rtmm_i => rtmm,
rtmp_i => rtmp
);
end Behavioral;
hdl/basic_trigger/rtl/basic_trigger_core.vhd
View file @ cf33831c
......@@ -26,9 +26,9 @@ use work.ctdah_pkg.ALL;
entity basic_trigger_core is
generic
(
g_CLK_PERIOD : TIME;
g_OUTPUT_PULSE_LENGTH : TIME;
g_LED_BLINKING_LENGTH : TIME
g_clk_period : TIME;
g_output_pulse_length : TIME;
g_led_blinking_length : TIME
);
port
(
......@@ -51,7 +51,7 @@ architecture Behavioral of basic_trigger_core is
-- return natural is
-- variable v : natural;
-- begin
-- v := g_OUTPUT_PULSE_LENGTH/g_CLK_PERIOD;
-- v := g_output_pulse_length/g_clk_period;
-- report "pulse length: " & integer'image(v);
-- return v;
-- end pulselen;
......@@ -60,13 +60,13 @@ architecture Behavioral of basic_trigger_core is
-- return natural is
-- variable v : natural;
-- begin
-- v := g_LED_BLINKING_LENGTH/g_CLK_PERIOD;
-- v := g_led_blinking_length/g_clk_period;
-- report "LED length: " & integer'image(v);
-- return v;
-- end ledlen;
constant c_PULSE_LENGTH : NATURAL := g_OUTPUT_PULSE_LENGTH/g_CLK_PERIOD;
constant c_LED_LENGTH : NATURAL := g_LED_BLINKING_LENGTH/g_CLK_PERIOD;
constant c_PULSE_LENGTH : NATURAL := g_output_pulse_length/g_clk_period;
constant c_LED_LENGTH : NATURAL := g_led_blinking_length/g_clk_period;
signal s_pulse : STD_LOGIC;
......
hdl/basic_trigger/rtl/basic_trigger_top.vhd
View file @ cf33831c
......@@ -31,143 +31,166 @@ use UNISIM.VCOMPONENTS.ALL;
entity basic_trigger_top is
generic
(
g_NUMBER_OF_CHANNELS : NATURAL := 6;
g_CLK_PERIOD : TIME := 20 ns;
g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns
g_number_of_channels : natural := 6;
g_clk_period : time := 20 ns;
g_pulse_length : time := 1000 ns;
g_led_blinking_length : time := (10**6)*250 ns
);
port
(
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level_i : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1)
clk_i : in std_logic;
rst_i : in std_logic;
led_ttl_o : out std_logic;
-- Enable signals
fpga_o_en : out std_logic;
fpga_o_ttl_en : out std_logic;
fpga_o_inv_en : out std_logic;
fpga_o_blo_en : out std_logic;
level_i : in std_logic;
switch_i : in std_logic;
-- The manual reset allows power sequencing of the
-- 24V rail after a security given delay
manual_rst_n_o : out std_logic;
-- Front and rear pulse signals
pulse_i_front : in std_logic_vector(g_number_of_channels downto 1);
pulse_o_front : out std_logic_vector(g_number_of_channels downto 1);
pulse_i_rear : in std_logic_vector(g_number_of_channels downto 1);
pulse_o_rear : out std_logic_vector(g_number_of_channels downto 1);
-- Front and rear LED signals
led_o_front : out std_logic_vector(g_number_of_channels downto 1);
led_o_rear : out std_logic_vector(g_number_of_channels downto 1);
-- Inverting inputs and outputs
inv_i : in std_logic_vector(4 downto 1);
inv_o : out std_logic_vector(4 downto 1)
);
end basic_trigger_top;
architecture Behavioral of basic_trigger_top is
signal s_pulse_i : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_i_front : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_o : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_n_o : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_led : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_crop : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1) := (others => '0');
signal s_level : STD_LOGIC;
signal s_fpga_o_en : STD_LOGIC;
signal s_fpga_o_ttl_en : STD_LOGIC;
signal s_fpga_o_inv_en : STD_LOGIC;
signal s_fpga_o_blo_en : STD_LOGIC;
type delay_array is array (g_NUMBER_OF_CHANNELS downto 1) of STD_LOGIC_VECTOR(3 downto 0);
signal s_pulse_i_reg : delay_array;
--============================================================================
-- Component declarations
--============================================================================
component basic_trigger_core is
generic
(
g_CLK_PERIOD : TIME := g_CLK_PERIOD;
g_OUTPUT_PULSE_LENGTH : TIME := g_OUTPUT_PULSE_LENGTH;
g_LED_BLINKING_LENGTH : TIME := g_LED_BLINKING_LENGTH
g_clk_period : time;
g_output_pulse_length : time;
g_led_blinking_length : time
);
port
(
wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_rst_i : in std_logic;
wb_clk_i : in std_logic;
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
pulse_n_o : out STD_LOGIC;
pulse_i : in std_logic;
pulse_o : out std_logic;
pulse_n_o : out std_logic;
crop_o : out STD_LOGIC;
crop_o : out std_logic;
led_o : out STD_LOGIC
led_o : out std_logic
);
end component;
--============================================================================
-- Signal declarations
--============================================================================
signal pulse_in : std_logic_vector(g_number_of_channels downto 1);
signal pulse_in_front : std_logic_vector(g_number_of_channels downto 1);
signal pulse_out : std_logic_vector(g_number_of_channels downto 1);
signal pulse_out_n : std_logic_vector(g_number_of_channels downto 1);
signal led : std_logic_vector(g_number_of_channels downto 1);
signal crop : std_logic_vector(g_number_of_channels downto 1) := (others => '0');
signal level : std_logic;
signal fpga_out_en : std_logic;
signal fpga_out_ttl_en : std_logic;
signal fpga_out_inv_en : std_logic;
signal fpga_out_blo_en : std_logic;
-- type delay_array is array (g_number_of_channels downto 1) of std_logic_vector(3 downto 0);
-- signal pulse_in_reg : delay_array;
begin
--! level_i 0 means TTL Switch UP
--! 1 means TTL_N Switch DOWN
s_level <= level_i;
led_ttl_o <= s_level;
-- Level selection via on-board switch:
-- +---------+-----------------+
-- | level_i | Switch | Level |
-- +---------+---------+-------+
-- | 0 TTL | UP | TTL |
-- | 1 TTL_N | DOWN | TTL_N |
-- +---------+---------+-------+
level <= level_i;
led_ttl_o <= level;
-- pulse signal assignments
s_pulse_i_front <= pulse_i_front when (s_level = '0') else
not pulse_i_front;
s_pulse_i <= s_pulse_i_front or pulse_i_rear;
fpga_o_en <= s_fpga_o_en when (switch_i = '0') else '0';
fpga_o_ttl_en <= s_fpga_o_ttl_en;
fpga_o_inv_en <= s_fpga_o_inv_en;
fpga_o_blo_en <= s_fpga_o_blo_en;
led_o_front <= not(s_led); --! No need of accurate sync, hence we place
led_o_rear <= not(s_led); --! some combinatorial here.
pulse_o_front <= s_pulse_o when s_level = '0' else
not s_pulse_o;
pulse_o_rear <= s_pulse_o;
--! As we have one Schmitt inverter in the input,
--! and a buffer in the output, there's no need
--! to invert here.
inv_o <= inv_i;
pulse_in_front <= pulse_i_front when (level = '0') else
not pulse_i_front;
pulse_in <= pulse_in_front or pulse_i_rear;
fpga_o_en <= fpga_out_en when (switch_i = '0') else '0';
fpga_o_ttl_en <= fpga_out_ttl_en;
fpga_o_inv_en <= fpga_out_inv_en;
fpga_o_blo_en <= fpga_out_blo_en;
led_o_front <= not(led); -- No need of accurate sync, hence we place
led_o_rear <= not(led); -- some combinatorial here.
pulse_o_front <= pulse_out when level = '0' else
not pulse_out;
pulse_o_rear <= pulse_out;
-- As we have one Schmitt inverter in the input,
-- and a buffer in the output, there's no need
-- to invert here.
inv_o <= inv_i;
gen_trig_cores: for i in 1 to g_NUMBER_OF_CHANNELS generate
gen_trig_cores: for i in 1 to g_number_of_channels generate
trigger: basic_trigger_core
generic map
(
g_clk_period => g_clk_period,
g_output_pulse_length => g_pulse_length,
g_led_blinking_length => g_led_blinking_length
)
port map
(
wb_rst_i => rst_i,
wb_clk_i => clk_i,
pulse_i => s_pulse_i(i),
pulse_o => s_pulse_o(i),
pulse_n_o => s_pulse_n_o(i),
pulse_i => pulse_in(i),
pulse_o => pulse_out(i),
pulse_n_o => pulse_out_n(i),
crop_o => open,
led_o => s_led(i)
led_o => led(i)
);
end generate gen_trig_cores;
--! @brief Process to lock the enables so to avoid output glitches
--! on the startup.
--! @param clk_i Main clock used in this clock domain.
-- Process to lock the enables so to avoid output glitches
-- on the startup.
p_reset_chain : process(clk_i) is
begin
if rising_edge(clk_i) then
if rst_i = '1' then
--! First we reset the FPGA general output enable
--! Then we let one clock delay for the rest of signals
if (rst_i = '1') then
-- First we reset the FPGA general output enable
-- Then we let one clock delay for the rest of signals
manual_rst_n_o <= '0';
s_fpga_o_en <= '0';
s_fpga_o_ttl_en <= '0';
s_fpga_o_inv_en <= '0';
s_fpga_o_blo_en <= '0';
fpga_out_en <= '0';
fpga_out_ttl_en <= '0';
fpga_out_inv_en <= '0';
fpga_out_blo_en <= '0';
else
manual_rst_n_o <= '1';
s_fpga_o_en <= '1';
s_fpga_o_ttl_en <= s_fpga_o_en;
s_fpga_o_inv_en <= s_fpga_o_en;
s_fpga_o_blo_en <= s_fpga_o_en;
fpga_out_en <= '1';
fpga_out_ttl_en <= fpga_out_en;
fpga_out_inv_en <= fpga_out_en;
fpga_out_blo_en <= fpga_out_en;
end if;
end if;
end process p_reset_chain;
......
hdl/rtm_detector/rtl/rtm_detector.vhd
View file @ cf33831c
--==============================================================================
-- CERN (BE-CO-HT)
-- Rear transition module (RTM) detector
--==============================================================================
--
-- author: Carlos Gil Soriano
-- Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-01-09
--
-- version: 2.0
--
-- description:
--
-- This module detects the presence of rear transition module motherboards
-- (RTMMs) and piggybacks (RTMPs). Detection works by checking the RTMM and
-- RTMP input pins and these pins are pulled up on the front module. The
-- RTMM_OK and RTMP_OK ouputs are set if the corresponding inputs do not
-- yield errors. Different boards have the RTMM/P pins setup differently,
-- as outlined in the tables below:
--
-- Table 1. RTMM detection pins.
-- __________________________________________
-- | Board | RTMM[2] | RTMM[1] | RTMM[0] |
-- +-----------------------------------------+
-- | Error | '1' | '1' | '1' |
-- | RTMM_V1 | '1' | '1' | '0' |
-- | RTMM_V2 | '1' | '0' | '1' |
-- | Reserved | '1' | '0' | '0' |
-- | Reserved | '0' | '1' | '1' |
-- | Reserved | '0' | '1' | '0' |
-- | Reserved | '0' | '0' | '1' |
-- | Reserved | '0' | '0' | '0' |
-- +-----------+---------+---------+---------+
--
--
-- Table 2. RTMP detection pins.
-- _____________________________________________
-- | Board | RTMP[2] | RTMP[1] | RTMP[0] |
-- +-------------------------------------------+
-- | Error OR | '1' | '1' | '1' |
-- | Blocking_V1 | | | |
-- | RS485_V1 | '1' | '1' | '0' |
-- | -Reserved- | '1' | '0' | '1' |
-- | -Reserved- | '1' | '0' | '0' |
-- | -Reserved- | '0' | '1' | '1' |
-- | -Reserved- | '0' | '1' | '0' |
-- | -Reserved- | '0' | '0' | '1' |
-- | Error | '0' | '0' | '0' |
-- +-------------+---------+---------+---------+
--
--
-- dependencies:
-- none
--
-- references:
-- http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-01-09 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.rtm_detector_pkg.ALL;
--use work.rtm_detector_pkg.ALL;
entity rtm_detector is
generic(g_identifier_RTMM : t_RTMM;
g_identifier_RTMP : t_RTMP);
port (RTMM_i : in STD_LOGIC_VECTOR(2 downto 0);
RTMP_i : in STD_LOGIC_VECTOR(2 downto 0);
ok_RTMM_o : out STD_LOGIC;
ok_RTMP_o : out STD_LOGIC);
end rtm_detector;
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end entity rtm_detector;
architecture Behavioral of rtm_detector is
signal s_identifier_RTMM : UNSIGNED(2 downto 0)
:= f_UNSIGNED(g_identifier_RTMM);
signal s_identifier_RTMP : UNSIGNED(2 downto 0)
:= f_UNSIGNED(g_identifier_RTMP);
signal s_RTMM : UNSIGNED(2 downto 0);
signal s_RTMP : UNSIGNED(2 downto 0);
-- signal s_identifier_rtmm : unsigned(2 downto 0) := f_unsigned(g_identifier_rtmm);
-- signal s_identifier_rtmp : unsigned(2 downto 0) := f_unsigned(g_identifier_rtmp);
-- signal s_rtmm : unsigned(2 downto 0);
-- signal s_rtmp : unsigned(2 downto 0);
begin
s_RTMM <= UNSIGNED(RTMM_i);
s_RTMP <= UNSIGNED(RTMP_i);
rtmm_ok_o <= '0' when (rtmm_i = "111") else '1';
rtmp_ok_o <= '0' when (rtmp_i = "111") else '1';
ok_RTMM_o <= '1' when s_RTMM = s_identifier_RTMM
else '0';
ok_RTMP_o <= '1' when s_RTMP = s_identifier_RTMP
else '0';
-- s_rtmm <= unsigned(rtmm_i);
-- s_rtmp <= unsigned(rtmp_i);
--
-- ok_rtmm_o <= '1' when s_rtmm = s_identifier_rtmm else '0';
-- ok_rtmp_o <= '1' when s_rtmp = s_identifier_rtmp else '0';
end Behavioral;
hdl/rtm_detector/rtl/rtm_detector_pkg.vhd
View file @ cf33831c
......@@ -4,44 +4,6 @@ use IEEE.NUMERIC_STD.ALL;
package rtm_detector_pkg is
--! Please refer to:
--! http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection
--! to see conventions used to guarantee consistency between front board
--! and read transition modules
--! It should be noted that the RTMM, and RTMP pins are pulled up in
--! all the Front boards.
--! On 27/Nov/2012 the correspondencies are:
--!
--! __________________________________________
--! | Board | RTMM[2] | RTMM[1] | RTMM[0] |
--! +-----------------------------------------+
--! | Error | '1' | '1' | '1' |
--! | RTMM_V1 | '1' | '1' | '0' |
--! | Reserved0 | '1' | '0' | '1' |
--! | Reserved1 | '1' | '0' | '0' |
--! | Reserved2 | '0' | '1' | '1' |
--! | Reserved3 | '0' | '1' | '0' |
--! | Reserved4 | '0' | '0' | '1' |
--! | Reserved5 | '0' | '0' | '0' |
--! +-----------+---------+---------+---------+
--!
--! _____________________________________________
--! | Board | RTMP[2] | RTMP[1] | RTMP[0] |
--! +-------------------------------------------+
--! | Error | '1' | '1' | '1' |
--! | Blocking_V1 | '1' | '1' | '0' |
--! | RS485_V1 | '1' | '0' | '1' |
--! | Reserved0 | '1' | '0' | '0' |
--! | Reserved1 | '0' | '1' | '1' |
--! | Reserved2 | '0' | '1' | '0' |
--! | Reserved3 | '0' | '0' | '1' |
--! | Reserved4 | '0' | '0' | '0' |
--! +-------------+---------+---------+---------+
--!
--! It should be noted that there is an inverter before the FPGA,
--! so the signals/constant will be negated in rtm_detector.vhd
type t_RTMM is (RTMM_ERROR,
RTMM_V1,
RESERVED0,
......
installation/V2/dummy/constraints/BloV2.ucf
View file @ cf33831c
......@@ -7,8 +7,8 @@
###----------------------------------------
#
#
#NET "RST_N" LOC = N20;
# NET "RST_N" IOSTANDARD = "LVCMOS33";
NET "RST_N" LOC = N20;
NET "RST_N" IOSTANDARD = "LVCMOS33";
#NET "FPGA_SYSRESET_N" LOC = L20;
# NET "FPGA_SYSRESET_N" IOSTANDARD = "LVCMOS33";
#NET "MR_N" LOC = T22;
......
installation/V2/dummy/project/dummy.gise
View file @ cf33831c
......@@ -22,9 +22,174 @@
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="dummy_top_envsettings.html"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="dummy_top_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="dummy_top_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="dummy_top_summary.xml"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
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<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361461338" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1361461338">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361461338" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1922430530514574527" xil_pn:start_ts="1361461338">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361461338" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1361461338">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361461338" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-28695541088094260" xil_pn:start_ts="1361461338">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361526588" xil_pn:in_ck="8395426835488392827" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8773670417354495131" xil_pn:start_ts="1361526579">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="dummy_top.lso"/>
<outfile xil_pn:name="dummy_top.ngc"/>
<outfile xil_pn:name="dummy_top.ngr"/>
<outfile xil_pn:name="dummy_top.prj"/>
<outfile xil_pn:name="dummy_top.stx"/>
<outfile xil_pn:name="dummy_top.syr"/>
<outfile xil_pn:name="dummy_top.xst"/>
<outfile xil_pn:name="dummy_top_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1361461347" xil_pn:in_ck="5140566070660021827" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-8176852928571196330" xil_pn:start_ts="1361461347">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361526593" xil_pn:in_ck="-3428321779339669433" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-3420677949626786771" xil_pn:start_ts="1361526588">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="dummy_top.bld"/>
<outfile xil_pn:name="dummy_top.ngd"/>
<outfile xil_pn:name="dummy_top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1361526614" xil_pn:in_ck="-3428321779339669432" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1361526593">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="dummy_top.pcf"/>
<outfile xil_pn:name="dummy_top_map.map"/>
<outfile xil_pn:name="dummy_top_map.mrp"/>
<outfile xil_pn:name="dummy_top_map.ncd"/>
<outfile xil_pn:name="dummy_top_map.ngm"/>
<outfile xil_pn:name="dummy_top_map.xrpt"/>
<outfile xil_pn:name="dummy_top_summary.xml"/>
<outfile xil_pn:name="dummy_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1361526639" xil_pn:in_ck="-1058796387014212767" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1361526614">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="dummy_top.ncd"/>
<outfile xil_pn:name="dummy_top.pad"/>
<outfile xil_pn:name="dummy_top.par"/>
<outfile xil_pn:name="dummy_top.ptwx"/>
<outfile xil_pn:name="dummy_top.unroutes"/>
<outfile xil_pn:name="dummy_top.xpi"/>
<outfile xil_pn:name="dummy_top_pad.csv"/>
<outfile xil_pn:name="dummy_top_pad.txt"/>
<outfile xil_pn:name="dummy_top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1361526657" xil_pn:in_ck="6853856633696009377" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1361526639">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="dummy_top.bgn"/>
<outfile xil_pn:name="dummy_top.bit"/>
<outfile xil_pn:name="dummy_top.drc"/>
<outfile xil_pn:name="dummy_top.ut"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1361463463" xil_pn:in_ck="6853856633695996523" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="2682241697568822907" xil_pn:start_ts="1361463463">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1361526660" xil_pn:in_ck="6853856633695996523" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1361526657">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361526639" xil_pn:in_ck="-3428321779339669564" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1361526632">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="dummy_top.twr"/>
<outfile xil_pn:name="dummy_top.twx"/>
</transform>
</transforms>
</generated_project>
installation/V2/dummy/project/dummy.xise
View file @ cf33831c
......@@ -318,6 +318,7 @@
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="impact.ipf" xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
......
installation/V2/dummy/project/dummy_top_guide.ncd
View file @ cf33831c
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
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DMI4+M8CgFZogqS/aYJV/jPEDfFIG6QahC5w/RvPl+p5ow4XgJ/FZEB80MBMA0wlqJcSTS2U8TdwTxWob6EufwPZGaBuYaGUvyHCr1wjuj/wylIZmlOH5shhqHGp+HSHsNDFOOSwctFQVcZGDMdNJVoqVAjGkyc96Z6rwHiSI60KYyM8wdH48a7QIQF1GD9ysFQPFoio8SP7LmljItwQ8Tp8NYtv4GiSuFAMlOs3cPKqPiWo3s4bN+NqSBJUr/lN/YoFCNsMOoZtFlhcLRkotwk76Cfs9HOEDa/4zxH2xq2+mrer/PO83b+BaJe4v3YD5X20WXw9h2NJLH+Rw3uDKb+Fw/3vxOHFkxxeemGehqUf5llYBmGeh2Uagv4THN4sEu/7c7gkg69m5/R7sXNNkkXNzmnNzi5qmiQ7Vw07BzWdpYadG7IsQrcCiquEC48Y74aYPWyhDTF7joU2xMxKC22IuWhAi5j9Oipf02BRE7OrXUui9WWLJGYs35m2aYhZbR6JMsuTImbN5FVhPGXSxjU2DTErTpAotTwpatYDA65pPKneibFpuDkghptlg6RcashZ9itB1yZnX4PMJudUk3NWdcgZd8g5/X8i504uXX4LJ+ffh5PL6ls4ufxOnOx8PSejkn0fTs6qpzk5C/MyLPMwr8IiDbMyLLIQ9P8TOBl9PSej0v8rnNzlYuUQdr7Yl2KnCmCHi6FJcjHSXIxKzWBC13Bx0WgbLnYr491wsVtaqOFi10IbLvaohdZcnBm3DRer1SWj0gwqh9TmYkfxnhiRTJJL19hYXFzWbFhanlpcXFbGk+LiwthYXJzXaG55anFxWRpPqvfM2Jg8GdtcnCuG9YnNxTpR9qnhYjksCbqGi+VbU4ky6XAx6XBxtsPFn6Pg6nvmx/jruRiV6V/h4h7aI9/wbUN+kfmLHFz2cTD9Fg6uvlNeTJ7+tgHs64RFEeYoLMowx2FRhaD/n8DB7jdwcPWdvlooxyLFJJqLK9zJi4niYrfm4sqpL+fWV4uaH0HbcDEjxrv1wcLq0/pggSzU5MWOhTZ5sXFrcXFV82qlc1DS4WKqc1BSc3FpbMwHi7L++CA/J9Se2nkxMZ7kB4syMzYNFysukGhqeWrnxdh4Ur0HxsZwMTNcLBskw3rWRwvRrwR9m4srDQYWF1f1RwvExPf4XHyRJzUZU0XGapHl/76cWDGvVgq4oWD2DRRcfa9PFN63fGb+tk8U/wsj0UGf###5148:XlxV32DM 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ae8eNq9W0mWpDYQvZKkkAgon8MHyCTJZe+8que7WwOIEGgWzwu3IQnN/8eoUmqWH/WVq/xKlIsE/d+m3wVwmBlTs34GUIz9++8fiZ8f9iN//3D+/hHsr384f/2Iv/7mfPlZ8RcmeNnWUn3VrNsvatG/ScZI71+llNTfuP5VKT2KHonp57OdfvftnISyEvcZ6lnpt1VL2TWEY9qZS8VDmcRMWmZ9nwcAklHW2yrIl/gq9FzNbDlMuRUl1hHO4uPObj+vTZ8X7OclgvOaPr+6xSszmu1J/6u/FvdwatjDKbqHItjD1rXb1u7ETf927V+CVQjW/nn/AkaxqiIzFgSpPIpURZAaRwgbWJs0PLTf4IqmyxzyOGMEZ0nMK8iuw82let/23ty+xdev9nPjRaYKd64zI5hWwbnO4lfPsIRpqMT00oBpI7tFtRndoa1Tm6kiRvwuHuifOdklDHaJf391z+VdsmsL3/TTtvcvCLumAXYpwi5RZJeI698iukQRXaoa14rgWhR5FJ+xuvK1iclAmCwHNIubxcdqzYNdQHAzh+ySNeySVezK7FxCdotq4Bi74pqL53VQYadsa4ekwxeaJWHAEvpCMuULxfA0EwZAkQEQt55FBkCRAfWafU5Y8GUA04JgGgZOys3ic1g5e1KKYPrd4AUd7OCVFgOqd5AnztH63AMovXns80RQuoZ6+tuipx1/NqPRkjidvITD6SbXjF5HL5HWknMR1/0evnrIw8eyh+8YY/XsiJWPePgzEmxvHdge8/DVQx6+6vHw55lg+xusfXtdsU010X3GxmJjycLsEnnfOK3/1puXu0Z3WiZtQFw2hhNV0UcoHdEmA9qcE20uBk79EvvYU19OxANv8FDUI/6/Svr/atd2GRu+aztInIMY8QmdDj18QrtTL7JT0BADqMoY4H3yD0QhG5THMcYZNRIReeTIIV9bEiSrIr9FBb+xqF9y1rBhR71GO3z7leBBdjBnzLdXSd/+YA4rMoclNO8Ic6RnjvCWheQ5IcwxbKzFsrisC5S8+yNaNNxKaIe03zBV+A3gfeIRLqQylXEuQJELqVyJ9SMVWj8yEfFntGx8FNffyQWSGQVs4ML0SEwwpWICBbuHLdJY2T1skeDCMsSF5Tg9H0GYPOq071SYEeC4GTMionSwSZCswVPBVNtBvXhnGAbS7+CXPNaP8v3IDDmw4ggmfwQiVRgp7CxcnJc8PcD3l9uBg9aygtZQpPVD8/a0hkyIuWVGlJfApmJE2599NvRYSDoaXgE9lvevRkVJkYwFYFMqAPOKBIqKxEhMWqHZHUnuBpUoherNhiUMkO2+cmKCw6TNZ00lLrCrfIPF8o3KuKLYUsCon3NQOomee1Wppj9lIf2J8AEtHQngFkEY82ko4EyPBHBTZwEHBwo42F7AWUgiHr4NwdtUF7wtkpj1MHHE548ZAKJmHSu88RFf9VKT6DbHF69+wKxPnggwZNa9X1xB6VzVqE6FXKtUeeXVWx/DVEUvG9FRByYX0aViJbBmixG3haUV+znO3rJ/VsqTk1QUJOuIHsYi6amzSoZDVTLsqZItpP4gw2zdZ2sx4zM5bZHmD6kn5GtqxOjnou7MjRxsrUUNGONQB1XvWLFKF9cGVbVCe7qk+iChofqAj0TR+FBlDXsqawupPsgwm7bOqfovdt6Fw/JduEx1BYdrZfg/1srQY10OnFikVraQyoEM76wsLKe18ZFQDRtqZVPVOYTSMa6Paa/JV9wOzL8I5sOs2fZO5UWxs+KGQxU3HK644QMVN2yquOVuBdUwx6do8h5fR8j2JsxZGvwdfCRkw86aGw7V3LCn5rashCGvIYYkamKZtaak21Kv+FBtDR9MmY7V1rC7toa1tbXlQxjy7mDIWESA6dpa9m4lFu9WyuDucnvUy3wUfjCEVF4w9Ju4cBfnlNQdmAM/l8j3CyD+i/6/0KucwEi5pSW+24Xrdy2ntYFZrj0CHUJK3LdDAtoxbP6ZSrmW2vB/be7k6JORPn0/divebi42g+e+2JbByGY8ScY7Z0JHpr1NGam7zFdN+stH/yrdfE0bvQK27+esx1484d5W2vdjiWbWGH6P9haO7qS1RjhHmXzKxP5u5SVJyLhf0T1X9kGlF2DnL7qNBp7ZGx+mf0+ohVE6X98mxUWz8w7aBgdIr68UVE7orvvWMTmtMhBk6OLrHRU2CDKtwY/tJJUvXMp7VtLKgv8ek7X41LOmyDPtZmcUCIpcO9jJSn7X/R59n2MzO7baL/v5sTUK7vN0sov/XpKdfY0lJrv6VV1bYfUIy36RkciS0Cs1wkLSK6kQjO9u3aEZaEt/GrSVb6ONiv5Gvp5YNk/JXsvtvqqv54Z2XuN+d+Sfuvvsb01JmXeqwQ1vX6SmpkJ3k0tpiMtuxJUWBj5PUixRhjEHaR2T9NSFLAgnQl0gIIQssBiBIxA4Qgq65CY4la2DbsoP5s3QdW0yEOyBbR56PXBNQJVVQZVd329QJX9noy5/ZyPUr+4yDlR+BA5Fl1ZEgMqjbqmI2xgPz5tl2SvZOS0sIrJpAsizlTmAhJ6Mg23ew/DnwOZ6fBJsrsdnwDbvqYQWsJHKqVIXvchzepF1OjS+da1D4xfHGsAmrmCL5kIJMIkZrjHeOzA7jHcelL3GuwjMbuNdBGij8b6DtGy8SeFaXW4dz+ooLN9BKvcU+7zfMcmBFG4gvZY7vJwHKb+ByY14gJTvBcI4oOX+R31wADqQTQFPEslcwdLIulgQgnJlLD3qZOfw/kdQ6k3NxqbEaYlZP/8HZuIAwQ==###2164:XlxV32DM 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85ceNq9Ws2SpDYMfpl5AMuSbKAvU8llD3vIVpIH4Pc4VXNILtS8e2RDG8FAQ0NXdoti2/ok6+ezLXevRSCLaAzVlFNHOctDLRN3nKHhHBGdMYxsBckjsiMvKIzILugjaAtaM1mdaSUdQhCZkoq2IJiINy0+1un4eYsHdeLbBqSk4T5uF7bqLVT4LFgTs+aN+fr6oJIKU2D/AVAVDLd/AMrC3v4GyAswTY8ZlpKwmpgzauJELBM5zKUkmZgkmUDJVZI7ZqaAU+VMums49uyRRjJMOpDmG+SRAvJvG4ljHhDHYZaQHBI6oo+RJ2q/lDyDxVeSZ7D4GvIMtp4jDwt5gEf21DP2iMUexRXhj6ol5nEm0Zcstmg3F7SNmDOasODcM5pmVTNkUWJOmoOVbzw9HttMz47Zj3o7m1y+qkkr68lGfq57etdzC0/bcU3haf/gUP7Wqu1Oam5V+4imeTab0d5W3Q9EuTof7+aVN+p+RNOc1DzBtYfs4dPsoWkP39i/bfTqjCZs8G5f0z+Xndl5dWY+Vuds/X3OxUlcr5zEdpHf/Ypu8WndD96cf87j6GvM+3k7ZrSDD+zQaTvNt/18vcOZnVVDN3TJDqSu6pE//CI7tGuHRyvwIMt+N8uYqj7sDeftwGgHHtjhF/nDp/15vupmzLNd1uQ5FqZq4QXuxJN45DJf4uCRqPglUdGBqChFdcUOpOzgJTs+5QbGTtpJJ01DI93O+uim7NHPmmgvk/jFBj1s2xCPGlxtU1zUMkk+XKPWsdMVD3faNv9tASXvJMCYcIadgwkWB9NOfLt+LK6pJzfvRTQ7m8HdSrITi+qlqOPtiOZVBfJ9WCOzwj46kY3q5s1uNz+g671uPiK2iktPdIBb92o+YGGOXjulH/Y+Y9L3SGYunDyUTgzc6cP2+g1O/Y+9YAej9nDy0AsyHO1FwmaKsPPrPEDXY75F1/Tt3EbzutEu+812WVQeXFw5Ie672Fpzfdw/3KHHlfbav6i99v9jW5xiXqKfpKlJNL0TLFcE6xYEa7YIxqf2Q7/YD9fWtb+UpiyliS+lCVOa+NIu5VP5cXchwMZC2L69r1QgLTx41Ec/sUOf8TnWIZKrFHK5kVxzbmV5OG3twTbKrs7jdpsUjfTkCIR9W62Nlq9YONASzbH736k9Gy9c1N9vDWG3NbSXPOAL7ZxT7dx5O6Ds4Mpt86idqblcW2tHrai1mFrUSv38M29RMw7f35c73zrdOxEr7bWgdr+lWsWtNPrucO8J449e6/fz87vy7HYvuWIIP3YMqYLynioZtwXIePxswmeKuEleKj2v9KqFXqNwpHDtHOeMwsGEczDhQD7nyp51Ey5f2ItXzzsOJ5zcXua4XOGMwpULXK38axSumeNaZQ/thGsX9jqr5u0mXIcLHCtcrXBugcsULle4fI6T01g52E5AIdwS2SpkpZHdAkmKRJgpJNklkhSSNZIXSK8IRoqYkKnJyGvBcrJMTUakkcvJMq+QoJHZApmr+npts1QmVN2tr6ZxxRubqTrkelwRt9LjqhqsxzvlkBqvFSGcVqjVCnIqVtuoxDrUAuWqU7GhUTG7XAvUanGKELL9KAFpgaqVU+saSeXDgxaoxLpGC1RGnFpa0lMpgaI+5moxOqMFqtqs52i0RqkFOiW1Fmh3Ky3Q7qoKklVp504LVAW9cldODSWYCvX1719llMhf0//p6qKStW5kI5PLZl7Kzhm+Drv9KO3ts+RbJSdzQBYSY/+jpNtb3oX1U0Gdx3FzHy+xQLiLv6o1sUni8Of9/feeSTxpTA6UZTLwW+97gBiqTEhVuEK1t0+QQ+VLBKPfIulqeUp5fMHGyUPyWHnk7mVaeWp5SnmygkHkwigWPenG5GnkCf8VJE+Wqy5GaAtZJ+72BrVM34ggb0dXGJuik6SYabCTQclWK3u+7MvQNXJksDzylgissMU2maTEy97mCgzxt+I5kiSgmpsK9rtw4g6jUIVAqZC6lMKCosKiE3HguA3OmUC/N6jaAun2EyqJp/9JYr//JHv7gEoWnLxqH3apdQFsCeyWALcEQzXf3//of8m2aG6/xE2QzJrw4TPUTD4x1kUmLyl3F14wvCgELW8XyC7vTGIN71ICDu86RH0T4/8BCuMLAQ==
\ No newline at end of file
installation/V2/dummy/project/dummy_top_summary.html
View file @ cf33831c
......@@ -2,57 +2,400 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>dummy_top Project Status</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>dummy_top Project Status (02/22/2013 - 10:50:57)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>dummy.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>dummy_top</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
<TD>Programming File Generated</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx45t-3fgg484</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
<TD>
No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.2</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
<TD ALIGN=LEFT>No Warnings</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
<A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top.unroutes'>All Signals Completely Routed</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
<TD>
<A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD>
<A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
<TD>0 &nbsp;<A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>27</TD>
<TD ALIGN=RIGHT>54,576</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>27</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latch-thrus</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as AND/OR logics</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>55</TD>
<TD ALIGN=RIGHT>27,288</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>54</TD>
<TD ALIGN=RIGHT>27,288</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>33</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>18</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>3</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>6,408</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
<TD ALIGN=RIGHT>1</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice carry load</TD>
<TD ALIGN=RIGHT>1</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with other load</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>19</TD>
<TD ALIGN=RIGHT>6,822</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Nummber of MUXCYs used</TD>
<TD ALIGN=RIGHT>20</TD>
<TD ALIGN=RIGHT>13,644</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>55</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>30</TD>
<TD ALIGN=RIGHT>55</TD>
<TD ALIGN=RIGHT>54%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>55</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>25</TD>
<TD ALIGN=RIGHT>55</TD>
<TD ALIGN=RIGHT>45%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
<TD ALIGN=RIGHT>2</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>5</TD>
<TD ALIGN=RIGHT>54,576</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>296</TD>
<TD ALIGN=RIGHT>2%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of LOCed IOBs</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>116</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>232</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>6%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGMUX</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>376</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>376</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>376</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>256</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>58</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of GTPA1_DUALs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCIE_A1s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>2.17</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
<A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top.unroutes'>All Signals Completely Routed</A></TD>
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>
<A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TABLE>
......@@ -60,19 +403,20 @@
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Feb 22 10:49:48 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Feb 22 10:49:53 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri Feb 22 10:50:13 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/_xmsgs/map.xmsgs?&DataKey=Info'>6 Infos (0 new, 0 filtered)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri Feb 22 10:50:32 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri Feb 22 10:50:39 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new, 0 filtered)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/dummy_top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Fri Feb 22 10:50:56 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri Feb 22 10:50:57 2013</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 02/01/2013 - 16:31:39</center>
<br><center><b>Date Generated:</b> 02/22/2013 - 10:50:57</center>
</BODY></HTML>
\ No newline at end of file
installation/V2/dummy/project/iseconfig/dummy.projectmgr
View file @ cf33831c
......@@ -23,13 +23,13 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
<SelectedItem></SelectedItem>
</SelectedItems>
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
......@@ -68,7 +68,7 @@
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<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a6000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a60000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001dc000000010000000100000000000000000000000064ffffffff000000810000000000000001000001dc0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Configure Target Device</CurrentItem>
</ItemView>
......@@ -82,7 +82,7 @@
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<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
......
installation/V2/dummy/project/iseconfig/dummy_top.xreport
View file @ cf33831c
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2013-02-01T16:31:39</DateModified>
<DateModified>2013-02-22T10:48:53</DateModified>
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<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/iseconfig/dummy_top.xreport</SavedFilePath>
......
installation/V2/dummy/project/par_usage_statistics.html
View file @ cf33831c
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>74</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>159</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>159</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>149</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>65</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>136</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>136</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>121</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>6.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>7.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>9.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>9.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>9.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>9.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>9.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>9.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>9.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>1.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>2.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>22.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>10.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>0.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>7.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>9.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>9.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>9.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>9.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>9.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>9.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>9.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>5.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>0.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>6.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>3.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>0.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0037</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0023</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
installation/V2/dummy/top/dummy_top.vhd
View file @ cf33831c
......@@ -12,40 +12,40 @@ end dummy_top;
architecture Behavioral of dummy_top is
signal pps : std_logic;
signal cnt : integer range 0 to 20000000;
signal cnt : integer range 0 to 1000000;
signal cnt2 : unsigned(6 downto 1);
begin
PULSE_FRONT_LED_N <= std_logic_vector(cnt2);
PULSE_FRONT_LED_N <= not std_logic_vector(cnt2);
p_dummy : process (CLK20_VCXO, RST_N)
begin
if rising_edge(CLK20_VCXO) then
if (rst_n = '1') then
cnt <= 0;
pps <= '0';
else
cnt <= cnt + 1;
pps <= '0';
if (cnt = 19999999) then
cnt <= 0;
pps <= '1';
end if;
end if;
end if;
end process;
p_dummy : process (CLK20_VCXO)
begin
if rising_edge(CLK20_VCXO) then
if (rst_n = '1') then
cnt <= 0;
pps <= '0';
else
cnt <= cnt + 1;
pps <= '0';
if (cnt = 999999) then
cnt <= 0;
pps <= '1';
end if;
end if;
end if;
end process;
p_dummy2 : process (clk20_vcxo) is
begin
if rising_edge(clk20_vcxo) then
if (rst_n = '1') then
cnt2 <= (others=>'0');
else
if (pps = '1') then
cnt2 <= cnt2+1;
end if;
end if;
end if;
end process;
p_dummy2 : process (clk20_vcxo) is
begin
if rising_edge(clk20_vcxo) then
if (rst_n = '1') then
cnt2 <= (others=>'0');
else
if (pps = '1') then
cnt2 <= cnt2+1;
end if;
end if;
end if;
end process;
end Behavioral;
......
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