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Commit cf33831c authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Creating i2c-test branch and switching to it, for testing purposes.

parent 271a30e4
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hdl/IMAGES/image1/constraints/V2/BloV2.ucf
View file @ cf33831c
......@@ -7,8 +7,8 @@
##----------------------------------------
NET "RST_N" LOC = N20;
NET "RST_N" IOSTANDARD = LVTTL;
NET "rst_i" LOC = N20;
NET "rst_i" IOSTANDARD = LVTTL;
#NET "FPGA_SYSRESET_N" LOC = L20;
NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = LVTTL;
......@@ -371,18 +371,18 @@ NET "LEVEL" IOSTANDARD = LVCMOS33;
##--
##-- + ACT: CMOS 3.3V input
##-------------------
NET "FPGA_RTMM_N[0]" LOC = V21;
NET "FPGA_RTMM_N[0]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[1]" LOC = V22;
NET "FPGA_RTMM_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[2]" LOC = U22;
NET "FPGA_RTMM_N[2]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[0]" LOC = W22;
NET "FPGA_RTMP_N[0]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[1]" LOC = Y22;
NET "FPGA_RTMP_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[2]" LOC = Y21;
NET "FPGA_RTMP_N[2]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[0]" LOC = V21;
NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[1]" LOC = V22;
NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[2]" LOC = U22;
NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[0]" LOC = W22;
NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[1]" LOC = Y22;
NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[2]" LOC = Y21;
NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
###-------------------
###-- General purpose
###--
......
hdl/IMAGES/image1/project/image1.gise
View file @ cf33831c
......@@ -102,7 +102,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361383048" xil_pn:in_ck="2481835375757340990" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1361383029">
<transform xil_pn:end_ts="1361527497" xil_pn:in_ck="2481835375757340990" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1361527478">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -120,11 +120,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1361359880" xil_pn:in_ck="-6700002251458007206" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1361359880">
<transform xil_pn:end_ts="1361520115" xil_pn:in_ck="-6700002251458007206" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1361520115">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361383079" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1361383072">
<transform xil_pn:end_ts="1361527503" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1361527497">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -134,7 +134,7 @@
<outfile xil_pn:name="image1_top.ngd"/>
<outfile xil_pn:name="image1_top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1361383118" xil_pn:in_ck="-662876564851204569" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1361383079">
<transform xil_pn:end_ts="1361527537" xil_pn:in_ck="-662876564851204569" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1361527503">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -147,7 +147,7 @@
<outfile xil_pn:name="image1_top_summary.xml"/>
<outfile xil_pn:name="image1_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1361383152" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1361383118">
<transform xil_pn:end_ts="1361527577" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1361527537">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -162,7 +162,7 @@
<outfile xil_pn:name="image1_top_pad.txt"/>
<outfile xil_pn:name="image1_top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1361383171" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1361383152">
<transform xil_pn:end_ts="1361527596" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1361527577">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -173,13 +173,13 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1361383284" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1361383284">
<transform xil_pn:end_ts="1361527596" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1361527596">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1361383152" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1361383144">
<transform xil_pn:end_ts="1361527577" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1361527568">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/IMAGES/image1/project/image1.xise
View file @ cf33831c
......@@ -445,8 +445,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb/i2c_driver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.i2c_master_driver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -469,7 +469,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.image1_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.i2c_master_driver" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.image1_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
hdl/IMAGES/image1/rtl/image1_core.vhd
View file @ cf33831c
This diff is collapsed.
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ cf33831c
......@@ -153,46 +153,46 @@ package image1_pkg is
end component;
component i2c_slave_top
generic(g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns
port(sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_master_we_o : out STD_LOGIC;
wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_we_i : in STD_LOGIC;
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
pf_wb_addr_o : out STD_LOGIC;
rd_done_o : out STD_LOGIC;
wr_done_o : out STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
);
end component;
-- component i2c_slave_top
-- generic(g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns
-- port(sda_oen : out STD_LOGIC;
-- sda_i : in STD_LOGIC;
-- sda_o : out STD_LOGIC;
-- scl_oen : out STD_LOGIC;
-- scl_i : in STD_LOGIC;
-- scl_o : out STD_LOGIC;
--
-- wb_clk_i : in STD_LOGIC;
-- wb_rst_i : in STD_LOGIC;
--
-- wb_master_stb_o : out STD_LOGIC;
-- wb_master_cyc_o : out STD_LOGIC;
-- wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
-- wb_master_we_o : out STD_LOGIC;
-- wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
-- wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
-- wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
-- wb_master_ack_i : in STD_LOGIC;
-- wb_master_rty_i : in STD_LOGIC;
-- wb_master_err_i : in STD_LOGIC;
--
-- wb_slave_stb_i : in STD_LOGIC;
-- wb_slave_cyc_i : in STD_LOGIC;
-- wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
-- wb_slave_we_i : in STD_LOGIC;
-- wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
-- wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
-- wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
-- wb_slave_ack_o : out STD_LOGIC;
-- wb_slave_rty_o : out STD_LOGIC;
-- wb_slave_err_o : out STD_LOGIC;
--
-- pf_wb_addr_o : out STD_LOGIC;
-- rd_done_o : out STD_LOGIC;
-- wr_done_o : out STD_LOGIC;
-- i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
-- );
-- end component;
component m25p32_top
generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
......@@ -242,14 +242,14 @@ package image1_pkg is
wb_err_o : out STD_LOGIC);
end component;
component rtm_detector
generic(g_identifier_RTMM : t_RTMM := RTMM_V1;
g_identifier_RTMP : t_RTMP := RTMP_BLOCKING_V1);
port (RTMM_i : in STD_LOGIC_VECTOR(2 downto 0);
RTMP_i : in STD_LOGIC_VECTOR(2 downto 0);
ok_RTMM_o : out STD_LOGIC;
ok_RTMP_o : out STD_LOGIC);
end component;
-- component rtm_detector
-- generic(g_identifier_RTMM : t_RTMM := RTMM_V1;
-- g_identifier_RTMP : t_RTMP := RTMP_BLOCKING_V1);
-- port (RTMM_i : in STD_LOGIC_VECTOR(2 downto 0);
-- RTMP_i : in STD_LOGIC_VECTOR(2 downto 0);
-- ok_RTMM_o : out STD_LOGIC;
-- ok_RTMP_o : out STD_LOGIC);
-- end component;
-- function check_sys_cfg return BOOLEAN;
......
hdl/IMAGES/image1/test/image1_top_tb.vhd
View file @ cf33831c
......@@ -56,7 +56,8 @@ architecture behavior of image1_top_tb is
signal switch_i : STD_LOGIC_VECTOR(1 downto 1);
signal manual_rst_n_o : STD_LOGIC;
signal s_RTM_id_i : t_RTM_id := c_RTM_id_default;
signal rtmp, rtmm : std_logic_vector(2 downto 0);
--! ========================================================================
--! Signals for the i2c_master_driver (Renesasa alike)
--! ========================================================================
......@@ -215,6 +216,8 @@ begin
write_done_o => s_i2c_driver_ctrl_done.WRITE,
read_done_o => s_i2c_driver_ctrl_done.READ);
rtmm <= "001";
rtmp <= "000";
uut: image1_top
-- generic map(g_NUMBER_OF_CHANNELS => work.image1_top_tb_pkg.c_NUMBER_OF_CHANNELS)
port map(RST_N => s_RST_N,
......@@ -258,8 +261,9 @@ begin
LEVEL => level,
EXTRA_SWITCH => switch_i,
MR_N => manual_rst_n_o,
FPGA_RTMM_N => s_RTM_id_i.RTMM,
FPGA_RTMP_N => s_RTM_id_i.RTMP);
fpga_rtmm_n_i => rtmm,
fpga_rtmp_n_i => rtmp
);
--! Stimulus process
......
hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
View file @ cf33831c
......@@ -70,8 +70,8 @@ package image1_top_tb_pkg is
MR_N : out STD_LOGIC;--! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM_N : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP_N : in STD_LOGIC_VECTOR(2 downto 0));
FPGA_RTMM_N_i : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP_N_i : in STD_LOGIC_VECTOR(2 downto 0));
end component;
type t_pulse_vector is
......
hdl/IMAGES/image1/top/image1_top.vhd
View file @ cf33831c
This diff is collapsed.
hdl/basic_trigger/rtl/basic_trigger_core.vhd
View file @ cf33831c
......@@ -26,9 +26,9 @@ use work.ctdah_pkg.ALL;
entity basic_trigger_core is
generic
(
g_CLK_PERIOD : TIME;
g_OUTPUT_PULSE_LENGTH : TIME;
g_LED_BLINKING_LENGTH : TIME
g_clk_period : TIME;
g_output_pulse_length : TIME;
g_led_blinking_length : TIME
);
port
(
......@@ -51,7 +51,7 @@ architecture Behavioral of basic_trigger_core is
-- return natural is
-- variable v : natural;
-- begin
-- v := g_OUTPUT_PULSE_LENGTH/g_CLK_PERIOD;
-- v := g_output_pulse_length/g_clk_period;
-- report "pulse length: " & integer'image(v);
-- return v;
-- end pulselen;
......@@ -60,13 +60,13 @@ architecture Behavioral of basic_trigger_core is
-- return natural is
-- variable v : natural;
-- begin
-- v := g_LED_BLINKING_LENGTH/g_CLK_PERIOD;
-- v := g_led_blinking_length/g_clk_period;
-- report "LED length: " & integer'image(v);
-- return v;
-- end ledlen;
constant c_PULSE_LENGTH : NATURAL := g_OUTPUT_PULSE_LENGTH/g_CLK_PERIOD;
constant c_LED_LENGTH : NATURAL := g_LED_BLINKING_LENGTH/g_CLK_PERIOD;
constant c_PULSE_LENGTH : NATURAL := g_output_pulse_length/g_clk_period;
constant c_LED_LENGTH : NATURAL := g_led_blinking_length/g_clk_period;
signal s_pulse : STD_LOGIC;
......
hdl/basic_trigger/rtl/basic_trigger_top.vhd
View file @ cf33831c
......@@ -31,143 +31,166 @@ use UNISIM.VCOMPONENTS.ALL;
entity basic_trigger_top is
generic
(
g_NUMBER_OF_CHANNELS : NATURAL := 6;
g_CLK_PERIOD : TIME := 20 ns;
g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns
g_number_of_channels : natural := 6;
g_clk_period : time := 20 ns;
g_pulse_length : time := 1000 ns;
g_led_blinking_length : time := (10**6)*250 ns
);
port
(
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level_i : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1)
clk_i : in std_logic;
rst_i : in std_logic;
led_ttl_o : out std_logic;
-- Enable signals
fpga_o_en : out std_logic;
fpga_o_ttl_en : out std_logic;
fpga_o_inv_en : out std_logic;
fpga_o_blo_en : out std_logic;
level_i : in std_logic;
switch_i : in std_logic;
-- The manual reset allows power sequencing of the
-- 24V rail after a security given delay
manual_rst_n_o : out std_logic;
-- Front and rear pulse signals
pulse_i_front : in std_logic_vector(g_number_of_channels downto 1);
pulse_o_front : out std_logic_vector(g_number_of_channels downto 1);
pulse_i_rear : in std_logic_vector(g_number_of_channels downto 1);
pulse_o_rear : out std_logic_vector(g_number_of_channels downto 1);
-- Front and rear LED signals
led_o_front : out std_logic_vector(g_number_of_channels downto 1);
led_o_rear : out std_logic_vector(g_number_of_channels downto 1);
-- Inverting inputs and outputs
inv_i : in std_logic_vector(4 downto 1);
inv_o : out std_logic_vector(4 downto 1)
);
end basic_trigger_top;
architecture Behavioral of basic_trigger_top is
signal s_pulse_i : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_i_front : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_o : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_n_o : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_led : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_crop : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1) := (others => '0');
signal s_level : STD_LOGIC;
signal s_fpga_o_en : STD_LOGIC;
signal s_fpga_o_ttl_en : STD_LOGIC;
signal s_fpga_o_inv_en : STD_LOGIC;
signal s_fpga_o_blo_en : STD_LOGIC;
type delay_array is array (g_NUMBER_OF_CHANNELS downto 1) of STD_LOGIC_VECTOR(3 downto 0);
signal s_pulse_i_reg : delay_array;
--============================================================================
-- Component declarations
--============================================================================
component basic_trigger_core is
generic
(
g_CLK_PERIOD : TIME := g_CLK_PERIOD;
g_OUTPUT_PULSE_LENGTH : TIME := g_OUTPUT_PULSE_LENGTH;
g_LED_BLINKING_LENGTH : TIME := g_LED_BLINKING_LENGTH
g_clk_period : time;
g_output_pulse_length : time;
g_led_blinking_length : time
);
port
(
wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_rst_i : in std_logic;
wb_clk_i : in std_logic;
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
pulse_n_o : out STD_LOGIC;
pulse_i : in std_logic;
pulse_o : out std_logic;
pulse_n_o : out std_logic;
crop_o : out STD_LOGIC;
crop_o : out std_logic;
led_o : out STD_LOGIC
led_o : out std_logic
);
end component;
--============================================================================
-- Signal declarations
--============================================================================
signal pulse_in : std_logic_vector(g_number_of_channels downto 1);
signal pulse_in_front : std_logic_vector(g_number_of_channels downto 1);
signal pulse_out : std_logic_vector(g_number_of_channels downto 1);
signal pulse_out_n : std_logic_vector(g_number_of_channels downto 1);
signal led : std_logic_vector(g_number_of_channels downto 1);
signal crop : std_logic_vector(g_number_of_channels downto 1) := (others => '0');
signal level : std_logic;
signal fpga_out_en : std_logic;
signal fpga_out_ttl_en : std_logic;
signal fpga_out_inv_en : std_logic;
signal fpga_out_blo_en : std_logic;
-- type delay_array is array (g_number_of_channels downto 1) of std_logic_vector(3 downto 0);
-- signal pulse_in_reg : delay_array;
begin
--! level_i 0 means TTL Switch UP
--! 1 means TTL_N Switch DOWN
s_level <= level_i;
led_ttl_o <= s_level;
-- Level selection via on-board switch:
-- +---------+-----------------+
-- | level_i | Switch | Level |
-- +---------+---------+-------+
-- | 0 TTL | UP | TTL |
-- | 1 TTL_N | DOWN | TTL_N |
-- +---------+---------+-------+
level <= level_i;
led_ttl_o <= level;
-- pulse signal assignments
s_pulse_i_front <= pulse_i_front when (s_level = '0') else
not pulse_i_front;
s_pulse_i <= s_pulse_i_front or pulse_i_rear;
fpga_o_en <= s_fpga_o_en when (switch_i = '0') else '0';
fpga_o_ttl_en <= s_fpga_o_ttl_en;
fpga_o_inv_en <= s_fpga_o_inv_en;
fpga_o_blo_en <= s_fpga_o_blo_en;
led_o_front <= not(s_led); --! No need of accurate sync, hence we place
led_o_rear <= not(s_led); --! some combinatorial here.
pulse_o_front <= s_pulse_o when s_level = '0' else
not s_pulse_o;
pulse_o_rear <= s_pulse_o;
--! As we have one Schmitt inverter in the input,
--! and a buffer in the output, there's no need
--! to invert here.
inv_o <= inv_i;
pulse_in_front <= pulse_i_front when (level = '0') else
not pulse_i_front;
pulse_in <= pulse_in_front or pulse_i_rear;
fpga_o_en <= fpga_out_en when (switch_i = '0') else '0';
fpga_o_ttl_en <= fpga_out_ttl_en;
fpga_o_inv_en <= fpga_out_inv_en;
fpga_o_blo_en <= fpga_out_blo_en;
led_o_front <= not(led); -- No need of accurate sync, hence we place
led_o_rear <= not(led); -- some combinatorial here.
pulse_o_front <= pulse_out when level = '0' else
not pulse_out;
pulse_o_rear <= pulse_out;
-- As we have one Schmitt inverter in the input,
-- and a buffer in the output, there's no need
-- to invert here.
inv_o <= inv_i;
gen_trig_cores: for i in 1 to g_NUMBER_OF_CHANNELS generate
gen_trig_cores: for i in 1 to g_number_of_channels generate
trigger: basic_trigger_core
generic map
(
g_clk_period => g_clk_period,
g_output_pulse_length => g_pulse_length,
g_led_blinking_length => g_led_blinking_length
)
port map
(
wb_rst_i => rst_i,
wb_clk_i => clk_i,
pulse_i => s_pulse_i(i),
pulse_o => s_pulse_o(i),
pulse_n_o => s_pulse_n_o(i),
pulse_i => pulse_in(i),
pulse_o => pulse_out(i),
pulse_n_o => pulse_out_n(i),
crop_o => open,
led_o => s_led(i)
led_o => led(i)
);
end generate gen_trig_cores;
--! @brief Process to lock the enables so to avoid output glitches
--! on the startup.
--! @param clk_i Main clock used in this clock domain.
-- Process to lock the enables so to avoid output glitches
-- on the startup.
p_reset_chain : process(clk_i) is
begin
if rising_edge(clk_i) then
if rst_i = '1' then
--! First we reset the FPGA general output enable
--! Then we let one clock delay for the rest of signals
if (rst_i = '1') then
-- First we reset the FPGA general output enable
-- Then we let one clock delay for the rest of signals
manual_rst_n_o <= '0';
s_fpga_o_en <= '0';
s_fpga_o_ttl_en <= '0';
s_fpga_o_inv_en <= '0';
s_fpga_o_blo_en <= '0';
fpga_out_en <= '0';
fpga_out_ttl_en <= '0';
fpga_out_inv_en <= '0';
fpga_out_blo_en <= '0';
else
manual_rst_n_o <= '1';
s_fpga_o_en <= '1';
s_fpga_o_ttl_en <= s_fpga_o_en;
s_fpga_o_inv_en <= s_fpga_o_en;
s_fpga_o_blo_en <= s_fpga_o_en;
fpga_out_en <= '1';
fpga_out_ttl_en <= fpga_out_en;
fpga_out_inv_en <= fpga_out_en;
fpga_out_blo_en <= fpga_out_en;
end if;
end if;
end process p_reset_chain;
......
hdl/rtm_detector/rtl/rtm_detector.vhd
View file @ cf33831c
--==============================================================================
-- CERN (BE-CO-HT)
-- Rear transition module (RTM) detector
--==============================================================================
--
-- author: Carlos Gil Soriano
-- Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-01-09
--
-- version: 2.0
--
-- description:
--
-- This module detects the presence of rear transition module motherboards
-- (RTMMs) and piggybacks (RTMPs). Detection works by checking the RTMM and
-- RTMP input pins and these pins are pulled up on the front module. The
-- RTMM_OK and RTMP_OK ouputs are set if the corresponding inputs do not
-- yield errors. Different boards have the RTMM/P pins setup differently,
-- as outlined in the tables below:
--
-- Table 1. RTMM detection pins.
-- __________________________________________
-- | Board | RTMM[2] | RTMM[1] | RTMM[0] |
-- +-----------------------------------------+
-- | Error | '1' | '1' | '1' |
-- | RTMM_V1 | '1' | '1' | '0' |
-- | RTMM_V2 | '1' | '0' | '1' |
-- | Reserved | '1' | '0' | '0' |
-- | Reserved | '0' | '1' | '1' |
-- | Reserved | '0' | '1' | '0' |
-- | Reserved | '0' | '0' | '1' |
-- | Reserved | '0' | '0' | '0' |
-- +-----------+---------+---------+---------+
--
--
-- Table 2. RTMP detection pins.
-- _____________________________________________
-- | Board | RTMP[2] | RTMP[1] | RTMP[0] |
-- +-------------------------------------------+
-- | Error OR | '1' | '1' | '1' |
-- | Blocking_V1 | | | |
-- | RS485_V1 | '1' | '1' | '0' |
-- | -Reserved- | '1' | '0' | '1' |
-- | -Reserved- | '1' | '0' | '0' |
-- | -Reserved- | '0' | '1' | '1' |
-- | -Reserved- | '0' | '1' | '0' |
-- | -Reserved- | '0' | '0' | '1' |
-- | Error | '0' | '0' | '0' |
-- +-------------+---------+---------+---------+
--
--
-- dependencies:
-- none
--
-- references:
-- http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-01-09 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.rtm_detector_pkg.ALL;
--use work.rtm_detector_pkg.ALL;
entity rtm_detector is
generic(g_identifier_RTMM : t_RTMM;
g_identifier_RTMP : t_RTMP);
port (RTMM_i : in STD_LOGIC_VECTOR(2 downto 0);
RTMP_i : in STD_LOGIC_VECTOR(2 downto 0);
ok_RTMM_o : out STD_LOGIC;
ok_RTMP_o : out STD_LOGIC);
end rtm_detector;
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end entity rtm_detector;
architecture Behavioral of rtm_detector is
signal s_identifier_RTMM : UNSIGNED(2 downto 0)
:= f_UNSIGNED(g_identifier_RTMM);
signal s_identifier_RTMP : UNSIGNED(2 downto 0)
:= f_UNSIGNED(g_identifier_RTMP);
signal s_RTMM : UNSIGNED(2 downto 0);
signal s_RTMP : UNSIGNED(2 downto 0);
-- signal s_identifier_rtmm : unsigned(2 downto 0) := f_unsigned(g_identifier_rtmm);
-- signal s_identifier_rtmp : unsigned(2 downto 0) := f_unsigned(g_identifier_rtmp);
-- signal s_rtmm : unsigned(2 downto 0);
-- signal s_rtmp : unsigned(2 downto 0);
begin
s_RTMM <= UNSIGNED(RTMM_i);
s_RTMP <= UNSIGNED(RTMP_i);
rtmm_ok_o <= '0' when (rtmm_i = "111") else '1';
rtmp_ok_o <= '0' when (rtmp_i = "111") else '1';
ok_RTMM_o <= '1' when s_RTMM = s_identifier_RTMM
else '0';
ok_RTMP_o <= '1' when s_RTMP = s_identifier_RTMP
else '0';
-- s_rtmm <= unsigned(rtmm_i);
-- s_rtmp <= unsigned(rtmp_i);
--
-- ok_rtmm_o <= '1' when s_rtmm = s_identifier_rtmm else '0';
-- ok_rtmp_o <= '1' when s_rtmp = s_identifier_rtmp else '0';
end Behavioral;
hdl/rtm_detector/rtl/rtm_detector_pkg.vhd
View file @ cf33831c
......@@ -4,44 +4,6 @@ use IEEE.NUMERIC_STD.ALL;
package rtm_detector_pkg is
--! Please refer to:
--! http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection
--! to see conventions used to guarantee consistency between front board
--! and read transition modules
--! It should be noted that the RTMM, and RTMP pins are pulled up in
--! all the Front boards.
--! On 27/Nov/2012 the correspondencies are:
--!
--! __________________________________________
--! | Board | RTMM[2] | RTMM[1] | RTMM[0] |
--! +-----------------------------------------+
--! | Error | '1' | '1' | '1' |
--! | RTMM_V1 | '1' | '1' | '0' |
--! | Reserved0 | '1' | '0' | '1' |
--! | Reserved1 | '1' | '0' | '0' |
--! | Reserved2 | '0' | '1' | '1' |
--! | Reserved3 | '0' | '1' | '0' |
--! | Reserved4 | '0' | '0' | '1' |
--! | Reserved5 | '0' | '0' | '0' |
--! +-----------+---------+---------+---------+
--!
--! _____________________________________________
--! | Board | RTMP[2] | RTMP[1] | RTMP[0] |
--! +-------------------------------------------+
--! | Error | '1' | '1' | '1' |
--! | Blocking_V1 | '1' | '1' | '0' |
--! | RS485_V1 | '1' | '0' | '1' |
--! | Reserved0 | '1' | '0' | '0' |
--! | Reserved1 | '0' | '1' | '1' |
--! | Reserved2 | '0' | '1' | '0' |
--! | Reserved3 | '0' | '0' | '1' |
--! | Reserved4 | '0' | '0' | '0' |
--! +-------------+---------+---------+---------+
--!
--! It should be noted that there is an inverter before the FPGA,
--! so the signals/constant will be negated in rtm_detector.vhd
type t_RTMM is (RTMM_ERROR,
RTMM_V1,
RESERVED0,
......
installation/V2/dummy/constraints/BloV2.ucf
View file @ cf33831c
......@@ -7,8 +7,8 @@
###----------------------------------------
#
#
#NET "RST_N" LOC = N20;
# NET "RST_N" IOSTANDARD = "LVCMOS33";
NET "RST_N" LOC = N20;
NET "RST_N" IOSTANDARD = "LVCMOS33";
#NET "FPGA_SYSRESET_N" LOC = L20;
# NET "FPGA_SYSRESET_N" IOSTANDARD = "LVCMOS33";
#NET "MR_N" LOC = T22;
......
installation/V2/dummy/project/dummy.gise
View file @ cf33831c
This diff is collapsed.
installation/V2/dummy/project/dummy.xise
View file @ cf33831c
......@@ -318,6 +318,7 @@
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="impact.ipf" xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
......
installation/V2/dummy/project/iseconfig/dummy.projectmgr
View file @ cf33831c
......@@ -23,13 +23,13 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a6000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a60000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001dc000000010000000100000000000000000000000064ffffffff000000810000000000000001000001dc0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
......@@ -68,7 +68,7 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a6000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a60000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001dc000000010000000100000000000000000000000064ffffffff000000810000000000000001000001dc0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Configure Target Device</CurrentItem>
</ItemView>
......@@ -82,7 +82,7 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a6000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a60000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001dd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001dd0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
......
installation/V2/dummy/project/iseconfig/dummy_top.xreport
View file @ cf33831c
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2013-02-01T16:31:39</DateModified>
<DateModified>2013-02-22T10:48:53</DateModified>
<ModuleName>dummy_top</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/tstana/Projects/conv-ttl-blo/installation/V2/dummy/project/iseconfig/dummy_top.xreport</SavedFilePath>
......
installation/V2/dummy/project/par_usage_statistics.html
View file @ cf33831c
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<xtag-section name="ParStatistics">
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<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>3.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>0.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0037</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0023</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
installation/V2/dummy/top/dummy_top.vhd
View file @ cf33831c
......@@ -12,40 +12,40 @@ end dummy_top;
architecture Behavioral of dummy_top is
signal pps : std_logic;
signal cnt : integer range 0 to 20000000;
signal cnt : integer range 0 to 1000000;
signal cnt2 : unsigned(6 downto 1);
begin
PULSE_FRONT_LED_N <= std_logic_vector(cnt2);
PULSE_FRONT_LED_N <= not std_logic_vector(cnt2);
p_dummy : process (CLK20_VCXO, RST_N)
begin
if rising_edge(CLK20_VCXO) then
if (rst_n = '1') then
cnt <= 0;
pps <= '0';
else
cnt <= cnt + 1;
pps <= '0';
if (cnt = 19999999) then
cnt <= 0;
pps <= '1';
end if;
end if;
end if;
end process;
p_dummy : process (CLK20_VCXO)
begin
if rising_edge(CLK20_VCXO) then
if (rst_n = '1') then
cnt <= 0;
pps <= '0';
else
cnt <= cnt + 1;
pps <= '0';
if (cnt = 999999) then
cnt <= 0;
pps <= '1';
end if;
end if;
end if;
end process;
p_dummy2 : process (clk20_vcxo) is
begin
if rising_edge(clk20_vcxo) then
if (rst_n = '1') then
cnt2 <= (others=>'0');
else
if (pps = '1') then
cnt2 <= cnt2+1;
end if;
end if;
end if;
end process;
p_dummy2 : process (clk20_vcxo) is
begin
if rising_edge(clk20_vcxo) then
if (rst_n = '1') then
cnt2 <= (others=>'0');
else
if (pps = '1') then
cnt2 <= cnt2+1;
end if;
end if;
end if;
end process;
end Behavioral;
......
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