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Conv TTL Blocking
Commit e2084caf authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Renamed pulse gens, redesigned CSR 

The CSR now has individual bits controlling pulse generation, LED
sequencing and setting the RTM blocking pulse LED lines for testing them
and the RTM detection lines.

The doc files for the PTS have also been moved to the main doc/ folder,
and work on pts_hdlguide has restarted.
parent 4c3d7df3
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Showing with 353 additions and 232 deletions
doc/pts/.gitignore 0 → 100644
View file @ e2084caf
build/
\ No newline at end of file
doc/pts/pts_hdlguide.bib 0 → 100644
View file @ e2084caf
@misc{StandardBlocking,
author = "C. Gil Soriano",
title = {{Standard Blocking Output Signal Definition for CTDAH board}},
month = sep,
year = 2011,
note = "{\url{http://www.ohwr.org/documents/109}}"
}
@misc{sysmon-i2c,
author = "{ELMA}",
title = {{Access to board data using SNMP and I2C}},
howpublished = {\url{http://www.ohwr.org/documents/227}}
}
@TECHREPORT{UG380,
institution = "Xilinx Inc.",
title = {{Spartan-6 FPGA Configuration User Guide}},
month = jul,
year = 2011,
number = "UG380 v2.3",
note = "{\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}"
}
@misc{rtm-ident,
title = {{RTM detection}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection}}
}
@misc{flyback,
title = {{Under the Hood of Flyback SMPS Designs}},
howpublished = {\url{http://focus.ti.com/asia/download/Topic_1_Picard_42pages.pdf}}
}
doc/pts/pts_hdlguide.tex 0 → 100644
View file @ e2084caf
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{rotating}
\usepackage{multirow}
\usepackage{color}
\begin{document}
\title{
\textbf{
Conv-TTL-Blo Production Test Suite\\
HDL Developer's Guide\\}}
\author{Theodor-Adrian Stana\\
% \href{mailto:t.stana@cern.ch}{\textbf{\textit{t.stana@cern.ch}}}\\
BE-CO-HT\\
}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25, keepaspectratio]{fig/cern-logo.png}
\end{center}
\end{figure}
\maketitle{}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
\pagebreak
\listoffigures
\listoftables
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
\thispagestyle{empty}
\section*{List of abbreviations}
\begin{tabular}{l l}
\textit{FPGA} & Field-Programmable Gate Array \\
\textit{PTS} & Production Test Suite \\
\textit{RTM} & Rear Transition Module \\
\textit{RTMM} & RTM Motherboard \\
\textit{RTMP} & RTM Piggyback \\
\textit{SFP} & Small form-factor pluggable (in the context of SFP connectors) \\
\end{tabular}
%======================================================================================
% SEC: Intro
%======================================================================================
\pagebreak
\section{Introduction}
\label{sec:intro}
This document presents a high-level view of the firmware implemented on the FPGA for the
Production Test Suite (PTS) project for the Conv-TTL-Blo board. The document starts with a
description of the folder structure and where the developer should look for specific files.
In the following section, the structure of the top-level HDL file is given along with
hints on where the developer should look in case changes are to be made
to the code. After that, the memory map is presented, followed by sections
describing the logic implemented to run the tests comprising PTS.
All the logic implemented on the FPGA is written in VHDL and can be obtained freely by cloning
the OHWR git repository for the Conv-TTL-Blo PTS project at the following link:
\textcolor{red}{link ohwr repo}
\textcolor{red}{\cite{StandardBlocking}}
\textcolor{red}{REFERENCE THE OTHER DOCUMENTS}
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{pts_hdlguide}
\end{document}
hdl/pulse_generator/rtl/Manifest.py → hdl/ctb_pulse_gen/rtl/Manifest.py
View file @ e2084caf
files = "pulse_generator.vhd"
files = "ctb_pulse_gen.vhd"
modules = {
"local" : [
......
hdl/pulse_generator/rtl/pulse_generator.vhd → hdl/ctb_pulse_gen/rtl/ctb_pulse_gen.vhd
View file @ e2084caf
......@@ -56,7 +56,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_generator is
entity ctb_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
......@@ -92,10 +92,10 @@ entity pulse_generator is
-- TYPE 2 pulse: g_glitch_filt_len+3 clk_i cycles
pulse_o : out std_logic
);
end entity pulse_generator;
end entity ctb_pulse_gen;
architecture behav of pulse_generator is
architecture behav of ctb_pulse_gen is
--============================================================================
-- Type declarations
......
hdl/pulse_gen/rtl/pulse_gen.vhd → hdl/ctb_pulse_gen_gp/rtl/ctb_pulse_gen_gp.vhd
View file @ e2084caf
......@@ -39,7 +39,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_gen is
entity ctb_pulse_gen_gp is
generic
(
g_pwidth : natural := 200;
......@@ -53,10 +53,10 @@ entity pulse_gen is
en_i : in std_logic;
pulse_o : out std_logic
);
end entity pulse_gen;
end entity ctb_pulse_gen_gp;
architecture behav of pulse_gen is
architecture behav of ctb_pulse_gen_gp is
--============================================================================
-- Function and procedure declarations
......
hdl/pts/rtl/pts_regs.vhd
View file @ e2084caf
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created : Fri May 3 17:05:11 2013
-- Created : Wed May 29 11:50:18 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
......@@ -27,8 +27,16 @@ entity pts_regs is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'current test' in reg: 'control and status register'
pts_csr_crrt_test_o : out std_logic_vector(3 downto 0);
-- Port for BIT field: 'TTL pulse enable' in reg: 'control and status register'
pts_csr_ttl_en_o : out std_logic;
-- Port for BIT field: 'Blocking pulse enable' in reg: 'control and status register'
pts_csr_blo_en_o : out std_logic;
-- Port for BIT field: 'Blocking LED control' in reg: 'control and status register'
pts_csr_blo_led_o : out std_logic;
-- Port for BIT field: 'pulse LED enable' in reg: 'control and status register'
pts_csr_pulse_led_en_o : out std_logic;
-- Port for BIT field: 'status LED enable' in reg: 'control and status register'
pts_csr_stat_led_en_o : out std_logic;
-- Port for BIT field: 'reset' in reg: 'control and status register'
pts_csr_rst_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'control and status register'
......@@ -42,7 +50,11 @@ end pts_regs;
architecture syn of pts_regs is
signal pts_csr_crrt_test_int : std_logic_vector(3 downto 0);
signal pts_csr_ttl_en_int : std_logic ;
signal pts_csr_blo_en_int : std_logic ;
signal pts_csr_blo_led_int : std_logic ;
signal pts_csr_pulse_led_en_int : std_logic ;
signal pts_csr_stat_led_en_int : std_logic ;
signal pts_csr_rst_int : std_logic ;
signal pts_id_bits_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
......@@ -72,9 +84,13 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pts_csr_crrt_test_int <= "0000";
pts_csr_ttl_en_int <= '0';
pts_csr_blo_en_int <= '0';
pts_csr_blo_led_int <= '0';
pts_csr_pulse_led_en_int <= '0';
pts_csr_stat_led_en_int <= '0';
pts_csr_rst_int <= '0';
pts_id_bits_int <= x"424C4F32";
pts_id_bits_int <= x"424c4f32";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -89,14 +105,21 @@ begin
case rwaddr_reg(0) is
when '0' =>
if (wb_we_i = '1') then
pts_csr_crrt_test_int <= wrdata_reg(3 downto 0);
pts_csr_ttl_en_int <= wrdata_reg(0);
pts_csr_blo_en_int <= wrdata_reg(1);
pts_csr_blo_led_int <= wrdata_reg(2);
pts_csr_pulse_led_en_int <= wrdata_reg(3);
pts_csr_stat_led_en_int <= wrdata_reg(4);
pts_csr_rst_int <= wrdata_reg(15);
end if;
rddata_reg(3 downto 0) <= pts_csr_crrt_test_int;
rddata_reg(0) <= pts_csr_ttl_en_int;
rddata_reg(1) <= pts_csr_blo_en_int;
rddata_reg(2) <= pts_csr_blo_led_int;
rddata_reg(3) <= pts_csr_pulse_led_en_int;
rddata_reg(4) <= pts_csr_stat_led_en_int;
rddata_reg(15) <= pts_csr_rst_int;
rddata_reg(23 downto 16) <= pts_csr_switch_i;
rddata_reg(29 downto 24) <= pts_csr_rtm_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
......@@ -131,8 +154,16 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- current test
pts_csr_crrt_test_o <= pts_csr_crrt_test_int;
-- TTL pulse enable
pts_csr_ttl_en_o <= pts_csr_ttl_en_int;
-- Blocking pulse enable
pts_csr_blo_en_o <= pts_csr_blo_en_int;
-- Blocking LED control
pts_csr_blo_led_o <= pts_csr_blo_led_int;
-- pulse LED enable
pts_csr_pulse_led_en_o <= pts_csr_pulse_led_en_int;
-- status LED enable
pts_csr_stat_led_en_o <= pts_csr_stat_led_en_int;
-- reset
pts_csr_rst_o <= pts_csr_rst_int;
-- switches
......
hdl/pts/rtl/pts_regs.wb
View file @ e2084caf
......@@ -7,14 +7,47 @@ peripheral {
reg {
name = "control and status register";
prefix = "csr";
field {
name = "current test";
prefix = "crrt_test";
type = SLV;
size = 4;
name = "TTL pulse enable";
prefix = "ttl_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Blocking pulse enable";
prefix = "blo_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Blocking LED control";
prefix = "blo_led";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "pulse LED enable";
prefix = "pulse_led_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "status LED enable";
prefix = "stat_led_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "reset";
prefix = "rst";
......@@ -23,6 +56,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "switches";
prefix = "switch";
......@@ -32,6 +66,7 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RTM";
prefix = "rtm";
......
hdl/pts/syn/Makefile
View file @ e2084caf
......@@ -134,8 +134,8 @@ FILES := ../top/conv_ttl_blo_v2.ucf \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../pulse_gen/rtl/pulse_gen.vhd \
../../pulse_generator/rtl/pulse_generator.vhd \
../../ctb_pulse_gen_gp/rtl/ctb_pulse_gen_gp.vhd \
../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../rtm_detector/rtl/rtm_detector.vhd \
../../vme64x_i2c/rtl/i2c_slave.vhd \
......
hdl/pts/syn/conv_ttl_blo_v2.gise
View file @ e2084caf
......@@ -72,35 +72,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1368807798" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807798" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807798" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807798" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807798" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807798" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807798" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807863" xil_pn:in_ck="2106099442498953536" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821184" xil_pn:in_ck="8612814983564804210" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1368807863" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1368807863">
<transform xil_pn:end_ts="1369821184" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1369821184">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807876" xil_pn:in_ck="618428940982703508" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1368807863">
<transform xil_pn:end_ts="1369821198" xil_pn:in_ck="618428940982703508" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1369821184">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,7 +131,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1368808087" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1368807876">
<transform xil_pn:end_ts="1369821449" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1369821198">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -145,7 +145,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1368808177" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1368808087">
<transform xil_pn:end_ts="1369821553" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1369821449">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -159,7 +159,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1368808215" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1368808177">
<transform xil_pn:end_ts="1369821592" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1369821553">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -171,7 +171,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1368808177" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1368808160">
<transform xil_pn:end_ts="1369821553" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1369821536">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/pts/syn/conv_ttl_blo_v2.xise
View file @ e2084caf
......@@ -362,16 +362,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../rtl/pts_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../rtl/pulse_cnt_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../rtl/clk_info_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
......@@ -643,11 +643,11 @@
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../pulse_gen/rtl/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
<file xil_pn:name="../../ctb_pulse_gen_gp/rtl/ctb_pulse_gen_gp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../pulse_generator/rtl/pulse_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
<file xil_pn:name="../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
......
hdl/pts/top/Manifest.py
View file @ e2084caf
......@@ -7,8 +7,8 @@ modules = {
"local" : [
"../../../../ip_cores/general-cores",
"../../reset_gen",
"../../pulse_gen",
"../../pulse_generator",
"../../ctb_pulse_gen_gp",
"../../ctb_pulse_gen",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../../vme64x_i2c",
......
hdl/pts/top/conv_ttl_blo_v2.vhd
View file @ e2084caf
......@@ -164,17 +164,6 @@ architecture behav of conv_ttl_blo_v2 is
--============================================================================
-- Constant declarations
--============================================================================
-- Test number constants
constant c_test_led_1 : natural := 2;
constant c_test_led_2 : natural := 3;
constant c_test_thermo : natural := 4;
constant c_test_ttl : natural := 6;
constant c_test_blo_1 : natural := 8;
constant c_test_blo_2 : natural := 9;
constant c_test_pll : natural := 10;
constant c_test_sfp_eeprom : natural := 12;
constant c_test_sfp : natural := 14;
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 11;
......@@ -350,15 +339,23 @@ architecture behav of conv_ttl_blo_v2 is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'current test' in reg: 'control and status register'
pts_csr_crrt_test_o : out std_logic_vector(3 downto 0);
-- Port for BIT field: 'reset' in reg: 'control and status register'
-- Port for BIT field: 'TTL pulse enable' in reg: 'control and status register'
pts_csr_ttl_en_o : out std_logic;
-- Port for BIT field: 'Blocking pulse enable' in reg: 'control and status register'
pts_csr_blo_en_o : out std_logic;
-- Port for BIT field: 'Blocking LED control' in reg: 'control and status register'
pts_csr_blo_led_o : out std_logic;
-- Port for BIT field: 'pulse LED enable' in reg: 'control and status register'
pts_csr_pulse_led_en_o : out std_logic;
-- Port for BIT field: 'status LED enable' in reg: 'control and status register'
pts_csr_stat_led_en_o : out std_logic;
-- Port for BIT field: 'reset' in reg: 'control and status register'
pts_csr_rst_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'control and status register'
-- Port for std_logic_vector field: 'switches' in reg: 'control and status register'
pts_csr_switch_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM' in reg: 'control and status register'
-- Port for std_logic_vector field: 'RTM' in reg: 'control and status register'
pts_csr_rtm_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID'
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID'
pts_id_bits_o : out std_logic_vector(31 downto 0)
);
end component pts_regs;
......@@ -366,7 +363,7 @@ architecture behav of conv_ttl_blo_v2 is
-- Fixed-frequency pulse generator component
-- (use: generate the first pulse that gets replicated from one channel to
-- another, in the TTL pulse test)
component pulse_gen is
component ctb_pulse_gen_gp is
generic
(
g_pwidth : natural := 200;
......@@ -380,11 +377,11 @@ architecture behav of conv_ttl_blo_v2 is
en_i : in std_logic;
pulse_o : out std_logic
);
end component pulse_gen;
end component ctb_pulse_gen_gp;
-- Pulse generator component
-- (use: TTL and BLO pulse tests)
component pulse_generator is
component ctb_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
......@@ -420,7 +417,7 @@ architecture behav of conv_ttl_blo_v2 is
-- TYPE 2 pulse: g_glitch_filt_len+3 clk_i cycles
pulse_o : out std_logic
);
end component pulse_generator;
end component ctb_pulse_gen;
-- Pulse counter Wishbone regs component
-- use: TTL, BLO tests
......@@ -606,18 +603,9 @@ architecture behav of conv_ttl_blo_v2 is
-- Global reset signals
signal rst_n, rst : std_logic;
-- RTM detection signals
signal rtmm, rtmp : std_logic_vector(2 downto 0);
signal rtmm_ok, rtmp_ok : std_logic;
-- Temporary signal for inverted-TTL pulse outputs
signal inv_outputs : std_logic_vector(g_nr_inv_chan downto 1);
-- Pulse status LED signals
signal front_led_en : std_logic_vector(g_nr_ttl_chan downto 1);
signal rear_led_en : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_leds : std_logic_vector(g_nr_ttl_chan downto 1);
-- Output enable signals
signal oe, ttl_oe : std_logic;
signal blo_oe, inv_oe : std_logic;
......@@ -638,9 +626,9 @@ architecture behav of conv_ttl_blo_v2 is
-- LED signals
signal led_seq : unsigned(4 downto 0);
signal front_led_ledtest : std_logic_vector(g_nr_ttl_chan downto 1);
signal front_led_plltest : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_led_en : std_logic;
signal stat_led_en : std_logic;
-- PTS register signals
signal pts_state : t_pts_state;
signal pts_crrt_test_slv : std_logic_vector(3 downto 0);
......@@ -666,6 +654,8 @@ architecture behav of conv_ttl_blo_v2 is
-- Blocking pulse test signals
signal blo_pulse_en : std_logic;
signal blo_led : std_logic;
signal blo_trigs : std_logic_vector(6 downto 1);
signal blo_trigs_d0 : std_logic_vector(6 downto 1);
signal blo_trigs_d1 : std_logic_vector(6 downto 1);
......@@ -880,10 +870,14 @@ begin
wb_stall_o => xbar_master_in(c_slv_pts_regs).stall,
-- PTS control register
pts_csr_crrt_test_o => pts_crrt_test_slv,
pts_csr_rst_o => rst_fr_reg,
pts_csr_switch_i => switches,
pts_csr_rtm_i => rtm_lines,
pts_csr_ttl_en_o => ttl_pulse_en,
pts_csr_blo_en_o => blo_pulse_en,
pts_csr_blo_led_o => blo_led,
pts_csr_pulse_led_en_o => pulse_led_en,
pts_csr_stat_led_en_o => stat_led_en,
pts_csr_rst_o => rst_fr_reg,
pts_csr_switch_i => switches,
pts_csr_rtm_i => rtm_lines,
-- PTS ID register
pts_id_bits_o => open
......@@ -892,74 +886,6 @@ begin
-- Assign the unsigned current test signal
pts_crrt_test <= unsigned(pts_crrt_test_slv);
--============================================================================
-- FSM logic
--============================================================================
-- The test number is a four-bit fractional with one bit fractional part. It
-- is set via the first four bits of the PTS control register and is used
-- to set the state of the FSM.
pts_state <= ST_TTLTEST when (pts_crrt_test = c_test_ttl) else
ST_BLOTEST_1 when (pts_crrt_test = c_test_blo_1) else
ST_BLOTEST_2 when (pts_crrt_test = c_test_blo_2) else
ST_LEDTEST_1 when (pts_crrt_test = c_test_led_1) else
ST_LEDTEST_2 when (pts_crrt_test = c_test_led_2) else
ST_IDLE;
-- This process implements the main FSM of the PTS firmware, governing
-- operation during various tests. The operations implemented are shown
-- below:
--
-- test07 Increment LED sequence every time interval.
p_fsm : process(clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
ttl_pulse_en <= '0';
blo_pulse_en <= '0';
cnt_halfsec <= (others => '0');
led_seq <= (others => '0');
pulse_rear_led_n_o <= (others => '0');
else
-- Default: pulses not generated
ttl_pulse_en <= '0';
blo_pulse_en <= '0';
case pts_state is
when ST_TTLTEST =>
ttl_pulse_en <= '1';
when ST_BLOTEST_1 =>
blo_pulse_en <= '1';
when ST_BLOTEST_2 =>
pulse_rear_led_n_o <= (others => '1');
when ST_LEDTEST_1 =>
cnt_halfsec <= cnt_halfsec + 1;
if (cnt_halfsec = 62499999) then
cnt_halfsec <= (others => '0');
led_seq <= led_seq + 1;
if (led_seq = 7) then
led_seq <= (others => '0');
end if;
end if;
when others =>
cnt_halfsec <= cnt_halfsec + 1;
if (cnt_halfsec = 62499999) then
cnt_halfsec <= (others => '0');
led_seq <= led_seq + 1;
if (led_seq = 31) then
led_seq <= to_unsigned(8,5);
end if;
end if;
end case;
end if;
end if;
end process p_fsm;
--============================================================================
-- Thermometer test logic
......@@ -1034,11 +960,11 @@ begin
--============================================================================
-- TTL pulse test logic
--============================================================================
-- First, instantiate a pulse generator with fixed frequency and pulse
-- width, to generate the output pulse from CH10 (INV-TTL CH4) to CH1
-- First, instantiate a general-purpose pulse generator to generate the output
-- pulse from CH10 (INV-TTL CH4) to CH1
--
-- 1-us pulses are generated twice a second.
cmp_first_pulse_gen : pulse_gen
cmp_first_pulse_gen : ctb_pulse_gen_gp
generic map
(
g_pwidth => 125,
......@@ -1067,7 +993,7 @@ begin
-- Type 1 pulses (non-glich-filtered) with 1us width will be generated by
-- the generator blocks.
gen_ttl_pulse_gens : for i in 1 to 9 generate
cmp_ttl_pulse_gen : pulse_generator
cmp_ttl_pulse_gen : ctb_pulse_gen
generic map
(
g_pulse_width => 125,
......@@ -1084,13 +1010,13 @@ begin
);
end generate gen_ttl_pulse_gens;
-- Assign the outputs of the pulse_generator components to the TTL and INV-TTL
-- Assign the outputs of the ctb_pulse_gen components to the TTL and INV-TTL
-- outputs
fpga_out_ttl_o <= ttl_pulses( 6 downto 1);
inv_out_o <= ttl_pulses(10 downto 7);
-- Process to count input and output pulses. Since the pulses are generated
-- on the rising edge of the input pulse, the outputs from the pulse_generator
-- on the rising edge of the input pulse, the outputs from the ctb_pulse_gen
-- blocks need to be resynced.
p_cnt_ttl_pulses : process(clk125) is
begin
......@@ -1130,12 +1056,12 @@ begin
-- Blocking pulse test logic
--============================================================================
-- First, instantiate six fixed-frequency, fixed-delay pulse generators
-- (pulse_gen components) to output the pulses on each channel. The channels
-- (ctb_pulse_gen_gp components) to output the pulses on each channel. The channels
-- are time-domain multiplexed, each channel outputting a pulse 100 ms after
-- the other. Blocking CH1 will output a pulse at 0 ms, CH2 at 100 ms, CH3 at
-- 200 ms, and so on.
gen_blo_pulse_gen : for i in 1 to 6 generate
cmp_blo_pulse_gen : pulse_gen
cmp_blo_pulse_gen : ctb_pulse_gen_gp
generic map
(
g_pwidth => 125,
......@@ -1157,7 +1083,7 @@ begin
fpga_trig_blo_o <= blo_pulses;
-- Process to count input and output pulses. Since the pulses are generated
-- on the rising edge of the input pulse, the outputs from the pulse_generator
-- on the rising edge of the input pulse, the outputs from the ctb_pulse_gen
-- blocks need to be resynced.
p_cnt_blo_pulses : process(clk125) is
begin
......@@ -1193,9 +1119,14 @@ begin
end if;
end process p_cnt_blo_pulses;
-- Pulse LEDs are connected back to RTM detection lines, so here we connect
-- the output to the blocking pulse LED control bit
pulse_rear_led_n_o <= (others => blo_led);
-- Uncomment following lines to debug BLO pulse output
-- NOTE: you need a blocking RTM for this to work properly.
-- gen_pulse_leds : for i in 1 to 6 generate
-- cmp_pulse_led_gen : pulse_gen
-- cmp_pulse_led_gen : ctb_pulse_gen_gp
-- generic map
-- (
-- g_pwidth => 12*(10**6),
......@@ -1435,18 +1366,6 @@ begin
-- Finally, assign the SYNC_N output to the DAC
fpga_plldac2_sync_n_o <= plldac2_sync_n(0);
p_shift_front_leds : process(clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
front_led_plltest <= "111110";
else
front_led_plltest <= front_led_plltest(g_nr_ttl_chan-1 downto 1) &
front_led_plltest(g_nr_ttl_chan);
end if;
end if;
end process p_shift_front_leds;
--============================================================================
-- SFP EEPROM test logic
-- * test J1 SFP connector using an SFP loopback module
......@@ -1648,70 +1567,84 @@ begin
-- * test bicolor LEDs and its driving circuit (IC1)
-- * test front panel LED logic and driving circuit (IC5)
--============================================================================
-- The front LED outputs are multiplexed between the PLL test and the LED test.
-- pulse_front_led_n_o <= front_led_plltest when (state = ST_TEST04) else
-- front_led_ledtest when (state = ST_TEST11) else
-- (others => '1');
-- Sequence the front-panel LEDs based on the sequence counter in the FSM
pulse_front_led_n_o <= "111110" when (led_seq = 1) else
"111101" when (led_seq = 2) else
"111011" when (led_seq = 3) else
"110111" when (led_seq = 4) else
"101111" when (led_seq = 5) else
"011111" when (led_seq = 6) else
-- "111110" when (led_seq = 7) else
-- "111101" when (led_seq = 8) else
-- "111011" when (led_seq = 9) else
-- "110111" when (led_seq = 10) else
-- "101111" when (led_seq = 11) else
-- "011111" when (led_seq = 12) else
-- "111110" when (led_seq = 13) else
-- "111101" when (led_seq = 14) else
-- "111011" when (led_seq = 15) else
-- "110111" when (led_seq = 16) else
-- "101111" when (led_seq = 17) else
-- "011111" when (led_seq = 18) else
-- "111110" when (led_seq = 19) else
-- "111101" when (led_seq = 20) else
-- "111011" when (led_seq = 21) else
-- "110111" when (led_seq = 22) else
-- "101111" when (led_seq = 23) else
-- "011111" when (led_seq = 24) else
-- Process to control the LED sequence counter
p_led_seq : process (clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
cnt_halfsec <= (others => '0');
led_seq <= (others => '0');
elsif (pulse_led_en = '1') or (stat_led_en = '1') then
cnt_halfsec <= cnt_halfsec + 1;
if (cnt_halfsec = 62499999) then
cnt_halfsec <= (others => '0');
led_seq <= led_seq + 1;
if (led_seq = 24) then
led_seq <= (others => '0');
end if;
end if;
end if;
end if;
end process p_led_seq;
-- Sequence the front-panel LEDs based on the sequence counter
pulse_front_led_n_o <= "111110" when (pulse_led_en = '1') and (led_seq = 1) else
"111101" when (pulse_led_en = '1') and (led_seq = 2) else
"111011" when (pulse_led_en = '1') and (led_seq = 3) else
"110111" when (pulse_led_en = '1') and (led_seq = 4) else
"101111" when (pulse_led_en = '1') and (led_seq = 5) else
"011111" when (pulse_led_en = '1') and (led_seq = 6) else
"111110" when (pulse_led_en = '1') and (led_seq = 7) else
"111101" when (pulse_led_en = '1') and (led_seq = 8) else
"111011" when (pulse_led_en = '1') and (led_seq = 9) else
"110111" when (pulse_led_en = '1') and (led_seq = 10) else
"101111" when (pulse_led_en = '1') and (led_seq = 11) else
"011111" when (pulse_led_en = '1') and (led_seq = 12) else
"111110" when (pulse_led_en = '1') and (led_seq = 13) else
"111101" when (pulse_led_en = '1') and (led_seq = 14) else
"111011" when (pulse_led_en = '1') and (led_seq = 15) else
"110111" when (pulse_led_en = '1') and (led_seq = 16) else
"101111" when (pulse_led_en = '1') and (led_seq = 17) else
"011111" when (pulse_led_en = '1') and (led_seq = 18) else
"111110" when (pulse_led_en = '1') and (led_seq = 19) else
"111101" when (pulse_led_en = '1') and (led_seq = 20) else
"111011" when (pulse_led_en = '1') and (led_seq = 21) else
"110111" when (pulse_led_en = '1') and (led_seq = 22) else
"101111" when (pulse_led_en = '1') and (led_seq = 23) else
"011111" when (pulse_led_en = '1') and (led_seq = 24) else
"111111";
-- Light each LED red and green in a sequence, based on the sequence counter
-- in the FSM.
-- Light each LED red and green in a sequence, based on the sequence counter.
--
-- The colors are set via the LED state vector (two bits per LED) as follows:
-- state(1..0) color
-- 00 OFF
-- 01 RED
-- 10 GREEN
bicolor_led_state <= "000000000001000000000000" when (led_seq = 8) else
"000000000100000000000000" when (led_seq = 9) else
"000000010000000000000000" when (led_seq = 10) else
"000001000000000000000000" when (led_seq = 11) else
"000000000000000001000000" when (led_seq = 12) else
"000000000000000000010000" when (led_seq = 13) else
"000000000000000000000100" when (led_seq = 14) else
"000000000000000000000001" when (led_seq = 15) else
"000000000000000100000000" when (led_seq = 16) else
"000000000000010000000000" when (led_seq = 17) else
"000100000000000000000000" when (led_seq = 18) else
"010000000000000000000000" when (led_seq = 19) else
"000000000010000000000000" when (led_seq = 20) else
"000000001000000000000000" when (led_seq = 21) else
"000000100000000000000000" when (led_seq = 22) else
"000010000000000000000000" when (led_seq = 23) else
"000000000000000010000000" when (led_seq = 24) else
"000000000000000000100000" when (led_seq = 25) else
"000000000000000000001000" when (led_seq = 26) else
"000000000000000000000010" when (led_seq = 27) else
"000000000000001000000000" when (led_seq = 28) else
"000000000000100000000000" when (led_seq = 29) else
"001000000000000000000000" when (led_seq = 30) else
"100000000000000000000000" when (led_seq = 31) else
bicolor_led_state <= "000000000001000000000000" when (stat_led_en = '1') and (led_seq = 1) else
"000000000100000000000000" when (stat_led_en = '1') and (led_seq = 2) else
"000000010000000000000000" when (stat_led_en = '1') and (led_seq = 3) else
"000001000000000000000000" when (stat_led_en = '1') and (led_seq = 4) else
"000000000000000001000000" when (stat_led_en = '1') and (led_seq = 5) else
"000000000000000000010000" when (stat_led_en = '1') and (led_seq = 6) else
"000000000000000000000100" when (stat_led_en = '1') and (led_seq = 7) else
"000000000000000000000001" when (stat_led_en = '1') and (led_seq = 8) else
"000000000000000100000000" when (stat_led_en = '1') and (led_seq = 9) else
"000000000000010000000000" when (stat_led_en = '1') and (led_seq = 10) else
"000100000000000000000000" when (stat_led_en = '1') and (led_seq = 11) else
"010000000000000000000000" when (stat_led_en = '1') and (led_seq = 12) else
"000000000010000000000000" when (stat_led_en = '1') and (led_seq = 13) else
"000000001000000000000000" when (stat_led_en = '1') and (led_seq = 14) else
"000000100000000000000000" when (stat_led_en = '1') and (led_seq = 15) else
"000010000000000000000000" when (stat_led_en = '1') and (led_seq = 16) else
"000000000000000010000000" when (stat_led_en = '1') and (led_seq = 17) else
"000000000000000000100000" when (stat_led_en = '1') and (led_seq = 18) else
"000000000000000000001000" when (stat_led_en = '1') and (led_seq = 19) else
"000000000000000000000010" when (stat_led_en = '1') and (led_seq = 20) else
"000000000000001000000000" when (stat_led_en = '1') and (led_seq = 21) else
"000000000000100000000000" when (stat_led_en = '1') and (led_seq = 22) else
"001000000000000000000000" when (stat_led_en = '1') and (led_seq = 23) else
"100000000000000000000000" when (stat_led_en = '1') and (led_seq = 24) else
"000000000000000000000000";
-- Then, we instantiate the LED controller and control it via the LED state
......
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