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Commit e4c9846a authored by gilsoriano's avatar gilsoriano
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Adding read capability to SPI.

parent 02e0a154
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Showing with 793 additions and 166 deletions
hdl/spi_master_multifield/project/spi_master_multifield.xise 0 → 100755
View file @ e4c9846a
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hdl/spi_master_multifield/project/waveform/wave.do
View file @ e4c9846a
......@@ -11,15 +11,12 @@ add wave -noupdate -radix hexadecimal /spi_master_core_tb/addr_i
add wave -noupdate -radix hexadecimal /spi_master_core_tb/data_i
add wave -noupdate -expand /spi_master_core_tb/uut/s_STATUS
add wave -noupdate -radix hexadecimal /spi_master_core_tb/s_SPI0
add wave -noupdate -radix hexadecimal /spi_master_core_tb/s_SPI1
add wave -noupdate -radix hexadecimal -expand -subitemconfig {/spi_master_core_tb/s_SPI1.PUSH_DATA {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI1.PUSH_ADDR {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI1.PUSH_INST {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI1.x {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI1.SEND_DATA {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI1.SEND_ADDR {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI1.SEND_INST {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI1.SEND_OP {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI1.READ_MISO {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI1.y {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI1.CLK_DIV {-height 17 -radix hexadecimal} /spi_master_core_tb/s_SPI1.z {-height 17 -radix hexadecimal}} /spi_master_core_tb/s_SPI1
add wave -noupdate -expand -subitemconfig {/spi_master_core_tb/uut/s_SPI2.x {-height 17 -radix hexadecimal} /spi_master_core_tb/uut/s_SPI2.CLK_DIV {-height 17 -radix unsigned}} /spi_master_core_tb/uut/s_SPI2
add wave -noupdate -group {Timing counter} /spi_master_core_tb/uut/s_timing_counter_en
add wave -noupdate -group {Timing counter} /spi_master_core_tb/uut/s_timing_counter_manual_rst_i
add wave -noupdate -group {Timing counter} /spi_master_core_tb/uut/s_timing_counter_rst_i
add wave -noupdate -group {Timing counter} -radix unsigned /spi_master_core_tb/uut/s_timing_counter_cnt
add wave -noupdate -expand -group {SPI counter} /spi_master_core_tb/uut/s_spi_counter_en
add wave -noupdate -expand -group {SPI counter} /spi_master_core_tb/uut/s_spi_counter_manual_rst_clk
add wave -noupdate -expand -group {SPI counter} -radix unsigned /spi_master_core_tb/uut/s_spi_counter_cnt
add wave -noupdate -group {Clk divider} /spi_master_core_tb/uut/spi_cclk/clk_i
add wave -noupdate -group {Clk divider} /spi_master_core_tb/uut/spi_cclk/rst_i
add wave -noupdate -group {Clk divider} /spi_master_core_tb/uut/spi_cclk/oe_n_i
......@@ -46,22 +43,27 @@ add wave -noupdate -group data_fifo -label s_STATUS.PULL_DATA /spi_master_core_t
add wave -noupdate -group data_fifo /spi_master_core_tb/uut/data_i
add wave -noupdate -group data_fifo /spi_master_core_tb/uut/s_data_reg_o
add wave -noupdate /spi_master_core_tb/uut/s_STATUS_pull_byte_already
add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_rst_spi_analyser
add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_spi_count
add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_end_inst_flag
add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_end_addr_flag
add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_end_data_flag
add wave -noupdate -expand -group Testbench -radix hexadecimal /spi_master_core_tb/inst_check
add wave -noupdate -expand -group Testbench -radix hexadecimal /spi_master_core_tb/addr_check
add wave -noupdate -expand -group Testbench -radix hexadecimal /spi_master_core_tb/data_check
add wave -noupdate -group Testbench /spi_master_core_tb/s_rst_spi_analyser
add wave -noupdate -group Testbench /spi_master_core_tb/s_spi_count
add wave -noupdate -group Testbench /spi_master_core_tb/s_end_inst_flag
add wave -noupdate -group Testbench /spi_master_core_tb/s_end_addr_flag
add wave -noupdate -group Testbench /spi_master_core_tb/s_end_data_flag
add wave -noupdate -group Testbench -radix hexadecimal /spi_master_core_tb/inst_check
add wave -noupdate -group Testbench -radix hexadecimal /spi_master_core_tb/addr_check
add wave -noupdate -group Testbench -radix hexadecimal /spi_master_core_tb/data_check
add wave -noupdate /spi_master_core_tb/uut/s_spi_clk
add wave -noupdate /spi_master_core_tb/uut/s_spi_clk_d0
add wave -noupdate /spi_master_core_tb/uut/s_spi_clk_n
add wave -noupdate /spi_master_core_tb/uut/s_spi_clk_n_d0
add wave -noupdate /spi_master_core_tb/uut/s_spi_clk_tmp
add wave -noupdate /spi_master_core_tb/uut/s_spi_start_stop_spi_tx
add wave -noupdate /spi_master_core_tb/uut/data_o
add wave -noupdate -expand -group {MISO counter} /spi_master_core_tb/uut/spi_miso_bit_counter/clk_i
add wave -noupdate -expand -group {MISO counter} /spi_master_core_tb/uut/spi_miso_bit_counter/rst_i
add wave -noupdate -expand -group {MISO counter} /spi_master_core_tb/uut/spi_miso_bit_counter/en_i
add wave -noupdate -expand -group {MISO counter} -radix unsigned /spi_master_core_tb/uut/spi_miso_bit_counter/cnt_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1023076 ps} 0}
WaveRestoreCursors {{Cursor 1} {1585000 ps} 0}
configure wave -namecolwidth 260
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -76,4 +78,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {3482416 ps}
WaveRestoreZoom {0 ps} {7739618 ps}
hdl/spi_master_multifield/test/spi_master_core_tb.vhd
View file @ e4c9846a
......@@ -48,6 +48,8 @@ architecture behavior of spi_master_core_tb is
addr_i : in STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);
data_o : out STD_LOGIC_VECTOR (31 downto 0);
SPI0_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI1_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI2_o : out STD_LOGIC_VECTOR (15 downto 0);
......@@ -271,9 +273,12 @@ begin
s_SPI1 <= c_SPI1_default;
end procedure;
procedure set_FIFO_contents(inst: STD_LOGIC_VECTOR(8*c_INST_LENGTH - 1 downto 0);
addr: STD_LOGIC_VECTOR(8*c_ADDR_LENGTH - 1 downto 0);
data: STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0)) is
procedure set_FIFO_contents(inst: STD_LOGIC_VECTOR(8*c_INST_LENGTH - 1
downto 0);
addr: STD_LOGIC_VECTOR(8*c_ADDR_LENGTH - 1
downto 0);
data: STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1
downto 0)) is
begin
inst_i <= inst;
addr_i <= addr;
......@@ -297,8 +302,10 @@ begin
procedure set_spi_lengths(inst_length: NATURAL;
addr_length: NATURAL;
data_length: NATURAL) is
data_length: NATURAL;
read_length : NATURAL) is
begin
s_SPI0.BREAD <= to_unsigned(data_length, s_SPI0.BREAD'length);
s_SPI0.BDATA <= to_unsigned(data_length, s_SPI0.BDATA'length);
s_SPI0.BADDR <= to_unsigned(addr_length, s_SPI0.BADDR'length);
s_SPI0.BINST <= to_unsigned(inst_length, s_SPI0.BINST'length);
......@@ -306,11 +313,13 @@ begin
procedure send_SPI_and_wait(send_inst: STD_LOGIC;
send_addr: STD_LOGIC;
send_data: STD_LOGIC) is
send_data: STD_LOGIC;
read_miso: STD_LOGIC) is
begin
s_SPI1.SEND_INST <= '0';
s_SPI1.SEND_ADDR <= '0';
s_SPI1.SEND_DATA <= '0';
s_SPI1.READ_MISO <= '0';
wait until rising_edge(clk_i);
if send_inst = '1' then
s_SPI1.SEND_INST <= '1';
......@@ -321,12 +330,16 @@ begin
if send_data = '1' then
s_SPI1.SEND_DATA <= '1';
end if;
if read_miso = '1' then
s_SPI1.READ_MISO <= '1';
end if;
s_SPI1.SEND_OP <= '1';
wait until s_SPI2.SENT_OP = '1';
s_SPI1.SEND_OP <= '0';
s_SPI1.SEND_INST <= '0';
s_SPI1.SEND_ADDR <= '0';
s_SPI1.SEND_DATA <= '0';
s_SPI1.READ_MISO <= '0';
end procedure;
-- procedure assert_to_file(data : STD_LOGIC_VECTOR(31 downto 0);
......@@ -344,12 +357,21 @@ begin
-- assert data = reference report "Bad"&msg;
-- end procedure;
procedure spi_command(cpol : STD_LOGIC; cpha : STD_LOGIC;
inst_length: NATURAL; addr_length: NATURAL; data_length: NATURAL;
send_inst : STD_LOGIC; send_addr: STD_LOGIC; send_data: STD_LOGIC;
inst : STD_LOGIC_VECTOR(8*c_INST_LENGTH - 1 downto 0);
addr : STD_LOGIC_VECTOR(8*c_ADDR_LENGTH - 1 downto 0);
data : STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0)) is
procedure spi_command(cpol : STD_LOGIC; cpha : STD_LOGIC;
inst_length : NATURAL;
addr_length : NATURAL;
data_length : NATURAL;
read_length : NATURAL;
send_inst : STD_LOGIC;
send_addr : STD_LOGIC;
send_data : STD_LOGIC;
read_mosi : STD_LOGIC;
inst : STD_LOGIC_VECTOR(8*c_INST_LENGTH - 1
downto 0);
addr : STD_LOGIC_VECTOR(8*c_ADDR_LENGTH - 1
downto 0);
data : STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1
downto 0)) is
begin
s_rst_spi_analyser <= '1';
wait until rising_edge(clk_i);
......@@ -358,11 +380,10 @@ begin
wait until rising_edge(clk_i);
set_SPI_mode(cpol, cpha);
set_FIFO_contents(inst, addr, data);
set_spi_lengths(inst_length, addr_length, data_length);
send_SPI_and_wait(send_inst, send_addr, send_data);
set_spi_lengths(inst_length, addr_length, data_length, read_length);
send_SPI_and_wait(send_inst, send_addr, send_data, read_mosi);
end procedure;
begin
init_cond;
......@@ -381,36 +402,36 @@ begin
data_i <= (others => '0');
spi_command( '0', '0',
1, 1, 1,
'1', '1', '1',
1, 1, 1, 1,
'1', '1', '1', '1',
inst_i, addr_i, data_i);
wait for c_WISHBONE_PERIOD*10;
spi_command( '0', '1',
1, 1, 1,
'1', '1', '1',
1, 1, 1, 1,
'1', '1', '1', '1',
inst_i, addr_i, data_i);
wait for c_WISHBONE_PERIOD*10;
spi_command( '1', '0',
1, 1, 1,
'1', '1', '1',
1, 1, 1, 1,
'1', '1', '1', '1',
inst_i, addr_i, data_i);
wait for c_WISHBONE_PERIOD*10;
spi_command( '1', '1',
1, 1, 1,
'1', '1', '1',
1, 1, 1, 1,
'1', '1', '1', '1',
inst_i, addr_i, data_i);
wait for c_WISHBONE_PERIOD*10;
spi_command( '0', '0',
1, 3, 256,
'1', '1', '1',
1, 3, 256, 4,
'1', '1', '1', '1',
inst_i, addr_i, data_i);
wait for c_WISHBONE_PERIOD*10;
wait;
end process;
......
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