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Conv TTL Blocking
Commit eced93bc authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Updated Python test scripts 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 336ea4b3
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Showing with 37 additions and 32 deletions
software/multiboot/multiboot.py
View file @ eced93bc
......@@ -75,7 +75,7 @@ def spi_transfer(nbytes, cs, dat):
else:
for i in xrange(len(dat)):
wval.append((ctrl << 24) | dat[i])
testelma.writemregs(MB_BASE+MB_FAR_OFS, wval)
testelma.writemregs(slot, MB_BASE+MB_FAR_OFS, wval)
# Read the data and prepare the return value
while (retval & (1 << 28) == 0):
......@@ -291,7 +291,7 @@ def _iprog(addr):
except NAckError:
pass
# Set timeout to be sixty seconds from now...
# Set timeout...
t0 = time.time()
t1 = t0 + 20
......@@ -301,7 +301,10 @@ def _iprog(addr):
if (time.time() >= t1):
print "Timeout, IPROG unsuccessful!"
break
if ((testelma.read(slot, 0x4) & 0xFFFF) > 0x0200):
if ((testelma.read(slot, 0x4) & 0xFF) == 0x00):
print "IPROG unsuccessful, fallback to Golden bitstream occured!"
break
else:
print "IPROG successful!"
break
except NAckError:
......@@ -357,8 +360,8 @@ if __name__ == "__main__":
# Open VBCP connection
testelma.open()
# Set MB_BASE to value in pulsetest bitstream, if this bitstream is present
if (testelma.read(slot, 0x04) & 0xFFFF == 0x9999):
# The PULSETEST bitstream has the MultiBoot module starting at address 0x300
if (testelma.read(slot, 0x04) & 0xFF == 0x99):
MB_BASE = 0x300;
# Read config reg, if user wants to
......
software/pulsetest/pulsetest.py
View file @ eced93bc
......@@ -39,6 +39,8 @@ C4FREQREG = 0x240
C5FREQREG = 0x244
C6FREQREG = 0x248
CTB_CLK_PER = 50*(10**(-9))
#CTB_CLK_PER = 8*(10**(-9))
if __name__ == "__main__":
ip = "elma" # raw_input("Crate IP? ")
......@@ -65,9 +67,9 @@ if __name__ == "__main__":
testelma.open()
bloid = testelma.read(slot, 0x00)
fwvers = testelma.read(slot, 0x04) & 0xFFFF
fwvers = testelma.read(slot, 0x04) & 0xFF
if ( bloid != 0x424c4f32 ) or ( fwvers != 0x9999 ):
if ( bloid != 0x54424c4f ) or ( fwvers != 0x99 ):
print "Wrong version number (0x%04x)" % fwvers
sys.exit(1)
......@@ -79,12 +81,12 @@ if __name__ == "__main__":
chen = 0x00;
# Setup channel output pulse widths to 1.2us
testelma.write(slot, C1WDTHREG, 0x96)
testelma.write(slot, C2WDTHREG, 0x96)
testelma.write(slot, C3WDTHREG, 0x96)
testelma.write(slot, C4WDTHREG, 0x96)
testelma.write(slot, C5WDTHREG, 0x96)
testelma.write(slot, C6WDTHREG, 0x96)
testelma.write(slot, C1WDTHREG, 1.2*(10**(-6))/CTB_CLK_PER)
testelma.write(slot, C2WDTHREG, 1.2*(10**(-6))/CTB_CLK_PER)
testelma.write(slot, C3WDTHREG, 1.2*(10**(-6))/CTB_CLK_PER)
testelma.write(slot, C4WDTHREG, 1.2*(10**(-6))/CTB_CLK_PER)
testelma.write(slot, C5WDTHREG, 1.2*(10**(-6))/CTB_CLK_PER)
testelma.write(slot, C6WDTHREG, 1.2*(10**(-6))/CTB_CLK_PER)
# Setup channel delays and frequencies
farr = [0,0,0,0,0,0]
......@@ -100,7 +102,7 @@ if __name__ == "__main__":
# freq = 166000
# print "Automatically setting channel frequency to 166 kHz."
# farr[0] = freq
# freq = 1/(freq * 8*(10**(-9)))
# freq = 1/(freq * CTB_CLK_PER)
# testelma.write(slot, C1FREQREG, int(freq))
# #print freq
# #print hex(int(freq))
......@@ -116,7 +118,7 @@ if __name__ == "__main__":
# freq = 166000
# print "Automatically setting channel frequency to 166 kHz."
# farr[1] = freq
# freq = 1/(freq * 8*(10**(-9)))
# freq = 1/(freq * CTB_CLK_PER)
# testelma.write(slot, C2FREQREG, int(freq))
# #print freq
# #print hex(int(freq))
......@@ -132,7 +134,7 @@ if __name__ == "__main__":
# freq = 166000
# print "Automatically setting channel frequency to 166 kHz."
# farr[2] = freq
# freq = 1/(freq * 8*(10**(-9)))
# freq = 1/(freq * CTB_CLK_PER)
# testelma.write(slot, C3FREQREG, int(freq))
# #print freq
# #print hex(int(freq))
......@@ -148,7 +150,7 @@ if __name__ == "__main__":
# freq = 166000
# print "Automatically setting channel frequency to 166 kHz."
# farr[3] = freq
# freq = 1/(freq * 8*(10**(-9)))
# freq = 1/(freq * CTB_CLK_PER)
# testelma.write(slot, C4FREQREG, int(freq))
# #print freq
# #print hex(int(freq))
......@@ -164,7 +166,7 @@ if __name__ == "__main__":
# freq = 166000
# print "Automatically setting channel frequency to 166 kHz."
# farr[4] = freq
# freq = 1/(freq * 8*(10**(-9)))
# freq = 1/(freq * CTB_CLK_PER)
# testelma.write(slot, C5FREQREG, int(freq))
# #print freq
# #print hex(int(freq))
......@@ -180,7 +182,7 @@ if __name__ == "__main__":
freq = 166000
print "Automatically setting channel frequency to 166 kHz."
farr[5] = freq
freq = 1/(freq * 8*(10**(-9)))
freq = 1/(freq * CTB_CLK_PER)
testelma.write(slot, C6FREQREG, int(freq))
#print freq
#print hex(int(freq))
......
software/regtest/regtest.py
View file @ eced93bc
......@@ -8,7 +8,7 @@
#
# version: 1.0
#
# description:
# description:
#
# dependencies:
#
......@@ -29,7 +29,7 @@
# last changes:
# 2013-08-13 Theodor Stana t.stana@cern.ch File created
#===============================================================================
# TODO: -
# TODO: -
#===============================================================================
import random
......@@ -42,9 +42,9 @@ RAMSTART = 0x000
RAMEND = 0xFFF
if __name__ == "__main__":
ip = "elma" # raw_input("Crate IP? ")
ip = "cfvm-864-celma1" # raw_input("Crate IP? ")
user = "user" # raw_input("Username? ")
pwd = "public" # raw_input("Password? ")
pwd = "USER" # raw_input("Password? ")
# Wait for proper slot number
while 1:
......@@ -97,7 +97,7 @@ if __name__ == "__main__":
print " Seconds must be a decimal number >= 0!"
# Compute test end time according to current time
#
#
# time.time() returns time since start of epoch
# in seconds, so add secs, mins and hrs to that
start_time = time.time()
......@@ -120,7 +120,7 @@ if __name__ == "__main__":
wexcep_cnt = 0
rexcep_cnt = 0
mismatch_cnt = 0
br = 0
# Run test loop for the specified time
while time.time() < end_time:
......@@ -140,7 +140,7 @@ if __name__ == "__main__":
except VBCPException as e:
f.write("wex %i / %s / %s\r\n" % (i, time.strftime("%Y-%m-%d-%Hh%Mm%Ss",time.localtime()), e.strerror))
wexcep_cnt += 1
# Try a read from CONV-TTL-BLO, exception if unsuccessful
try:
rval = testelma.read(i, addr)
......@@ -150,8 +150,8 @@ if __name__ == "__main__":
if rval != wval:
mismatch_cnt += 1
f.write("mis %i / %s / %03x : %08x != %08x\r\n" % (i, time.strftime("%Y-%m-%d-%Hh%Mm%Ss",time.localtime()), addr, wval, rval))
br = 1
break
# br = 1
# break
except VBCPException as e:
f.write("rex %i / %s / %s\r\n" % (i, time.strftime("%Y-%m-%d-%Hh%Mm%Ss",time.localtime()), e.strerror))
......@@ -168,7 +168,7 @@ if __name__ == "__main__":
#
# # Write the regaddress value to the register
# wval = addr
#
#
# #f.write("a:%x w:%x " % (addr, wval))
#
# # Try a write to CONV-TTL-BLO, exception if unsuccessful
......@@ -189,15 +189,15 @@ if __name__ == "__main__":
# if rval != wval:
# mismatch_cnt += 1
# f.write("mis %i / %s / %03x : %08x != %08x\r\n" % (i, time.strftime("%Y-%m-%d-%Hh%Mm%Ss",time.localtime()), addr, wval, rval))
# br = 1
# break
## br = 1
## break
#
# except VBCPException as e:
# f.write("rex %i / %s / %s\r\n" % (i, time.strftime("%Y-%m-%d-%Hh%Mm%Ss",time.localtime()), e.strerror))
# rexcep_cnt += 1
## br = 1
## break
#
#
# # Increment regaddr, reset on overflow above 2^12
# addr += 4
......
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