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Conv TTL Blocking
Commit ee3b4c61 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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test00 & test07 complete

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hdl/pts/syn/Makefile 0 → 100644
View file @ ee3b4c61
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := conv_ttl_blo_v2.xise
ISE_CRAP := *.b conv_ttl_blo_v2_summary.html *.tcl conv_ttl_blo_v2.bld conv_ttl_blo_v2.cmd_log *.drc conv_ttl_blo_v2.lso *.ncd conv_ttl_blo_v2.ngc conv_ttl_blo_v2.ngd conv_ttl_blo_v2.ngr conv_ttl_blo_v2.pad conv_ttl_blo_v2.par conv_ttl_blo_v2.pcf conv_ttl_blo_v2.prj conv_ttl_blo_v2.ptwx conv_ttl_blo_v2.stx conv_ttl_blo_v2.syr conv_ttl_blo_v2.twr conv_ttl_blo_v2.twx conv_ttl_blo_v2.gise conv_ttl_blo_v2.unroutes conv_ttl_blo_v2.ut conv_ttl_blo_v2.xpi conv_ttl_blo_v2.xst conv_ttl_blo_v2_bitgen.xwbt conv_ttl_blo_v2_envsettings.html conv_ttl_blo_v2_guide.ncd conv_ttl_blo_v2_map.map conv_ttl_blo_v2_map.mrp conv_ttl_blo_v2_map.ncd conv_ttl_blo_v2_map.ngm conv_ttl_blo_v2_map.xrpt conv_ttl_blo_v2_ngdbuild.xrpt conv_ttl_blo_v2_pad.csv conv_ttl_blo_v2_pad.txt conv_ttl_blo_v2_par.xrpt conv_ttl_blo_v2_summary.xml conv_ttl_blo_v2_usage.xml conv_ttl_blo_v2_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=conv_ttl_blo_v2
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../top/conv_ttl_blo_v2.ucf \
../top/pts_regs.vhd \
../top/conv_ttl_blo_v2.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd \
../../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd \
../../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../../../ip_cores/general-cores/modules/common/gc_clk_div.vhd \
../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../rtm_detector/rtl/rtm_detector.vhd \
../../vme64x_i2c/rtl/i2c_slave.vhd \
../../vme64x_i2c/rtl/vme64x_i2c.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
run.tcl \
conv_ttl_blo_v2.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
hdl/pts/syn/Manifest.py 0 → 100644
View file @ ee3b4c61
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo_v2"
syn_project = "conv_ttl_blo_v2.xise"
modules = {
"local" : [
"../top"
]
}
hdl/pts/syn/conv_ttl_blo_v2.gise 0 → 100644
View file @ ee3b4c61
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="conv_ttl_blo_v2.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_CMD" xil_pn:name="_impact.cmd"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impact.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo_v2.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="conv_ttl_blo_v2.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="conv_ttl_blo_v2.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="conv_ttl_blo_v2.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="conv_ttl_blo_v2.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="conv_ttl_blo_v2.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_IMPACT_MISC" xil_pn:name="conv_ttl_blo_v2.mcs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_v2.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="conv_ttl_blo_v2.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="conv_ttl_blo_v2.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="conv_ttl_blo_v2.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="conv_ttl_blo_v2.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="conv_ttl_blo_v2.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="conv_ttl_blo_v2.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="conv_ttl_blo_v2.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_IMPACT_MISC" xil_pn:name="conv_ttl_blo_v2.prm"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="conv_ttl_blo_v2.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="conv_ttl_blo_v2.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="conv_ttl_blo_v2.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="conv_ttl_blo_v2.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="conv_ttl_blo_v2.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="conv_ttl_blo_v2.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo_v2.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="conv_ttl_blo_v2.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo_v2.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_v2_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_v2_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_v2_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_v2_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_v2_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="conv_ttl_blo_v2_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_v2_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="conv_ttl_blo_v2_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="conv_ttl_blo_v2_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_v2_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_v2_xst.xrpt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1364415005" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1364415005">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1364416893" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1364416893">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1364416893" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1364416893">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1364415005" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1364415005">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1364416893" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1364416893">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1364415005" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1364415005">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1364416893" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1364416893">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1364416905" xil_pn:in_ck="761168912318142379" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1364416893">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.lso"/>
<outfile xil_pn:name="conv_ttl_blo_v2.ngc"/>
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hdl/pts/syn/conv_ttl_blo_v2.mcs 0 → 100644
View file @ ee3b4c61
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/pts/syn/conv_ttl_blo_v2.prm 0 → 100644
View file @ ee3b4c61
PROMGEN: Xilinx Prom Generator P.28xd
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
promgen -spi -w -u 0 conv_ttl_blo_v2.bit
PROM conv_ttl_blo_v2.prm map: Wed Mar 27 16:36:24 2013
Format Mcs86 (32-bit)
Size 2048K
PROM start 0000:0000
PROM end 001f:ffff
Addr1 Addr2 Date File(s)
0000:0000 0016:a673 Mar 27 14:19:40 2013 conv_ttl_blo_v2.bit
hdl/pts/syn/conv_ttl_blo_v2.xise 0 → 100644
View file @ ee3b4c61
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<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
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<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="conv_ttl_blo_v2" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
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<file xil_pn:name="../top/conv_ttl_blo_v2.ucf" xil_pn:type="FILE_UCF">
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<file xil_pn:name="../top/pts_regs.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_clk_div.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../vme64x_i2c/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../vme64x_i2c/rtl/vme64x_i2c.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
</project>
hdl/pts/syn/run.tcl 0 → 100644
View file @ ee3b4c61
project open conv_ttl_blo_v2.xise
process run {Generate Programming File} -force rerun_all
hdl/pts/top/Manifest.py 0 → 100644
View file @ ee3b4c61
files = [
"conv_ttl_blo_v2.ucf",
"pts_regs.vhd",
"conv_ttl_blo_v2.vhd"
]
modules = {
"local" : [
"../../../../ip_cores/general-cores",
"../../reset_gen",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../../vme64x_i2c"
]
}
hdl/pts/top/conv_ttl_blo_v2.ucf 0 → 100644
View file @ ee3b4c61
##---------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##----------------------------------------
#NET "RST" LOC = N20;
#NET "RST" IOSTANDARD = LVTTL;
#NET "FPGA_SYSRESET_N" LOC = L20;
NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = LVTTL;
#NET "CLK20_VCXO" LOC = E16;
#TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50 %;
NET "FPGA_CLK_P" LOC = H12;
NET "FPGA_CLK_N" LOC = G11;
##======================================
##-- FRONT PANEL TTLs
##======================================
##-------------------
##-- LEDs
##-------------------
NET "LED_CTRL0" LOC = M18;
NET "LED_CTRL0" IOSTANDARD = LVTTL;
NET "LED_CTRL0_OEN" LOC = T20;
NET "LED_CTRL0_OEN" IOSTANDARD = LVTTL;
NET "LED_CTRL1" LOC = M17;
NET "LED_CTRL1" IOSTANDARD = LVTTL;
NET "LED_CTRL1_OEN" LOC = U19;
NET "LED_CTRL1_OEN" IOSTANDARD = LVTTL;
NET "LED_MULTICAST_2_0" LOC = P16;
NET "LED_MULTICAST_2_0" IOSTANDARD = LVTTL;
NET "LED_MULTICAST_3_1" LOC = P17;
NET "LED_MULTICAST_3_1" IOSTANDARD = LVTTL;
NET "LED_WR_GMT_TTL_TTLN" LOC = N16;
NET "LED_WR_GMT_TTL_TTLN" IOSTANDARD = LVTTL;
NET "LED_WR_LINK_SYSERROR" LOC = R15;
NET "LED_WR_LINK_SYSERROR" IOSTANDARD = LVTTL;
NET "LED_WR_OK_SYSPW" LOC = R16;
NET "LED_WR_OK_SYSPW" IOSTANDARD = LVTTL;
NET "LED_WR_OWNADDR_I2C" LOC = N15;
NET "LED_WR_OWNADDR_I2C" IOSTANDARD = LVTTL;
##-------------------
##-- Front channel LEDs
##-------------------
NET "PULSE_FRONT_LED_N[1]" LOC = H5;
NET "PULSE_FRONT_LED_N[1]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[1]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[1]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[2]" LOC = J6;
NET "PULSE_FRONT_LED_N[2]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[2]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[2]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[3]" LOC = K6;
NET "PULSE_FRONT_LED_N[3]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[3]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[3]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[4]" LOC = K5;
NET "PULSE_FRONT_LED_N[4]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[4]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[4]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[5]" LOC = M7;
NET "PULSE_FRONT_LED_N[5]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[5]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[5]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[6]" LOC = M6;
NET "PULSE_FRONT_LED_N[6]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[6]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[6]" SLEW = QUIETIO;
##-------------------
##-- Rear LEDs
##-------------------
NET "PULSE_REAR_LED_N[1]" LOC = AB17;
NET "PULSE_REAR_LED_N[1]" IOSTANDARD = LVCMOS33;
NET "PULSE_REAR_LED_N[1]" DRIVE = 4;
NET "PULSE_REAR_LED_N[1]" SLEW = QUIETIO;
NET "PULSE_REAR_LED_N[2]" LOC = AB19;
NET "PULSE_REAR_LED_N[2]" IOSTANDARD = LVCMOS33;
NET "PULSE_REAR_LED_N[2]" DRIVE = 4;
NET "PULSE_REAR_LED_N[2]" SLEW = QUIETIO;
NET "PULSE_REAR_LED_N[3]" LOC = AA16;
NET "PULSE_REAR_LED_N[3]" IOSTANDARD = LVCMOS33;
NET "PULSE_REAR_LED_N[3]" DRIVE = 4;
NET "PULSE_REAR_LED_N[3]" SLEW = QUIETIO;
NET "PULSE_REAR_LED_N[4]" LOC = AA18;
NET "PULSE_REAR_LED_N[4]" IOSTANDARD = LVCMOS33;
NET "PULSE_REAR_LED_N[4]" DRIVE = 4;
NET "PULSE_REAR_LED_N[4]" SLEW = QUIETIO;
NET "PULSE_REAR_LED_N[5]" LOC = AB16;
NET "PULSE_REAR_LED_N[5]" IOSTANDARD = LVCMOS33;
NET "PULSE_REAR_LED_N[5]" DRIVE = 4;
NET "PULSE_REAR_LED_N[5]" SLEW = QUIETIO;
NET "PULSE_REAR_LED_N[6]" LOC = AB18;
NET "PULSE_REAR_LED_N[6]" IOSTANDARD = LVCMOS33;
NET "PULSE_REAR_LED_N[6]" DRIVE = 4;
NET "PULSE_REAR_LED_N[6]" SLEW = QUIETIO;
###-------------------
###-- TTL trigger I/O
###-------------------
#NET "FPGA_INPUT_TTL_N[1]" LOC = T2;
#NET "FPGA_INPUT_TTL_N[1]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[2]" LOC = U3;
#NET "FPGA_INPUT_TTL_N[2]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[3]" LOC = V5;
#NET "FPGA_INPUT_TTL_N[3]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[4]" LOC = W4;
#NET "FPGA_INPUT_TTL_N[4]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[5]" LOC = T6;
#NET "FPGA_INPUT_TTL_N[5]" IOSTANDARD = LVCMOS33;
#NET "FPGA_INPUT_TTL_N[6]" LOC = T3;
#NET "FPGA_INPUT_TTL_N[6]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[1]" LOC = C1;
#NET "FPGA_OUT_TTL[1]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[2]" LOC = F2;
#NET "FPGA_OUT_TTL[2]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[3]" LOC = F5;
#NET "FPGA_OUT_TTL[3]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[4]" LOC = H4;
#NET "FPGA_OUT_TTL[4]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[5]" LOC = J4;
#NET "FPGA_OUT_TTL[5]" IOSTANDARD = LVCMOS33;
#NET "FPGA_OUT_TTL[6]" LOC = H2;
#NET "FPGA_OUT_TTL[6]" IOSTANDARD = LVCMOS33;
##-------------------
##-- Inverted TTL I/O
##--
##-- Schematics name: INV_IN_*
##---- renamed to INV_IN[*]
##-------------------
#NET "INV_IN_N[1]" LOC = V2;
#NET "INV_IN_N[1]" IOSTANDARD = LVCMOS33;
#NET "INV_IN_N[2]" LOC = W3;
#NET "INV_IN_N[2]" IOSTANDARD = LVCMOS33;
#NET "INV_IN_N[3]" LOC = Y2;
#NET "INV_IN_N[3]" IOSTANDARD = LVCMOS33;
#NET "INV_IN_N[4]" LOC = AA2;
#NET "INV_IN_N[4]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[1]" LOC = J3;
#NET "INV_OUT[1]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[2]" LOC = L3;
#NET "INV_OUT[2]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[3]" LOC = M3;
#NET "INV_OUT[3]" IOSTANDARD = LVCMOS33;
#NET "INV_OUT[4]" LOC = P2;
#NET "INV_OUT[4]" IOSTANDARD = LVCMOS33;
##======================================
##-- RTM signals
##======================================
##-- Blocking I/O
##
##-- Schematics name: FPGA_BLO_IN_*
##---- renamed to FPGA_BLO_IN[*]
##-------------------
#NET "FPGA_BLO_IN[1]" LOC = Y9;
#NET "FPGA_BLO_IN[1]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[2]" LOC = AA10;
#NET "FPGA_BLO_IN[2]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[3]" LOC = W12;
#NET "FPGA_BLO_IN[3]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[4]" LOC = AA6;
#NET "FPGA_BLO_IN[4]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[5]" LOC = Y7;
#NET "FPGA_BLO_IN[5]" IOSTANDARD = LVCMOS33;
#NET "FPGA_BLO_IN[6]" LOC = AA8;
#NET "FPGA_BLO_IN[6]" IOSTANDARD = LVCMOS33;
#
#NET "FPGA_TRIG_BLO[1]" LOC = W9;
#NET "FPGA_TRIG_BLO[1]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[2]" LOC = T10;
#NET "FPGA_TRIG_BLO[2]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[3]" LOC = V7;
#NET "FPGA_TRIG_BLO[3]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[4]" LOC = U9;
#NET "FPGA_TRIG_BLO[4]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[5]" LOC = T8;
#NET "FPGA_TRIG_BLO[5]" IOSTANDARD = LVCMOS33;
#NET "FPGA_TRIG_BLO[6]" LOC = R9;
#NET "FPGA_TRIG_BLO[6]" IOSTANDARD = LVCMOS33;
###======================================
###-- VME CONNECTOR SIGNALS
###======================================
###-------------------
###-- I2C lines
###-------------------
NET "SCL_I" LOC = F19;
NET "SCL_I" IOSTANDARD = LVTTL;
NET "SCL_O" LOC = E20;
NET "SCL_O" IOSTANDARD = LVTTL;
NET "SCL_O" DRIVE = 4;
NET "SCL_OE" LOC = H18;
NET "SCL_OE" IOSTANDARD = LVTTL;
NET "SCL_OE" DRIVE = 4;
# NET "SCL_OE" PULLDOWN;
NET "SDA_I" LOC = G20;
NET "SDA_I" IOSTANDARD = LVTTL;
NET "SDA_O" LOC = F20;
NET "SDA_O" IOSTANDARD = LVTTL;
NET "SDA_O" SLEW = FAST;
NET "SDA_O" DRIVE = 4;
# NET "SDA_O" PULLUP;
NET "SDA_OE" LOC = J19;
NET "SDA_OE" IOSTANDARD = LVTTL;
NET "SDA_OE" SLEW = FAST;
NET "SDA_OE" DRIVE = 4;
# NET "SDA_OE" PULLDOWN;
###-------------------
###-- Geographical Address
###-------------------
NET "FPGA_GA[0]" LOC = H20;
NET "FPGA_GA[0]" IOSTANDARD = LVTTL;
NET "FPGA_GA[1]" LOC = J20;
NET "FPGA_GA[1]" IOSTANDARD = LVTTL;
NET "FPGA_GA[2]" LOC = K19;
NET "FPGA_GA[2]" IOSTANDARD = LVTTL;
NET "FPGA_GA[3]" LOC = K20;
NET "FPGA_GA[3]" IOSTANDARD = LVTTL;
NET "FPGA_GA[4]" LOC = L19;
NET "FPGA_GA[4]" IOSTANDARD = LVTTL;
NET "FPGA_GAP" LOC = H19;
NET "FPGA_GAP" IOSTANDARD = LVTTL;
###-------------------
###-- ROM memory
###-------------------
#NET "FPGA_PROM_CCLK" LOC = Y20;
#NET "FPGA_PROM_CCLK" IOSTANDARD = LVTTL;
#NET "FPGA_PROM_CSO_B_N" LOC = AA3;
#NET "FPGA_PROM_CSO_B_N" IOSTANDARD = LVTTL;
#NET "FPGA_PROM_DIN" LOC = AA20;
#NET "FPGA_PROM_DIN" IOSTANDARD = LVTTL;
#NET "FPGA_PROM_MOSI" LOC = AB20;
#NET "FPGA_PROM_MOSI" IOSTANDARD = LVTTL;
#
#
####======================================
####-- WHITE RABBIT
####======================================
####-------------------
####-- Thermo for UID
####-------------------
##NET "THERMOMETER" LOC = B1;
## NET "THERMOMETER" IOSTANDARD = "LVCMOS25";
####-------------------
####-- DACs control
####--
####-- + CMOS 3.3V input
####-------------------
##NET "FPGA_PLLDAC1_DIN" LOC = AB14;
## NET "FPGA_PLLDAC1_DIN" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC1_SCLK" LOC = AA14;
## NET "FPGA_PLLDAC1_SCLK" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC1_SYNC_N" LOC = AB15;
## NET "FPGA_PLLDAC1_SYNC_N" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC2_DIN" LOC = W14;
## NET "FPGA_PLLDAC2_DIN" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC2_SCLK" LOC = Y14;
## NET "FPGA_PLLDAC2_SCLK" IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC2_SYNC_N" LOC = W13;
## NET "FPGA_PLLDAC2_SYNC_N" IOSTANDARD = "LVCMOS25";
####-------------------
####-- SFP connection
####-------------------
##NET "FPGA_SFP_LOS" LOC = G3;
## NET "FPGA_SFP_LOS" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_MOD_DEF0" LOC = K8;
## NET "FPGA_SFP_MOD_DEF0" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_RATE_SELECT" LOC = C4;
## NET "FPGA_SFP_RATE_SELECT" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_MOD_DEF1" LOC = G4;
## NET "FPGA_SFP_MOD_DEF1" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_MOD_DEF2" LOC = F3;
## NET "FPGA_SFP_MOD_DEF2" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_TX_DISABLE" LOC = E4;
## NET "FPGA_SFP_TX_DISABLE" IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_TX_FAULT" LOC = D2;
## NET "FPGA_SFP_TX_FAULT" IOSTANDARD = "LVCMOS33";
####-------------------
####-- FPGA MGT lines
####-------------------
##NET "FPGAMGTCLK0_P" LOC = A10;
## NET "FPGAMGTCLK0_P" IOSTANDARD = "LVDS_12";
##NET "FPGAMGTCLK0_N" LOC = B10;
## NET "FPGAMGTCLK0_N" IOSTANDARD = "LVDS_12";
##NET "MGTSFPRX0_P" LOC = D7;
## NET "MGTSFPRX0_P" IOSTANDARD = "LVDS_12";
##NET "MGTSFPRX0_N" LOC = C7;
## NET "MGTSFPRX0_N" IOSTANDARD = "LVDS_12";
##NET "MGTSFPTX0_P" LOC = B6;
## NET "MGTSFPTX0_P" IOSTANDARD = "LVDS_12";
##NET "MGTSFPTX0_N" LOC = A6;
## NET "MGTSFPTX0_N" IOSTANDARD = "LVDS_12";
#
#
###======================================
###-- ADDITIONAL PINS
###======================================
NET "FPGA_OE" LOC = R3;
NET "FPGA_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_OE" DRIVE = 4;
NET "FPGA_OE" SLEW = QUIETIO;
NET "FPGA_BLO_OE" LOC = P5;
NET "FPGA_BLO_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_BLO_OE" DRIVE = 4;
NET "FPGA_BLO_OE" SLEW = QUIETIO;
NET "FPGA_TRIG_TTL_OE" LOC = N3;
NET "FPGA_TRIG_TTL_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_TRIG_TTL_OE" DRIVE = 4;
NET "FPGA_TRIG_TTL_OE" SLEW = QUIETIO;
NET "FPGA_INV_OE" LOC = P6;
NET "FPGA_INV_OE" IOSTANDARD = LVCMOS33;
NET "FPGA_INV_OE" DRIVE = 4;
NET "FPGA_INV_OE" SLEW = QUIETIO;
###-------------------
###-- Configuration Switches
###
###-- Schematics name EXTRA_SWITCH_*
###---- renamed to EXTRA_SWITCH[*]
###-------------------
#NET "EXTRA_SWITCH[1]" LOC = F22;
#NET "EXTRA_SWITCH[1]" IOSTANDARD = LVCMOS33;
## NET "EXTRA_SWITCH[2]" LOC = G22;
## NET "EXTRA_SWITCH[2]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[3]" LOC = H21;
## NET "EXTRA_SWITCH[3]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[4]" LOC = H22;
## NET "EXTRA_SWITCH[4]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[5]" LOC = J22;
## NET "EXTRA_SWITCH[5]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[6]" LOC = K21;
## NET "EXTRA_SWITCH[6]" IOSTANDARD = "LVCMOS33";
## NET "EXTRA_SWITCH[7]" LOC = K22;
## NET "EXTRA_SWITCH[7]" IOSTANDARD = "LVCMOS33";
NET "LEVEL" LOC = L22;
NET "LEVEL" IOSTANDARD = LVCMOS33;
##-------------------
##-- Motherboard and piggyback IDs
##-------------------
NET "FPGA_RTMM_N[0]" LOC = V21;
NET "FPGA_RTMM_N[0]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[1]" LOC = V22;
NET "FPGA_RTMM_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[2]" LOC = U22;
NET "FPGA_RTMM_N[2]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[0]" LOC = W22;
NET "FPGA_RTMP_N[0]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[1]" LOC = Y22;
NET "FPGA_RTMP_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[2]" LOC = Y21;
NET "FPGA_RTMP_N[2]" IOSTANDARD = LVCMOS33;
####-------------------
####-- General purpose
####-------------------
## NET "FPGA_HEADER_OUT_N[1]" LOC = F15;
## NET "FPGA_HEADER_OUT_N[1]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[2]" LOC = F16;
## NET "FPGA_HEADER_OUT_N[2]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[3]" LOC = F17;
## NET "FPGA_HEADER_OUT_N[3]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[4]" LOC = F14;
## NET "FPGA_HEADER_OUT_N[4]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[5]" LOC = H14;
## NET "FPGA_HEADER_OUT_N[5]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_OUT_N[6]" LOC = H13;
## NET "FPGA_HEADER_OUT_N[6]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[1]" LOC = A17;
## NET "FPGA_HEADER_IN_N[1]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[2]" LOC = A18;
## NET "FPGA_HEADER_IN_N[2]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[3]" LOC = B18;
## NET "FPGA_HEADER_IN_N[3]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[4]" LOC = A19;
## NET "FPGA_HEADER_IN_N[4]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[5]" LOC = A20;
## NET "FPGA_HEADER_IN_N[5]" IOSTANDARD = "LVCMOS33";
## NET "FPGA_HEADER_IN_N[6]" LOC = B20;
## NET "FPGA_HEADER_IN_N[6]" IOSTANDARD = "LVCMOS33";
hdl/pts/top/conv_ttl_blo_v2.vhd 0 → 100644
View file @ ee3b4c61
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- http://www.ohwr.org/projects/conv-trig-blo
--------------------------------------------------------------------------------
--
-- unit name: conv_ttl_blo_v2.vhd
--
-- author: Theodor-Adrian Stana (t.stana@cern.ch)
-- Carlos Gil Soriano (gilsoriano@gmail.com)
--
-- version: 1.0
--
-- description: Top entity of CONV-TTL-BLO V1
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library IEEE;
library unisim;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VCOMPONENTS.ALL;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
entity conv_ttl_blo_v2 is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4
);
port
(
-- RST : in std_logic;
-- CLK20_VCXO : in std_logic;
FPGA_CLK_P : in std_logic; --Using the 125MHz clock
FPGA_CLK_N : in std_logic;
-- LEDs
LED_CTRL0 : out std_logic;
LED_CTRL0_OEN : out std_logic;
LED_CTRL1 : out std_logic;
LED_CTRL1_OEN : out std_logic;
LED_MULTICAST_2_0 : out std_logic;
LED_MULTICAST_3_1 : out std_logic;
LED_WR_GMT_TTL_TTLN : out std_logic;
LED_WR_LINK_SYSERROR : out std_logic;
LED_WR_OK_SYSPW : out std_logic;
LED_WR_OWNADDR_I2C : out std_logic;
-- I/Os for pulses
PULSE_FRONT_LED_N : out std_logic_vector(g_nr_ttl_chan downto 1);
PULSE_REAR_LED_N : out std_logic_vector(g_nr_ttl_chan downto 1);
-- FPGA_INPUT_TTL_N : in std_logic_vector(g_nr_ttl_chan downto 1);
-- FPGA_OUT_TTL : out std_logic_vector(g_nr_ttl_chan downto 1);
-- FPGA_BLO_IN : in std_logic_vector(g_nr_ttl_chan downto 1);
-- FPGA_TRIG_BLO : out std_logic_vector(g_nr_ttl_chan downto 1);
-- INV_IN_N : in std_logic_vector(g_nr_inv_chan downto 1);
-- INV_OUT : out std_logic_vector(g_nr_inv_chan downto 1);
-- Lines for the i2c_slave
SCL_I : in std_logic;
SCL_O : out std_logic;
SCL_OE : out std_logic;
SDA_I : in std_logic;
SDA_O : out std_logic;
SDA_OE : out std_logic;
FPGA_GA : in std_logic_vector(4 downto 0);
FPGA_GAP : in std_logic;
--
-- -- Pins of the SPI interface to write into the Flash memory
-- FPGA_PROM_CCLK : out std_logic;
-- FPGA_PROM_CSO_B_N : out std_logic;
-- FPGA_PROM_DIN : in std_logic;
-- FPGA_PROM_MOSI : out std_logic;
--
FPGA_OE : out std_logic;
FPGA_BLO_OE : out std_logic;
FPGA_TRIG_TTL_OE : out std_logic;
FPGA_INV_OE : out std_logic;
-- TTL/INV_TTL_N
LEVEL : in std_logic;
-- EXTRA_SWITCH : in std_logic_vector(7 downto 1);
-- It allows power sequencing of the
-- 24V rail after a security given delay
MR_N : out std_logic;
-- RTM identifiers, should match with the expected values
-- TODO: add matching
FPGA_RTMM_N : in std_logic_vector(2 downto 0);
FPGA_RTMP_N : in std_logic_vector(2 downto 0)
);
end conv_ttl_blo_v2;
architecture behav of conv_ttl_blo_v2 is
--============================================================================
-- Type declarations
--============================================================================
type t_pts_state is
(
ST_TEST00,
ST_TEST11
);
--============================================================================
-- Constant declarations
--============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : NATURAL := 1;
constant c_nr_slaves : NATURAL := 1;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word aligned
-----------------------------------------
-- M25P32 [0200-03FF]
-- MULTIBOOT [0080-00CF]
-- I2C_SLAVE [0040-007F]
-- SR [0000-003F]
-----------------------------------------
-- base address definitions
constant c_addr_pts_regs : t_wishbone_address := x"00000000";
constant c_addr_i2c_bridge : t_wishbone_address := X"00000040";
constant c_addr_multiboot : t_wishbone_address := X"00000080";
constant c_addr_m25p32 : t_wishbone_address := X"00000200";
-- address mask definitions
-- 64 words per page: 6 + 1 bits
constant c_mask_pts_regs : t_wishbone_address := X"FFFFFFF0";
constant c_mask_i2c_bridge : t_wishbone_address := X"FFFFFFC0";
constant c_mask_multiboot : t_wishbone_address := X"FFFFFFC0";
constant c_mask_m25p32 : t_wishbone_address := X"FFFFFE00";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves - 1 downto 0)
:= (
(others => c_addr_pts_regs)
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves - 1 downto 0)
:= (
(others => c_mask_pts_regs)
);
--============================================================================
-- Component declarations
--============================================================================
-- Reset generator component
-- (use: global reset generation, output reset generation)
component reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 5_000_000
);
port
(
clk_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
-- RTM detector component
-- (use: detect the presence of an RTM/P module)
component rtm_detector is
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end component rtm_detector;
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
component vme64x_i2c is
port
(
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
-- I2C address and status
i2c_addr_i : in std_logic_vector(6 downto 0);
i2c_done_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
wbm_cyc_o : out std_logic;
wbm_sel_o : out std_logic_vector(3 downto 0);
wbm_we_o : out std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_adr_o : out std_logic_vector(31 downto 0);
wbm_ack_i : in std_logic;
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end component vme64x_i2c;
-- Regs to test I2C operation
component pts_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'current test' in reg: 'control register'
pts_ctrl_crrt_test_o : out std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 't00'
pts_t00_bits_o : out std_logic_vector(31 downto 0)
);
end component pts_regs;
--============================================================================
-- Signal declarations
--============================================================================
-- Clock signals
signal clk_125 : std_logic;
-- Reset signals
signal rst_n, rst : std_logic;
-- RTM detection signals
signal rtmm, rtmp : std_logic_vector(2 downto 0);
signal rtmm_ok, rtmp_ok : std_logic;
-- Signals for pulse generation triggers
signal trig : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_inv : std_logic_vector(g_nr_inv_chan downto 1);
signal trig_ttl, trig_blo : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for blocking and TTL pulse outputs
signal pulse_outputs : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for inverted-TTL pulse outputs
signal inv_outputs : std_logic_vector(g_nr_inv_chan downto 1);
-- Pulse status LED signals
signal front_led_en : std_logic_vector(g_nr_ttl_chan downto 1);
signal rear_led_en : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_leds : std_logic_vector(g_nr_ttl_chan downto 1);
-- Output enable signals
signal oe, ttl_oe, blo_oe, inv_oe : std_logic;
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array (c_nr_slaves - 1 downto 0);
-- I2C bridge signals
signal i2c_done : std_logic;
signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
-- PTS-specific signals
signal pts_state : t_pts_state;
signal pts_crrt_test : std_logic_vector(3 downto 0);
signal cnt_halfsec : unsigned(25 downto 0);
signal led_seq : unsigned( 4 downto 0);
begin
--============================================================================
-- Generate 125 MHz global signal from differential lines
--============================================================================
cmp_125_diff_buf: IBUFGDS
generic map
(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE
)
port map
(
I => FPGA_CLK_P,
IB => FPGA_CLK_N,
O => clk_125
);
--============================================================================
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for 96ms power-on reset
cmp_reset_gen: reset_gen
generic map
(
-- Reset time: 12 * 8ns * (10**6) = 96 ms
g_reset_time => 12*(10**6)
)
port map
(
clk_i => clk_125,
rst_n_o => rst_n
);
rst <= not rst_n;
MR_N <= rst_n;
--============================================================================
-- Output enable logic
--============================================================================
-- The general output enable is set first and the blocking, TTL
-- and INV output enable signals are set one clock cycle later.
p_oe: process(clk_125)
begin
if rising_edge(clk_125) then
if (rst_n = '0') then
oe <= '0';
blo_oe <= '0';
ttl_oe <= '0';
inv_oe <= '0';
else
oe <= '0';
if (oe = '1') then
blo_oe <= '1';
ttl_oe <= '1';
inv_oe <= '1';
end if;
end if;
end if;
end process p_oe;
FPGA_OE <= oe;
FPGA_BLO_OE <= blo_oe;
FPGA_TRIG_TTL_OE <= ttl_oe;
FPGA_INV_OE <= inv_oe;
--============================================================================
-- I2C bridge logic
--============================================================================
i2c_addr <= "10" & FPGA_GA;
cmp_i2c_bridge: vme64x_i2c
port map
(
-- Clock, reset
clk_i => clk_125,
rst_n_i => rst_n,
-- I2C lines
sda_en_o => SDA_OE,
sda_i => SDA_I,
sda_o => SDA_O,
scl_en_o => SCL_OE,
scl_i => SCL_I,
scl_o => SCL_O,
-- I2C address and status
i2c_addr_i => i2c_addr,
i2c_done_o => i2c_done,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
wbm_cyc_o => xbar_slave_in(0).cyc,
wbm_sel_o => xbar_slave_in(0).sel,
wbm_we_o => xbar_slave_in(0).we,
wbm_dat_i => xbar_slave_out(0).dat,
wbm_dat_o => xbar_slave_in(0).dat,
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Process to set the I2C_UP signal for display on the front panel
-- of the front module. The I2C_UP signal is permanently set once an
-- I2C transfer has successfully completed, as signaled by the RD_DONE
-- and WR_DONE outputs of the I2C slave.
p_i2c_up: process (clk_125) is
begin
if rising_edge(clk_125) then
if (rst_n = '0') then
i2c_up <= '0';
elsif (i2c_done = '1') then
i2c_up <= '1';
end if;
end if;
end process p_i2c_up;
--============================================================================
-- Output enable logic
--============================================================================
-- Regs to test I2C operation
cmp_pts_regs: pts_regs
port map
(
rst_n_i => rst_n,
clk_sys_i => clk_125,
wb_adr_i => xbar_master_out(0).adr(2 downto 2),
wb_dat_i => xbar_master_out(0).dat,
wb_dat_o => xbar_master_in(0).dat,
wb_cyc_i => xbar_master_out(0).cyc,
wb_sel_i => xbar_master_out(0).sel,
wb_stb_i => xbar_master_out(0).stb,
wb_we_i => xbar_master_out(0).we,
wb_ack_o => xbar_master_in(0).ack,
wb_stall_o => xbar_master_in(0).stall,
-- PTS control register
pts_ctrl_crrt_test_o => pts_crrt_test,
-- PTS T00 register
pts_t00_bits_o => open
);
--============================================================================
-- Instantiation and connection of a Wishbone crossbar module
--============================================================================
-- xbar_master_in(0).stall <= '0';
xbar_master_in(0).int <= '0';
xbar_master_in(0).err <= '0';
cmp_wb_crossbar: xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
-- Address of the slaves connected
-- It should be noted that the default address length is 32
-- In our project only 16 bits are addressable
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk_125,
rst_n_i => rst_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
PULSE_FRONT_LED_N <= "111110" when (led_seq = 1) else
"111101" when (led_seq = 2) else
"111011" when (led_seq = 3) else
"110111" when (led_seq = 4) else
"101111" when (led_seq = 5) else
"011111" when (led_seq = 6) else
"111110" when (led_seq = 7) else
"111101" when (led_seq = 8) else
"111011" when (led_seq = 9) else
"110111" when (led_seq = 10) else
"101111" when (led_seq = 11) else
"011111" when (led_seq = 12) else
"111110" when (led_seq = 13) else
"111101" when (led_seq = 14) else
"111011" when (led_seq = 15) else
"110111" when (led_seq = 16) else
"101111" when (led_seq = 17) else
"011111" when (led_seq = 18) else
"111110" when (led_seq = 19) else
"111101" when (led_seq = 20) else
"111011" when (led_seq = 21) else
"110111" when (led_seq = 22) else
"101111" when (led_seq = 23) else
"011111" when (led_seq = 24) else
"111111";
PULSE_REAR_LED_N <= "111110" when (led_seq = 1) else
"111101" when (led_seq = 2) else
"111011" when (led_seq = 3) else
"110111" when (led_seq = 4) else
"101111" when (led_seq = 5) else
"011111" when (led_seq = 6) else
"111110" when (led_seq = 7) else
"111101" when (led_seq = 8) else
"111011" when (led_seq = 9) else
"110111" when (led_seq = 10) else
"101111" when (led_seq = 11) else
"011111" when (led_seq = 12) else
"111110" when (led_seq = 13) else
"111101" when (led_seq = 14) else
"111011" when (led_seq = 15) else
"110111" when (led_seq = 16) else
"101111" when (led_seq = 17) else
"011111" when (led_seq = 18) else
"111110" when (led_seq = 19) else
"111101" when (led_seq = 20) else
"111011" when (led_seq = 21) else
"110111" when (led_seq = 22) else
"101111" when (led_seq = 23) else
"011111" when (led_seq = 24) else
"111111";
--============================================================================
-- FSM logic
--============================================================================
p_fsm: process(clk_125) is
begin
if rising_edge(clk_125) then
if (rst_n = '0') then
pts_state <= ST_TEST00;
cnt_halfsec <= (others => '0');
led_seq <= (others => '0');
else
case pts_state is
when ST_TEST00 =>
if (pts_crrt_test = x"7") then
pts_state <= ST_TEST11;
end if;
when ST_TEST11 =>
cnt_halfsec <= cnt_halfsec + 1;
if (cnt_halfsec = 62499999) then
cnt_halfsec <= (others => '0');
led_seq <= led_seq + 1;
if (led_seq = 24) then
led_seq <= (others => '0');
pts_state <= ST_TEST00;
end if;
end if;
when others =>
pts_state <= ST_TEST00;
end case;
end if;
end if;
end process p_fsm;
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
bicolor_led_state <= "000000000001000000000000" when (led_seq = 1) else
"000000000100000000000000" when (led_seq = 2) else
"000000010000000000000000" when (led_seq = 3) else
"000001000000000000000000" when (led_seq = 4) else
"000000000000000001000000" when (led_seq = 5) else
"000000000000000000010000" when (led_seq = 6) else
"000000000000000000000100" when (led_seq = 7) else
"000000000000000000000001" when (led_seq = 8) else
"000000000000000100000000" when (led_seq = 9) else
"000000000000010000000000" when (led_seq = 10) else
"000100000000000000000000" when (led_seq = 11) else
"010000000000000000000000" when (led_seq = 12) else
"000000000010000000000000" when (led_seq = 13) else
"000000001000000000000000" when (led_seq = 14) else
"000000100000000000000000" when (led_seq = 15) else
"000010000000000000000000" when (led_seq = 16) else
"000000000000000010000000" when (led_seq = 17) else
"000000000000000000100000" when (led_seq = 18) else
"000000000000000000001000" when (led_seq = 19) else
"000000000000000000000010" when (led_seq = 20) else
"000000000000001000000000" when (led_seq = 21) else
"000000000000100000000000" when (led_seq = 22) else
"001000000000000000000000" when (led_seq = 23) else
"100000000000000000000000" when (led_seq = 24) else
"000000000000000000000000";
cmp_bicolor_led_ctrl: bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
g_NB_LINE => 2,
g_clk_freq => 125000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk_125,
rst_n_i => rst_n,
led_intensity_i => "0011111",
led_state_i => bicolor_led_state,
column_o(0) => LED_WR_OWNADDR_I2C,
column_o(1) => LED_WR_GMT_TTL_TTLN,
column_o(2) => LED_WR_LINK_SYSERROR,
column_o(3) => LED_WR_OK_SYSPW,
column_o(4) => LED_MULTICAST_2_0,
column_o(5) => LED_MULTICAST_3_1,
line_o(0) => LED_CTRL0,
line_o(1) => LED_CTRL1,
line_oen_o(0) => LED_CTRL0_OEN,
line_oen_o(1) => LED_CTRL1_OEN
);
--============================================================================
-- RTM detection logic
--============================================================================
rtmm <= not FPGA_RTMM_N;
rtmp <= not FPGA_RTMP_N;
cmp_rtm_detector: rtm_detector
port map
(
rtmm_i => rtmm,
rtmp_i => rtmp,
rtmm_ok_o => rtmm_ok,
rtmp_ok_o => rtmp_ok
);
end behav;
hdl/pts/top/pts_regs.vhd 0 → 100644
View file @ ee3b4c61
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for PTS registers
---------------------------------------------------------------------------------------
-- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created : Wed Mar 27 17:33:09 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pts_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'current test' in reg: 'control register'
pts_ctrl_crrt_test_o : out std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 't00'
pts_t00_bits_o : out std_logic_vector(31 downto 0)
);
end pts_regs;
architecture syn of pts_regs is
signal pts_ctrl_crrt_test_int : std_logic_vector(3 downto 0);
signal pts_t00_bits_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(0 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pts_ctrl_crrt_test_int <= "0000";
pts_t00_bits_int <= x"424C4F32";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(0) is
when '0' =>
if (wb_we_i = '1') then
pts_ctrl_crrt_test_int <= wrdata_reg(3 downto 0);
end if;
rddata_reg(3 downto 0) <= pts_ctrl_crrt_test_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when '1' =>
if (wb_we_i = '1') then
pts_t00_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pts_t00_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- current test
pts_ctrl_crrt_test_o <= pts_ctrl_crrt_test_int;
-- bits
pts_t00_bits_o <= pts_t00_bits_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/pts/top/pts_regs.wb 0 → 100644
View file @ ee3b4c61
peripheral {
name = "PTS registers";
description = "Registers of the PTS firmware";
hdl_entity = "pts_regs";
prefix = "pts";
reg {
name = "control register";
prefix = "ctrl";
field {
name = "current test";
prefix = "crrt_test";
type = SLV;
size = 4;
};
};
reg {
name = "t00";
prefix = "t00";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
};
hdl/vme64x_i2c/Manifest.py 0 → 100644
View file @ ee3b4c61
modules = {"local" : "rtl"}
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