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Commit ef23e750 authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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Updated image1: crossbar added. I2C module, multiboot, m25p32 integrated with… 

Updated image1: crossbar added. I2C module, multiboot, m25p32 integrated with basic_trigger. Tests on the way.
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hdl/IMAGES/image1/.gitignore 0 → 100644
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#Ignore LaTeX trash
#doc/.*
#doc/.*_*
#doc/*.*
#doc/.*.*.swp
#doc/.*.*.swp
#doc/Figures/*.eps
#!doc/*.tex
#!doc/*.pdf
#Ignore autotrash from ISE
project/*
project/*/
!project/image1.gise
!project/image1.xise
!project/image1.tcl
#!project/waveform/
#Ignore swap files at rtl/ and test/ folders
rtl/.*.*.swo
rtl/.*.*.swp
rtl/.swo
rtl/.swp
test/.swo
test/.swp
test/.*.*.swo
test/.*.*.swp
hdl/IMAGES/image1/build_image.sh 0 → 100644
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#! /bin/bash
echo "Running ./project/image1.tcl script to rebuild project"
echo "Log files can be found in ./build_reports"
BUILD_DIR="./project/reports/trash"
BITSTREAM_DIR="./project/bitstream"
echo "Cleaning-up eventually ISE temporary files"
rm -r ./project/iseconfig
rm -r ./project/_xmsgs
if [ ! -d "$BUILD_DIR" ]; then
echo "Creating not previously existing $BUILD_DIR"
mkdir -p $BUILD_DIR
fi
if [ ! -d "$BITSTREAM_DIR" ]; then
echo "Creating not previously existing $BITSTREAM_DIR"
mkdir -p $BITSTREAM_DIR
fi
cd $BUILD_DIR
echo "Executig tcl script from project folder"
pwd
xtclsh ../../image1.tcl rebuild_project
wait
echo "Log files are available"
cp image1_top.bld ../ngd.log &
cp image1_top.syr ../synthesis.log &
cp image1_top_summary.html ../summary.html
cd ../../..
#echo "Updating bitstream"
#cp $BUILD_DIR $BITSTREAM_DIR
##echo "Removing trash folder"
##rm -r $BUILD_DIR
hdl/IMAGES/image1/constraints/FPGAbank.ucf
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hdl/IMAGES/image1/project/image1.gise 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="image1.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="basic_trigger_top.vhi"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="i2c_slave_top.vhi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="image1_top.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="image1_top.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="image1_top.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="image1_top.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="image1_top.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="image1_top.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="image1_top.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="image1_top.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="image1_top.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="image1_top.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="image1_top_envsettings.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="image1_top_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="image1_top_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="image1_top_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_ngdbuild.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="image1_top_summary.html"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_xst.xrpt"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="m25p32_top.vhi"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1112065682908869959" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6110598410798097591" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8460592660931398612" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1354121484" xil_pn:in_ck="3132874348333545949" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1354121385">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="image1_top.lso"/>
<outfile xil_pn:name="image1_top.ngc"/>
<outfile xil_pn:name="image1_top.ngr"/>
<outfile xil_pn:name="image1_top.prj"/>
<outfile xil_pn:name="image1_top.stx"/>
<outfile xil_pn:name="image1_top.syr"/>
<outfile xil_pn:name="image1_top.xst"/>
<outfile xil_pn:name="image1_top_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1354033300" xil_pn:in_ck="-7461616560160808584" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1354033300">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1354033381" xil_pn:in_ck="4649869214785825988" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1354033375">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1354033402" xil_pn:in_ck="4649869214785825989" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1354033381">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
</transforms>
</generated_project>
hdl/IMAGES/image1/project/image1.tcl 0 → 100644
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hdl/IMAGES/image1/project/image1.xise
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hdl/IMAGES/image1/rtl/image1_pkg.vhd
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library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--! Packages from IP cores
use work.wishbone_pkg.ALL;
use work.i2c_slave_pkg.ALL;
use work.m25p32_pkg.ALL;
use work.multiboot_pkg.ALL;
use work.rtm_detector_pkg.ALL;
package image1_pkg is
constant c_WB_CLK_PERIOD : TIME := 8 ns;
constant c_RST_CLKS : NATURAL := 256; --! @8ns
constant c_NUM_MASTERS : NATURAL := 1;
constant c_NUM_SLAVES : NATURAL := 3;
constant c_MASTER_I2C_SLAVE : NATURAL := 0;
constant c_SLAVE_I2C_SLAVE : NATURAL := 0;
constant c_SLAVE_MULTIBOOT : NATURAL := 1;
constant c_SLAVE_M25P32 : NATURAL := 2;
constant c_ADDR_MULTIBOOT : t_wishbone_address := X"00000200";
constant c_ADDR_M25P32 : t_wishbone_address := X"00000080";
constant c_ADDR_I2C_SLAVE : t_wishbone_address := X"00000040";
--! 64 words per page: 6 + 1 bits
constant c_MASK_M25P32 : t_wishbone_address := X"FFFFFFE0";
constant c_MASK_MULTIBOOT : t_wishbone_address := X"FFFFFFC0";
constant c_MASK_I2C_SLAVE : t_wishbone_address := X"FFFFFFC0";
constant c_addresses : t_wishbone_address_array(c_NUM_SLAVES - 1 downto 0)
:= (c_ADDR_MULTIBOOT,
c_ADDR_M25P32,
c_ADDR_I2C_SLAVE);
constant c_masks : t_wishbone_address_array(c_NUM_SLAVES - 1 downto 0)
:= (c_MASK_MULTIBOOT,
c_MASK_M25P32,
c_MASK_I2C_SLAVE);
component basic_trigger_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (
FPGA_CLK_P : in STD_LOGIC;
FPGA_CLK_N : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
--! WR LEDs not to let them ON
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1));
port (clk_125m_i : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
--! WR LEDs not to let them ON
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1));
end component;
component i2c_slave_top
generic(g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns
port(sda_oen : out STD_LOGIC;
......@@ -108,6 +145,37 @@ package image1_pkg is
prom_din_i : in STD_LOGIC);
end component;
component multiboot_top
generic(g_MBA_addr : UNSIGNED (23 downto 0) := UNSIGNED(c_MBA_map_addr);
g_GBA_addr : UNSIGNED (23 downto 0) := UNSIGNED(c_GBA_map_addr);
--! This is a vendor-dependant SPI opcode.
--! Pleasem take a look to the flash memory manual and put here
--! the op-code/instruction-code for a read operation over SPI
--! i.e. for m25p32 memory that corresponds to X"03"
--! Set it up accordingly.
g_READ_SPI_OPCODE : STD_LOGIC_VECTOR(7 downto 0) := X"03");
port(wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC);
end component;
component rtm_detector
generic(g_identifier_RTMM : t_RTMM := RTMM_V1;
g_identifier_RTMP : t_RTMP := RTMP_BLOCKING_V1);
port (RTMM_i : in STD_LOGIC_VECTOR(2 downto 0);
RTMP_i : in STD_LOGIC_VECTOR(2 downto 0);
ok_RTMM_o : out STD_LOGIC;
ok_RTMP_o : out STD_LOGIC);
end component;
end image1_pkg;
......
hdl/IMAGES/image1/rtl/image1_top.vhd
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hdl/IMAGES/image1/rtl/image1_top.vhd_OLD 0 → 100644
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hdl/IMAGES/image1/test/image1_top_tb.vhd_OLD 0 → 100644
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