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Conv TTL Blocking
Commit f00ea2e7 authored by gilsoriano's avatar gilsoriano
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More code to go. Test to be added shortly.

parent f764b158
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Showing with 239 additions and 85 deletions
hdl/spi_master_multifield/rtl/spi_master_pkg.vhd
View file @ f00ea2e7
......@@ -39,8 +39,8 @@ package spi_master_pkg is
-- Wishbone access: 32 bits
----------------------------------------
-- BIT NAME DESCRIPTION
-- 0 PUSH_DATA PUSH DATA bytes into internal SPI
-- core memory
-- 0 PUSH_DATA PUSH DATA bytes into internal SPI
-- core memory
-- 1 PUSH_ADDR PUSH ADDRess bytes into internal SPI
-- core memory
-- 2 PUSH_INST PUSH INSTruction bytes into internal
......@@ -81,6 +81,12 @@ package spi_master_pkg is
constant c_CLK_DIVISION_LOGSIZE : NATURAL := 2;
constant c_COUNTER_DATA_WIDTH : NATURAL := 8;
constant c_CKL_I_PERIOD : NATURAL := 50; --! ns
constant c_CS_SU_SPI : NATURAL := 20; --! ns
constant c_CS_SU_TICKS : NATURAL := c_CS_SU_SPI/c_CLK_I_PERIOD + 1;
constant c_CS_HOLD_SPI : NATURAL := 100; --! ns
constant c_CS_HOLD_TICKS: NATURAL := c_CS_HOLD_SPI/c_CLK_I_PERIOD + 1;
constant c_SPI0_addr : STD_LOGIC_VECTOR (3 downto 0) := X"0";
constant c_SPI1_addr : STD_LOGIC_VECTOR (3 downto 0) := X"1";
......
hdl/spi_master_multifield/rtl/spi_master_regs.vhd
View file @ f00ea2e7
......@@ -18,24 +18,44 @@
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use work.spi_master_pkg.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spi_master_regs is
wb_rst_i : STD_LOGIC;
wb_clk_i : STD_LOGIC;
wb_stb_i : STD_LOGIC;
wb_cyc_i : STD_LOGIC;
wb_sel_i : STD_LOGIC_VECTOR (3 downto 0);
wb_we_i : STD_LOGIC;
wb_data_i : STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : STD_LOGIC_VECTOR (31 downto 0);
wb_ack_o : STD_LOGIC;
wb_rty_o : STD_LOGIC;
wb_err_o : STD_LOGIC;
inst_i : STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
addr_i : STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
data_i : STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);
SPI0_i : STD_LOGIC_VECTOR (31 downto 0);
SPI1_i : STD_LOGIC_VECTOR (31 downto 0);
);
end spi_master_regs;
architecture Behavioral of spi_master_regs is
begin
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
else
end if;
else
end if;
end Behavioral;
hdl/spi_master_multifield/rtl/spi_master_top.vhd
View file @ f00ea2e7
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 17:33:55 06/14/2012
-- Design Name:
-- Create Date: 17:10:27 06/15/2012
-- Design Name:
-- Module Name: spi_master_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- Project Name: CTDAH/SVEC
-- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description: This is a spi_master with programable field length and progra
-- mable setup and hold chip select times.
--
-- Dependencies:
--
......@@ -18,24 +19,84 @@
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use work.spi_master_pkg.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spi_master_top is
port(
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_we_i : in STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
spi_mosi_o : out STD_LOGIC;
spi_miso_i : in STD_LOGIC;
spi_clk_o : out STD_LOGIC;
spi_cs_n_o : out STD_LOGIC
);
end spi_master_top;
architecture Behavioral of spi_master_top is
signal s_inst : STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
signal s_addr : STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
signal s_data : STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);
signal s_SPI0 : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI1 : STD_LOGIC_VECTOR (31 downto 0);
begin
inst_spi_master_core: spi_master_core
port map(
rst_i => wb_rst_i,
clk_i => wb_clk,
inst_i => s_inst,
addr_i => s_addr,
data_i => s_data,
SPI0_i => s_SPI0,
SPI1_i => s_SPI1,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
spi_clk_o => spi_clk_o,
spi_cs_n_o => spi_cs_n_o
);
inst_spi_master_regs: spi_master_regs
port map(
wb_rst_i => wb_rst_i,
wb_clk_i => wb_clk,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_we_i => wb_we_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
inst_i => s_inst,
addr_i => s_addr,
data_i => s_data,
SPI0_i => s_SPI0,
SPI1_i => s_SPI1
);
end Behavioral;
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