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Conv TTL Blocking
Commit fa473234 authored by gilsoriano's avatar gilsoriano
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Nighty night... Corrected top and core. Now it is all about tb...

parent 08f7ee8b
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hdl/m25p32/rtl/m25p32_core.vhd
View file @ fa473234
...@@ -55,9 +55,9 @@ entity m25p32_core is ...@@ -55,9 +55,9 @@ entity m25p32_core is
sclk_o : out STD_LOGIC; sclk_o : out STD_LOGIC;
ss_n_o : out STD_LOGIC; ss_n_o : out STD_LOGIC;
s_wr_data_i : in STD_LOGIC_VECTOR(g_PAGE_SIZE*8 - 1 downto 0); wr_data_i : in STD_LOGIC_VECTOR(g_PAGE_SIZE*8 - 1 downto 0);
s_rd_data_o : out STD_LOGIC_VECTOR(g_READ_LENGTH*8 - 1 downto 0); rd_data_o : out STD_LOGIC_VECTOR(g_READ_LENGTH*8 - 1 downto 0);
SR_m25p32_i : in STD_LOGIC_VECTOR(r_SR_m25p32'length - 1 downto 0); SR_m25p32_i : in STD_LOGIC_VECTOR(r_SR_m25p32'a_length - 1 downto 0);
FMI_io : inout STD_LOGIC_VECTOR (r_FMI'a_length - 1 downto 0) FMI_io : inout STD_LOGIC_VECTOR (r_FMI'a_length - 1 downto 0)
); );
...@@ -107,13 +107,14 @@ begin ...@@ -107,13 +107,14 @@ begin
s_FMI.OP <= s_FMI_tmp.OP; s_FMI.OP <= s_FMI_tmp.OP;
s_FMI.PG <= s_FMI_tmp.PG; s_FMI.PG <= s_FMI_tmp.PG;
s_FMI.SCT <= s_FMI_tmp.SCT; s_FMI.SCT <= s_FMI_tmp.SCT;
FMI_io.OPA <= s_FMI.OPA; --! Not the most stylish way of doing the assignment, but it works
FMI_io.OPF <= s_FMI.OPF; FMI_io(1) <= s_FMI.OPA;
FMI_io(2) <= s_FMI.OPF;
s_SPI0_slv <= f_STD_LOGIC_VECTOR(s_SPI0); s_SPI0_slv <= f_STD_LOGIC_VECTOR(s_SPI0);
s_SPI1_slv <= f_STD_LOGIC_VECTOR(s_SPI1); s_SPI1_slv <= f_STD_LOGIC_VECTOR(s_SPI1);
s_SPI2 <= f_SPI2(s_SPI2_slv); s_SPI2 <= f_SPI2(s_SPI2_slv);
s_SPI3 <= f_SPI2(s_SPI3_slv); s_SPI3 <= f_SPI3(s_SPI3_slv);
inst_spi_master_core: spi_master_core inst_spi_master_core: spi_master_core
...@@ -160,9 +161,9 @@ begin ...@@ -160,9 +161,9 @@ begin
--! s_MEM_fsm_d0 One clock delay of s_MEM_fsm --! s_MEM_fsm_d0 One clock delay of s_MEM_fsm
p_comb_SPIx : process (s_MEM_fsm, s_MEM_fsm_d0) p_comb_SPIx : process (s_MEM_fsm, s_MEM_fsm_d0)
procedure registers_setup (operation :s_FMI.OP) is procedure registers_setup (operation : t_operations) is
begin begin
case s_FMI.OP is case operation is
when RDID => when RDID =>
s_SPI0 <= c_SPI0_RDID; s_SPI0 <= c_SPI0_RDID;
s_SPI1 <= c_SPI1_RDID; s_SPI1 <= c_SPI1_RDID;
...@@ -190,9 +191,9 @@ begin ...@@ -190,9 +191,9 @@ begin
end case; end case;
end procedure; end procedure;
procedure place_inst (operation :s_FMI.OP) is procedure place_inst (operation : t_operations) is
begin begin
case s_FMI.OP is case operation is
when RDID => when RDID =>
s_inst_spi <= c_RDID_INST; s_inst_spi <= c_RDID_INST;
when RDSR => when RDSR =>
...@@ -211,13 +212,13 @@ begin ...@@ -211,13 +212,13 @@ begin
end case; end case;
end procedure; end procedure;
procedure place_addr (operation :s_FMI.OP) is procedure place_addr (operation : t_operations) is
constant c_offset : NATURAL := c_SECTOR_BITS constant c_offset : NATURAL := c_SECTOR_BITS
+ c_PAGES_PER_SECTOR_BITS - 1 + 3; + c_PAGES_PER_SECTOR_BITS - 1 + 3;
variable v_s_addr_spi : STD_LOGIC_VECTOR(23 downto 0); variable v_addr_spi : STD_LOGIC_VECTOR(23 downto 0);
begin begin
v_addr_spi := (others => '0'); v_addr_spi := (others => '0');
case s_FMI.OP is case operation is
when READ => when READ =>
v_addr_spi( c_offset downto 0) := s_FMI.SCT v_addr_spi( c_offset downto 0) := s_FMI.SCT
& s_FMI.PG & s_FMI.PG
...@@ -239,10 +240,13 @@ begin ...@@ -239,10 +240,13 @@ begin
s_addr_spi <= v_addr_spi; s_addr_spi <= v_addr_spi;
end procedure; end procedure;
procedure place_data (operation : s_FMI.OP) is procedure place_data (operation : t_operations) is
begin begin
s_data_i_spi <= SR_m25p32_i when s_FMI.OP = WRSR if operation = WRSR then
else s_wr_data_i; s_data_i_spi <= SR_m25p32_i;
else
s_data_i_spi <= wr_data_i;
end if;
end procedure; end procedure;
begin begin
...@@ -274,20 +278,20 @@ begin ...@@ -274,20 +278,20 @@ begin
begin begin
case s_MEM_fsm is case s_MEM_fsm is
when R0_RESET => when R0_RESET =>
s_CTRL.OPA <= c_CTRL_default.OPA; s_FMI.OPA <= c_FMI_default.OPA;
s_CTRL.OPF <= c_CTRL_default.OPF; s_FMI.OPF <= c_FMI_default.OPF;
when S0_IDLE => when S0_IDLE =>
s_CTRL.OPA <= '0'; s_FMI.OPA <= '0';
s_CTRL.OPF <= '0'; s_FMI.OPF <= '0';
when Q0_END => when Q0_END =>
s_CTRL.OPA <= '1'; s_FMI.OPA <= '1';
s_CTRL.OPF <= '1'; s_FMI.OPF <= '1';
when Q1_ERROR => when Q1_ERROR =>
s_CTRL.OPA <= '1'; s_FMI.OPA <= '1';
s_CTRL.OPF <= '1'; s_FMI.OPF <= '1';
when others => when others =>
s_CTRL.OPA <= '1'; s_FMI.OPA <= '1';
s_CTRL.OPF <= '0'; s_FMI.OPF <= '0';
end case; end case;
end process p_comb_OP; end process p_comb_OP;
...@@ -319,9 +323,11 @@ begin ...@@ -319,9 +323,11 @@ begin
--! Easiest way to add concurrency while performing an SPI --! Easiest way to add concurrency while performing an SPI
--! operation. --! operation.
if s_FMI.OP /= WRSR then if s_FMI.OP /= WRSR then
s_data_i_spi <= s_data_i; s_data_i_spi <= wr_data_i;
else else
s_data_i_spi <= s_data_i; --! TODO: check if this is correctly positioned
s_data_i_spi(r_SR_m25p32'a_length - 1 downto 0)
<= SR_m25P32_i;
end if; end if;
when S1_WREN => when S1_WREN =>
if s_SPI2.SENT_OP = '1' then if s_SPI2.SENT_OP = '1' then
...@@ -340,9 +346,9 @@ begin ...@@ -340,9 +346,9 @@ begin
s_MEM_fsm <= Q0_END; s_MEM_fsm <= Q0_END;
end if; end if;
when Q0_END => when Q0_END =>
s_MEM_fsm <= s_R0_RESET; s_MEM_fsm <= R0_RESET;
when Q1_ERROR => when Q1_ERROR =>
s_MEM_fsm <= s_R0_RESET; s_MEM_fsm <= R0_RESET;
when others => when others =>
end case; end case;
end if; end if;
......
hdl/m25p32/rtl/m25p32_top.vhd
View file @ fa473234
...@@ -65,9 +65,10 @@ end m25p32_top; ...@@ -65,9 +65,10 @@ end m25p32_top;
architecture Behavioral of m25p32_top is architecture Behavioral of m25p32_top is
signal s_wr_data : STD_LOGIC_VECTOR (c_DATA_LENGTH*8 - 1 downto 0); signal s_wr_data : STD_LOGIC_VECTOR (c_DATA_LENGTH*8 - 1 downto 0);
signal s_rd_data : STD_LOGIC_VECTOR (c_DATA_LENGTH*8 - 1 downto 0); signal s_rd_data : STD_LOGIC_VECTOR (c_READ_LENGTH*8 - 1 downto 0);
signal s_SR_m25p32 : STD_LOGIC_VECTOR (r_SR_m25p32'a_length - 1 downto 0);
signal s_FMOH : STD_LOGIC_VECTOR ( r_FMOH'a_length - 1 downto 0); signal s_FMI : STD_LOGIC_VECTOR ( r_FMI'a_length - 1 downto 0);
component m25p32_core is component m25p32_core is
generic( generic(
...@@ -84,7 +85,11 @@ architecture Behavioral of m25p32_top is ...@@ -84,7 +85,11 @@ architecture Behavioral of m25p32_top is
sclk_o : out STD_LOGIC; sclk_o : out STD_LOGIC;
ss_n_o : out STD_LOGIC; ss_n_o : out STD_LOGIC;
FMOH_io : inout STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0) wr_data_i : in STD_LOGIC_VECTOR(g_PAGE_SIZE*8 - 1 downto 0);
rd_data_o : out STD_LOGIC_VECTOR(g_READ_LENGTH*8 - 1 downto 0);
SR_m25p32_i : in STD_LOGIC_VECTOR(r_SR_m25p32'a_length - 1 downto 0);
FMI_io : inout STD_LOGIC_VECTOR (r_FMI'a_length - 1 downto 0)
); );
end component; end component;
...@@ -110,10 +115,11 @@ architecture Behavioral of m25p32_top is ...@@ -110,10 +115,11 @@ architecture Behavioral of m25p32_top is
wb_rty_o : out STD_LOGIC; wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC; wb_err_o : out STD_LOGIC;
wr_data_o : out STD_LOGIC_VECTOR(c_DATA_LENGTH*8 - 1 downto 0); wr_data_o : out STD_LOGIC_VECTOR(g_DATA_LENGTH*8 - 1 downto 0);
rd_data_i : in STD_LOGIC_VECTOR(c_DATA_LENGTH*8 - 1 downto 0); rd_data_i : in STD_LOGIC_VECTOR(g_READ_LENGTH*8 - 1 downto 0);
SR_m25p32_o : out STD_LOGIC_VECTOR(r_SR_m25p32'a_length - 1 downto 0);
FMOH_io : inout STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0) FMI_io : inout STD_LOGIC_VECTOR (r_FMI'a_length - 1 downto 0)
); );
end component; end component;
...@@ -129,7 +135,11 @@ begin ...@@ -129,7 +135,11 @@ begin
sclk_o => prom_cclk_o, sclk_o => prom_cclk_o,
ss_n_o => prom_cs0_b_n_o, ss_n_o => prom_cs0_b_n_o,
FMOH_io => s_FMOH wr_data_i => s_wr_data,
rd_data_o => s_rd_data,
SR_m25p32_i => s_SR_m25p32,
FMI_io => s_FMI
); );
inst_m25p32_regs: m25p32_regs inst_m25p32_regs: m25p32_regs
...@@ -148,10 +158,11 @@ begin ...@@ -148,10 +158,11 @@ begin
wb_rty_o => wb_rty_o, wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o, wb_err_o => wb_err_o,
wr_data_o => s_wr_data_o, wr_data_o => s_wr_data,
rd_data_i => s_rd_data_i, rd_data_i => s_rd_data,
SR_m25p32_o => s_SR_m25p32,
FMOH_io => s_FMOH FMI_io => s_FMI
); );
end Behavioral; end Behavioral;
hdl/m25p32/test/m25p32_top_tb.vhd
View file @ fa473234
...@@ -22,8 +22,8 @@ library IEEE; ...@@ -22,8 +22,8 @@ library IEEE;
library work; library work;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; use IEEE.NUMERIC_STD.ALL;
use work.spi_master_pkg.ALL;
use work.m25p32_pkg.ALL; use work.m25p32_pkg.ALL;
use work.serializer_sim_pkg.ALL;
use work.spi_analyser_pkg.ALL; use work.spi_analyser_pkg.ALL;
entity m25p32_top_tb is entity m25p32_top_tb is
...@@ -32,7 +32,7 @@ entity m25p32_top_tb is ...@@ -32,7 +32,7 @@ entity m25p32_top_tb is
architecture Behavioral of m25p32_top_tb is architecture Behavioral of m25p32_top_tb is
signal wb_rst_i : STD_LOGIC; signal s_rst : STD_LOGIC;
signal wb_clk : STD_LOGIC; signal wb_clk : STD_LOGIC;
signal s_wb_we : STD_LOGIC; signal s_wb_we : STD_LOGIC;
......
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