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Conv TTL Blocking
Commit 08f7ee8b authored by gilsoriano's avatar gilsoriano
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Nighty night code debugging for simulation. Remains core and top to clean up.

parent 67acc6e6
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Showing with 134 additions and 113 deletions
hdl/m25p32/rtl/m25p32_pkg.vhd
View file @ 08f7ee8b
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hdl/m25p32/rtl/m25p32_regs.vhd
View file @ 08f7ee8b
......@@ -66,7 +66,7 @@ entity m25p32_regs is
wr_data_o : out STD_LOGIC_VECTOR(g_DATA_LENGTH*8 - 1 downto 0);
rd_data_i : in STD_LOGIC_VECTOR(g_READ_LENGTH*8 - 1 downto 0);
SR_m25p32_o : out STD_LOGIC_VECTOR(r_SR_m25p32'length - 1 downto 0);
SR_m25p32_o : out STD_LOGIC_VECTOR(r_SR_m25p32'a_length - 1 downto 0);
FMI_io : inout STD_LOGIC_VECTOR (r_FMI'a_length - 1 downto 0)
);
......@@ -77,9 +77,6 @@ architecture Behavioral of m25p32_regs is
signal s_FMI : r_FMI;
signal s_SR_m25p32 : r_SR_m25p32;
signal wr_data_o : STD_LOGIC_VECTOR(g_DATA_LENGTH*8 - 1 downto 0);
signal rd_data_i : STD_LOGIC_VECTOR(g_READ_LENGTH*8 - 1 downto 0);
signal s_wr_page : r_page;
signal s_rd_word : r_word;
......@@ -93,12 +90,13 @@ begin
wb_rty_o <= s_wb_rty_o;
wb_err_o <= s_wb_err_o;
wr_data_o <= f_STD_LOGIC_VECTOR(wr_page);
wr_data_o <= f_STD_LOGIC_VECTOR(s_wr_page);
FMI_o <= f_STD_LOGIC_VECTOR(s_FMI);
FMI_io <= f_STD_LOGIC_VECTOR(s_FMI);
p_wbslave: process (wb_clk)
variable v_FMI : r_FMI;
variable v_pos : NATURAL;
begin
if rising_edge(wb_clk) then
if wb_rst_i = '1' then
......@@ -109,8 +107,6 @@ begin
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
s_addr_i <= (others => '0');
s_data_i <= (others => '0');
else
--! We never retry
s_wb_rty_o <= '0';
......@@ -128,7 +124,7 @@ begin
case wb_addr_i(1 downto 0) is
--! FMI address
when "00" =>
if s_FMI.OPP = '0' then
if s_FMI.OPA = '0' then
v_FMI := f_FMI(wb_data_i(23 downto 0));
s_FMI <= v_FMI;
else
......@@ -146,9 +142,9 @@ begin
end case;
--! WRITE_DATA address pool
when others =>
wr_page.word(to_integer(wb_addr_i(g_WB_ADDR_LENGTH
- 1 downto 0))) <=
f_word(wb_data_i);
v_pos := to_integer(UNSIGNED(wb_addr_i(g_WB_ADDR_LENGTH
- 1 downto 0)));
s_wr_page(v_pos).word_slv <= wb_data_i;
end case;
else
case wb_addr_i(g_WB_ADDR_LENGTH) is
......@@ -160,7 +156,7 @@ begin
<= (others => '0');
when "01" =>
wb_data_o(r_SR_m25p32'a_length - 1 downto 0)
<= s_SR_m25p32;
<= f_STD_LOGIC_VECTOR(s_SR_m25p32);
wb_data_o(31 downto r_SR_m25p32'a_length)
<= (others => '0');
when "10" =>
......@@ -170,9 +166,11 @@ begin
s_wb_err_o <= '1';
end case;
when others =>
wb_data_o <= f_word(s_wr_page,
to_integer(wb_addr_i(g_WB_ADDR_LENGTH - 1 downto 0);
end case
wb_data_o <= f_STD_LOGIC_VECTOR(
s_wr_page(to_integer(
UNSIGNED(wb_addr_i(g_WB_ADDR_LENGTH - 1 downto
0)))));
end case;
end if;
end if;
end if;
......
hdl/m25p32/rtl/m25p32_top.vhd
View file @ 08f7ee8b
......@@ -148,10 +148,10 @@ begin
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
wr_data_o => s_wr_data_o;
rd_data_i => s_rd_data_i;
wr_data_o => s_wr_data_o,
rd_data_i => s_rd_data_i,
FMOH_io => s_FMOH
FMOH_io => s_FMOH
);
end Behavioral;
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