[Jitter] Analog deglitching
While designing V1, the big picture of the repetitor was not perfectly clear. Due to this, we didn't pay attention to produce a low jitter repetition as we were relying completely in the FPGA for this task. A better approach can be used if the deglitching of the pulse is carried out before the signal goes into the FPGA.
How repetition was thought at the beginning
The schema for repetition consisted in registering the asynchronous signal and detect the edge of the synchronized input pulse. Thinking of jitter in terms of the deviation of the skew between the input signal and the FPGA-clock synchronous output signal, it is evident that the jitter will have, at least, two easy trackable components:
JITTER = SAMPLING (uniform along a clock cycle) + random noise (Gaussian)
The first one of these components can be reduced by reducing the clock period.
However, an analog approach can be very interesting to reduce the jitter of the output rise edge. If we use an analog deglitch stage, the beginning of the "clean" signal can be directly bypassed through the FPGA, which, later on, a synchronous process will take control of the repetition and will crop the output pulse when appropriate. Due to this, the jitter of the rise will be low, and the jitter of the fall edge will still have sampling jitter.
More sophisticated techniques should be carried out to reduce the jitter of the fall edge, which are not covered in this feature candidate.
Analog deglitch vs digital deglitch
Let's consider first the digital case. Assuming that the FPGA is working at 125MHz, the sampling jitter will have an uniform distribution of 8 ns, which will be pretty much excessive. The digital deglitch is configured to be two consecutive clocks, which means being stable for 16 ns (well, indeed is the probability to see over the threshold voltages during two consecutive setup times, that giving the input signals, thresholds and parasitic RC is more or less equivalent). To perform a similar deglitching stage, we must guarantee that the analog deglitch will limit short pulses to the FPGA to, at least, 16ns.
The analog picture is easy to follow.
Analog deglitch design
As said before, we must relate the low pass filter with the logic that
goes into the FPGA. Schmitt triggers play a crucial role into correct
the deglitching.
Schmitt triggers have two thresholds, called Vt- and Vt*. The hysteresis
represents the difference between them: Vh=Vt* - Vt-
Vt+ makes the output of the Schmitt trigger go high.
Vt- makes the output of the Schmitt trigger go low.
So putting together a RC low pass filter with a Schmitt trigger yield to a rock-solid deglitching stage.
The required analog deglitch should be, at least, equally deglitch
capable to the digital alternative and being able to be stable until an
edge is detected in the synchronous process of the FPGA. That means that
the low pass filter should be able to let the capacitance discharge from
Vt*,min to its Vt- of the Schmitt trigger. In the case of sn74lvc14a
powered at 3V3 Vt*,min is 1V and Vt- is 0,7V.
0,7 < 1*exp(-t/RC) where t=N*t_clk
and N is max(deglitching stage clocks, metastability+edge detection
clocks). In our case N=max(2 clocks, 3 clocks) = 3 clocks.
Working at 125MHz (which can be taken directly from the external LVDS clocking source with no need of internall PLL) yields that a good value for the front and back capacitance is 100pF. Simulations show that the calculations are correct.
Rear Block
In this case the RC filter is a band-pass filter. The resistive divisor permits an efficient divider to reduce in more than one fifth the voltage from the LEMO connector to input of the Schmitt trigger.
The schematic of the RC filter prior to the Schmitt inverter is shown below:
https://www.ohwr.org/project/conv-ttl-blo/repository/entry/doc/OHWR/issues/issue_621/rearSchmitt.jpg
Rhigh = 4K7
Rlow = 1K
Gain in band-pass 0,175
Then, a DC rejection filter (differentiator or high-pass) has a knee frequency of 3KHz thanks to the 9n4 capacitor.
The low pass filter is naturally done by the input pins of every IC. Typically this parasitic value is 4-5pF. So, to maximize the low pass effect, we add and extra capacitor of 100pF to the input of the circuit. The knee frequency is then 2MHz, enough for our needs.
A capture of the simulation in the worst-case scenario depicted before is attached:
https://www.ohwr.org/project/conv-ttl-blo/repository/entry/doc/OHWR/issues/issue_621/rearGlitch.jpg
Front Block
The TTL inputs are not expected to have DC component, so no need of serial capacitor.
The low pass is gain 1, as the TTL input level needs no attenuation. The knee frequency is 1,6MHz. A little bit low, but fine in any case.
The schematics:
The capture of the simulation in a similar worst-case scenario:
https://www.ohwr.org/project/conv-ttl-blo/repository/entry/doc/OHWR/issues/issue_621/frontGlitch.jpg