Commit 669b9ba3 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Compiled gateware for release version

parent 3395277e
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<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
</file>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
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<bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
</project>
......@@ -163,7 +163,7 @@ architecture arch of conv_ttl_rs485 is
constant c_board_id : std_logic_vector(31 downto 0) := x"54343835";
-- Gateware version
constant c_gwvers : std_logic_vector(7 downto 0) := x"00";
constant c_gwvers : std_logic_vector(7 downto 0) := x"10";
--============================================================================
-- Type declarations
......@@ -331,11 +331,11 @@ begin
g_gwvers => c_gwvers,
g_pgen_fixed_width => false,
g_pgen_gf_len => 1,
--g_with_pulse_cnt => true,
--g_with_pulse_timetag => true,
--g_with_man_trig => true,
--g_man_trig_pwidth => 24,
--g_with_thermometer => true,
g_with_pulse_cnt => true,
g_with_pulse_timetag => true,
g_with_man_trig => true,
g_man_trig_pwidth => 24,
g_with_thermometer => true,
g_bicolor_led_columns => c_bicolor_led_cols,
g_bicolor_led_lines => c_bicolor_led_lines
)
......
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