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Conv TTL RS485 - Gateware
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Conv TTL RS485 - Gateware
Commits
669b9ba3
Commit
669b9ba3
authored
Dec 18, 2014
by
Theodor-Adrian Stana
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Compiled gateware for release version
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conv_ttl_rs485.xise
syn/Release/conv_ttl_rs485.xise
+717
-706
conv_ttl_rs485.vhd
top/conv_ttl_rs485.vhd
+6
-6
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syn/Release/conv_ttl_rs485.xise
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669b9ba3
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"../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"119"
/>
</file>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"120"
/>
</file>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"121"
/>
</file>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"122"
/>
</file>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"123"
/>
</file>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"124"
/>
</file>
</files>
</file>
</files>
<bindings/>
<version
xil_pn:ise_version=
"14.2"
xil_pn:schema_version=
"2"
/>
</project>
top/conv_ttl_rs485.vhd
View file @
669b9ba3
...
...
@@ -163,7 +163,7 @@ architecture arch of conv_ttl_rs485 is
constant
c_board_id
:
std_logic_vector
(
31
downto
0
)
:
=
x"54343835"
;
-- Gateware version
constant
c_gwvers
:
std_logic_vector
(
7
downto
0
)
:
=
x"
0
0"
;
constant
c_gwvers
:
std_logic_vector
(
7
downto
0
)
:
=
x"
1
0"
;
--============================================================================
-- Type declarations
...
...
@@ -331,11 +331,11 @@ begin
g_gwvers
=>
c_gwvers
,
g_pgen_fixed_width
=>
false
,
g_pgen_gf_len
=>
1
,
--
g_with_pulse_cnt => true,
--
g_with_pulse_timetag => true,
--
g_with_man_trig => true,
--
g_man_trig_pwidth => 24,
--
g_with_thermometer => true,
g_with_pulse_cnt
=>
true
,
g_with_pulse_timetag
=>
true
,
g_with_man_trig
=>
true
,
g_man_trig_pwidth
=>
24
,
g_with_thermometer
=>
true
,
g_bicolor_led_columns
=>
c_bicolor_led_cols
,
g_bicolor_led_lines
=>
c_bicolor_led_lines
)
...
...
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