hdl-fm: Changed interface of pulse_gen_gp

The freq_i input is now appropriately named per_i (for period), which is what this input actually is.

hdl-fm: Changed interface of pulse_gen_gp
The freq_i input is now appropriately named per_i (for period), which is what this input actually is.
07338e2f · Theodor-Adrian Stana · a10a8e63 · 07338e2f · 07338e2f
Commit 07338e2f authored Dec 05, 2014 by Theodor-Adrian Stana
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Showing with 18 additions and 15 deletions

pulse_gen_gp.vhd hdl/modules/pulse_gen_gp.vhd +15 -12

pts.vhd hdl/top/pts.vhd +3 -3

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--- a/hdl/modules/pulse_gen_gp.vhd
+++ b/hdl/modules/pulse_gen_gp.vhd
@@ -11,23 +11,23 @@
 --
 -- description:
 --
--   This module generates pulses with configurable frequency, width and delay.
+--   This module generates pulses with configurable period, width and delay.
 --
 --   In order to generate pulses, the module must be enabled via the en_i port.
--   Once en_i is high, pulses are generated at the frequency specified via
+--   Once en_i is high, pulses are generated at the period specified via
--   freq_i, with the width specified via pwidth_i.
+--   per_i, with the width specified via pwidth_i.
 --
 --   An optional delay can be added before the start of the pulse, via the delay_i
 --   port.
 --
 --   Note that this delay can be set only before the module is enabled.
 --
--   freq_i, pwidth_i and delay_i are given in clk_i cycles.
+--   per_i, pwidth_i and delay_i are given in clk_i cycles.
 --
 -- dependencies:
 --
 -- references:
-- 
+--
 --==============================================================================
 -- GNU LESSER GENERAL PUBLIC LICENSE
 --==============================================================================
@@ -46,8 +46,11 @@
 --    2013 08-15   Theodor Stana     t.stana@cern.ch     v2.0, delay, pwidth, freq
 --                                                       now controllable via
 --                                                       inputs (regs, etc.)
+--    2014-12-05   Theodor Stana     t.stana@cern.ch     v3.0, renamed freq_i to
+--                                                       per_i, functionality
+--                                                       still the same
 --==============================================================================
-- TODO: - 
+-- TODO: -
 --==============================================================================
 library ieee;
@@ -64,11 +67,11 @@ entity pulse_gen_gp is
    -- Active high enable signal
    en_i     : in  std_logic;
-    -- Delay, pulse width and frequency inputs, in number of clk_i cycles
+    -- Delay, pulse width and period inputs, in number of clk_i cycles
    delay_i  : in  std_logic_vector(31 downto 0);
    pwidth_i : in  std_logic_vector(31 downto 0);
-    freq_i   : in  std_logic_vector(31 downto 0);
+    per_i    : in  std_logic_vector(31 downto 0);
    -- Output pulse signal
    pulse_o  : out std_logic
@@ -96,7 +99,7 @@ architecture behav of pulse_gen_gp is
  --============================================================================
  signal delay_int  : unsigned(31 downto 0);
  signal pwidth_int : unsigned(31 downto 0);
-  signal freq_int   : unsigned(31 downto 0);
+  signal per_int    : unsigned(31 downto 0);
  signal pulse_cnt  : unsigned(31 downto 0);
  signal delay_cnt  : unsigned(31 downto 0);
@@ -113,7 +116,7 @@ begin
  --============================================================================
  delay_int  <= unsigned(delay_i);
  pwidth_int <= unsigned(pwidth_i);
-  freq_int   <= unsigned(freq_i);
+  per_int    <= unsigned(per_i);
  --============================================================================
  -- Delay logic
@@ -152,7 +155,7 @@ begin
        pulse_o   <= '0';
        if (pulse_cnt < pwidth_int) then
          pulse_o <= '1';
-        elsif (pulse_cnt = freq_int-1) then
+        elsif (pulse_cnt = per_int-1) then
          pulse_cnt <= (others => '0');
        end if;
      end if;

--- a/hdl/top/pts.vhd
+++ b/hdl/top/pts.vhd
@@ -350,7 +350,7 @@ architecture arch of pts is
      -- Delay, pulse width and frequency inputs, in number of clk_i cycles
      delay_i  : in  std_logic_vector(31 downto 0);
      pwidth_i : in  std_logic_vector(31 downto 0);
-      freq_i   : in  std_logic_vector(31 downto 0);
+      per_i    : in  std_logic_vector(31 downto 0);
      -- Output pulse signal
      pulse_o  : out std_logic
@@ -1508,7 +1508,7 @@ begin
      -- Delay, pulse width and frequency inputs, in number of clk_i cycles
      delay_i  => x"00000000",
      pwidth_i => x"00000014",
-      freq_i   => x"00989680",
+      per_i    => x"00989680",
      -- Output pulse signal
      pulse_o  => front_pulses(0)
@@ -1675,7 +1675,7 @@ gen_rear_test_logic : for i in 0 to 5 generate
      -- Delay, pulse width and frequency inputs, in number of clk_i cycles
      delay_i  => x"00000050",
      pwidth_i => x"00000014",
-      freq_i   => x"00989680",
+      per_i    => x"00989680",
      -- Output pulse signal
      pulse_o  => rear_pulses(i)