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Conv TTL RS485
Commit 06886f17 authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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Added V1 ucf

parent 06e0ab1c
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hdl/IMAGES/image1/constraints/V1/BloV2.ucf2 0 → 100644
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##---------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##----------------------------------------
NET "RST_N" LOC = N20;
NET "RST_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_SYSRESET_N" LOC = L20;
NET "FPGA_SYSRESET_N" IOSTANDARD = "LVCMOS33";
NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = "LVCMOS33";
NET "CLK20_VCXO" LOC = E16;
NET "CLK20_VCXO" IOSTANDARD = "LVCMOS33";
NET "CLK20_VCXO" TNM_NET = "CLK20_VCXO";
TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50%;
NET "FPGA_CLK_N" LOC = H12;
NET "FPGA_CLK_N" IOSTANDARD = "LVDS_25";
NET "FPGA_CLK_P" LOC = G11;
NET "FPGA_CLK_P" IOSTANDARD = "LVDS_25";
TIMESPEC TS_clk_i = PERIOD "FPGA_CLK_N" 125 MHz HIGH 50%;
TIMESPEC TS_clk_i = PERIOD "FPGA_CLK_P" 125 MHz HIGH 50%;
##======================================
##-- FRONT PANEL TTLS
##======================================
##-- LEDs
##--
##-- + UBT: LVTTL input
##-------------------
NET "LED_CTRL0" LOC = M18;
NET "LED_CTRL0" IOSTANDARD = "LVTTL";
NET "LED_CTRL0" DRIVE = "4";
NET "LED_CTRL0" SLEW = "QUIETIO";
NET "LED_CTRL0_OEN" LOC = T20;
NET "LED_CTRL0_OEN" IOSTANDARD = "LVTTL";
NET "LED_CTRL0_OEN" DRIVE = "4";
NET "LED_CTRL0_OEN" SLEW = "QUIETIO";
NET "LED_CTRL1" LOC = M17;
NET "LED_CTRL1" IOSTANDARD = "LVTTL";
NET "LED_CTRL1" DRIVE = "4";
NET "LED_CTRL1" SLEW = "QUIETIO";
NET "LED_CTRL1_OEN" LOC = U19;
NET "LED_CTRL1_OEN" IOSTANDARD = "LVTTL";
NET "LED_CTRL1_OEN" DRIVE = "4";
NET "LED_CTRL1_OEN" SLEW = "QUIETIO";
NET "LED_MULTICAST_2_0" LOC = P16;
NET "LED_MULTICAST_2_0" IOSTANDARD = "LVTTL";
NET "LED_MULTICAST_2_0" DRIVE = "4";
NET "LED_MULTICAST_2_0" SLEW = "QUIETIO";
NET "LED_MULTICAST_3_1" LOC = P17;
NET "LED_MULTICAST_3_1" IOSTANDARD = "LVTTL";
NET "LED_MULTICAST_3_1" DRIVE = "4";
NET "LED_MULTICAST_3_1" SLEW = "QUIETIO";
NET "LED_WR_GMT_TTL_TTLN" LOC = N16;
NET "LED_WR_GMT_TTL_TTLN" IOSTANDARD = "LVTTL";
NET "LED_WR_GMT_TTL_TTLN" DRIVE = "4";
NET "LED_WR_GMT_TTL_TTLN" SLEW = "QUIETIO";
NET "LED_WR_LINK_SYSERROR" LOC = R15;
NET "LED_WR_LINK_SYSERROR" IOSTANDARD = "LVTTL";
NET "LED_WR_LINK_SYSERROR" DRIVE = "4";
NET "LED_WR_LINK_SYSERROR" SLEW = "QUIETIO";
NET "LED_WR_OK_SYSPW" LOC = R16;
NET "LED_WR_OK_SYSPW" IOSTANDARD = "LVTTL";
NET "LED_WR_OK_SYSPW" DRIVE = "4";
NET "LED_WR_OK_SYSPW" SLEW = "QUIETIO";
NET "LED_WR_OWNADDR_I2C" LOC = N15;
NET "LED_WR_OWNADDR_I2C" IOSTANDARD = "LVTTL";
NET "LED_WR_OWNADDR_I2C" DRIVE = "4";
NET "LED_WR_OWNADDR_I2C" SLEW = "QUIETIO";
##-------------------
##-- Front channel LEDs
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "PULSE_FRONT_LED1_N" LOC = H5;
NET "PULSE_FRONT_LED1_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED1_N" DRIVE = "4";
NET "PULSE_FRONT_LED1_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED2_N" LOC = J6;
NET "PULSE_FRONT_LED2_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED2_N" DRIVE = "4";
NET "PULSE_FRONT_LED2_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED3_N" LOC = K6;
NET "PULSE_FRONT_LED3_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED3_N" DRIVE = "4";
NET "PULSE_FRONT_LED3_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED4_N" LOC = K5;
NET "PULSE_FRONT_LED4_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED4_N" DRIVE = "4";
NET "PULSE_FRONT_LED4_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED5_N" LOC = M7;
NET "PULSE_FRONT_LED5_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED5_N" DRIVE = "4";
NET "PULSE_FRONT_LED5_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED6_N" LOC = M6;
NET "PULSE_FRONT_LED6_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED6_N" DRIVE = "4";
NET "PULSE_FRONT_LED6_N" SLEW = "QUIETIO";
##-------------------
##-- Rear LEDs
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "PULSE_REAR_LED1_N" LOC = AB17;
NET "PULSE_REAR_LED1_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED1_N" DRIVE = "4";
NET "PULSE_REAR_LED1_N" SLEW = "QUIETIO";
NET "PULSE_REAR_LED2_N" LOC = AB19;
NET "PULSE_REAR_LED2_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED2_N" DRIVE = "4";
NET "PULSE_REAR_LED2_N" SLEW = "QUIETIO";
NET "PULSE_REAR_LED3_N" LOC = AA16;
NET "PULSE_REAR_LED3_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED3_N" DRIVE = "4";
NET "PULSE_REAR_LED3_N" SLEW = "QUIETIO";
NET "PULSE_REAR_LED4_N" LOC = AA18;
NET "PULSE_REAR_LED4_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED4_N" DRIVE = "4";
NET "PULSE_REAR_LED4_N" SLEW = "QUIETIO";
NET "PULSE_REAR_LED5_N" LOC = AB16;
NET "PULSE_REAR_LED5_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED5_N" DRIVE = "4";
NET "PULSE_REAR_LED5_N" SLEW = "QUIETIO";
NET "PULSE_REAR_LED6_N" LOC = AB18;
NET "PULSE_REAR_LED6_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED6_N" DRIVE = "4";
NET "PULSE_REAR_LED6_N" SLEW = "QUIETIO";
##-------------------
##-- TTL trigger inputs
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "FPGA_INPUT_TTL1_N" LOC = T2;
NET "FPGA_INPUT_TTL1_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL2_N" LOC = U3;
NET "FPGA_INPUT_TTL2_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL3_N" LOC = V5;
NET "FPGA_INPUT_TTL3_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL4_N" LOC = W4;
NET "FPGA_INPUT_TTL4_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL5_N" LOC = T6;
NET "FPGA_INPUT_TTL5_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL6_N" LOC = T3;
NET "FPGA_INPUT_TTL6_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL1" LOC = C1;
NET "FPGA_OUT_TTL1" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL2" LOC = F2;
NET "FPGA_OUT_TTL2" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL3" LOC = F5;
NET "FPGA_OUT_TTL3" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL4" LOC = H4;
NET "FPGA_OUT_TTL4" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL5" LOC = J4;
NET "FPGA_OUT_TTL5" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL6" LOC = H2;
NET "FPGA_OUT_TTL6" IOSTANDARD = "LVCMOS33";
##-------------------
##-- Bottomly allocated GPIOs
##--
##-- + IN ACT family: CMOS/TTL 3.3V inputs
##-- + OUT BCT family (BiCMOS): TTL inputs
##
##-- Schematics name: INV_IN_*
##---- renamed to INV_IN[*]
##-------------------
NET "INV_IN_1_N" LOC = V2;
NET "INV_IN_1_N" IOSTANDARD = "LVCMOS33";
NET "INV_IN_2_N" LOC = W3;
NET "INV_IN_2_N" IOSTANDARD = "LVCMOS33";
NET "INV_IN_3_N" LOC = Y2;
NET "INV_IN_3_N" IOSTANDARD = "LVCMOS33";
NET "INV_IN_4_N" LOC = AA2;
NET "INV_IN_4_N" IOSTANDARD = "LVCMOS33";
NET "INV_OUT_1" LOC = J3;
NET "INV_OUT_1" IOSTANDARD = "LVCMOS33";
NET "INV_OUT_2" LOC = L3;
NET "INV_OUT_2" IOSTANDARD = "LVCMOS33";
NET "INV_OUT_3" LOC = M3;
NET "INV_OUT_3" IOSTANDARD = "LVCMOS33";
NET "INV_OUT_4" LOC = P2;
NET "INV_OUT_4" IOSTANDARD = "LVCMOS33";
##======================================
##-- RTM signals
##======================================
##-- Blocking input to FPGA
##
##-- Schematics name: FPGA_BLO_IN_*
##---- renamed to FPGA_BLO_IN[*]
##-------------------
NET "FPGA_BLO_IN_1" LOC = Y9;
NET "FPGA_BLO_IN_1" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_2" LOC = AA10;
NET "FPGA_BLO_IN_2" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_3" LOC = W12;
NET "FPGA_BLO_IN_3" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_4" LOC = AA6;
NET "FPGA_BLO_IN_4" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_5" LOC = Y7;
NET "FPGA_BLO_IN_5" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_6" LOC = AA8;
NET "FPGA_BLO_IN_6" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO1" LOC = W9;
NET "FPGA_TRIG_BLO1" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO2" LOC = T10;
NET "FPGA_TRIG_BLO2" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO3" LOC = V7;
NET "FPGA_TRIG_BLO3" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO4" LOC = U9;
NET "FPGA_TRIG_BLO4" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO5" LOC = T8;
NET "FPGA_TRIG_BLO5" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO6" LOC = R9;
NET "FPGA_TRIG_BLO6" IOSTANDARD = "LVCMOS33";
##======================================
##-- VME CONNECTOR SIGNALS
##======================================
##-- I2C lines
##--
##-- + UBT: LVTTL input
##-------------------
NET "SCL_I" LOC = F19;
NET "SCL_I" IOSTANDARD = "LVTTL";
NET "SCL_O" LOC = E20;
NET "SCL_O" IOSTANDARD = "LVTTL";
NET "SCL_O" DRIVE = "4";
NET "SCL_OE" LOC = H18;
NET "SCL_OE" IOSTANDARD = "LVTTL";
NET "SCL_OE" DRIVE = "4";
NET "SCL_OE" PULLDOWN;
NET "SDA_I" LOC = G20;
NET "SDA_I" IOSTANDARD = "LVTTL";
NET "SDA_O" LOC = F20;
NET "SDA_O" IOSTANDARD = "LVTTL";
NET "SDA_O" SLEW = "FAST";
NET "SDA_O" DRIVE = "4";
NET "SDA_O" PULLUP;
NET "SDA_OE" LOC = J19;
NET "SDA_OE" IOSTANDARD = "LVTTL";
NET "SDA_OE" SLEW = "FAST";
NET "SDA_OE" DRIVE = "4";
NET "SDA_OE" PULLDOWN;
##-------------------
##-- Geographical Address
##--
##-- + UBT: LVTTL input
##-------------------
NET "FPGA_GA0" LOC = H20;
NET "FPGA_GA0" IOSTANDARD = "LVTTL";
NET "FPGA_GA1" LOC = J20;
NET "FPGA_GA1" IOSTANDARD = "LVTTL";
NET "FPGA_GA2" LOC = K19;
NET "FPGA_GA2" IOSTANDARD = "LVTTL";
NET "FPGA_GA3" LOC = K20;
NET "FPGA_GA3" IOSTANDARD = "LVTTL";
NET "FPGA_GA4" LOC = L19;
NET "FPGA_GA4" IOSTANDARD = "LVTTL";
NET "FPGA_GAP" LOC = H19;
NET "FPGA_GAP" IOSTANDARD = "LVTTL";
##-------------------
##-- ROM memory
##-------------------
NET "FPGA_PROM_CCLK" LOC = Y20;
NET "FPGA_PROM_CCLK" IOSTANDARD = "LVTTL";
NET "FPGA_PROM_CSO_B_N" LOC = AA3;
NET "FPGA_PROM_CSO_B_N" IOSTANDARD = "LVTTL";
NET "FPGA_PROM_DIN" LOC = AA20;
NET "FPGA_PROM_DIN" IOSTANDARD = "LVTTL";
NET "FPGA_PROM_MOSI" LOC = AB20;
NET "FPGA_PROM_MOSI" IOSTANDARD = "LVTTL";
##======================================
##-- WHITE RABBIT
##======================================
##-------------------
##-- Thermo for UID
##-------------------
NET "THERMOMETER" LOC = B1;
NET "THERMOMETER" IOSTANDARD = "LVCMOS25";
##-------------------
##-- DACs control
##--
##-- + CMOS 3.3V input
##-------------------
NET "FPGA_PLLDAC1_DIN" LOC = AB14;
NET "FPGA_PLLDAC1_DIN" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC1_SCLK" LOC = AA14;
NET "FPGA_PLLDAC1_SCLK" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC1_SYNC_N" LOC = AB15;
NET "FPGA_PLLDAC1_SYNC_N" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC2_DIN" LOC = W14;
NET "FPGA_PLLDAC2_DIN" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC2_SCLK" LOC = Y14;
NET "FPGA_PLLDAC2_SCLK" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC2_SYNC_N" LOC = W13;
NET "FPGA_PLLDAC2_SYNC_N" IOSTANDARD = "LVCMOS25";
##-------------------
##-- SFP connection
##-------------------
NET "FPGA_SFP_LOS" LOC = G3;
NET "FPGA_SFP_LOS" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_MOD_DEF0" LOC = K8;
NET "FPGA_SFP_MOD_DEF0" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_RATE_SELECT" LOC = C4;
NET "FPGA_SFP_RATE_SELECT" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_MOD_DEF1" LOC = G4;
NET "FPGA_SFP_MOD_DEF1" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_MOD_DEF2" LOC = F3;
NET "FPGA_SFP_MOD_DEF2" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_TX_DISABLE" LOC = E4;
NET "FPGA_SFP_TX_DISABLE" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_TX_FAULT" LOC = D2;
NET "FPGA_SFP_TX_FAULT" IOSTANDARD = "LVCMOS33";
##-------------------
##-- FPGA MGT lines
##-------------------
NET "FPGAMGTCLK0_P" LOC = A10;
NET "FPGAMGTCLK0_P" IOSTANDARD = "LVDS_12";
NET "FPGAMGTCLK0_N" LOC = B10;
NET "FPGAMGTCLK0_N" IOSTANDARD = "LVDS_12";
NET "MGTSFPRX0_P" LOC = D7;
NET "MGTSFPRX0_P" IOSTANDARD = "LVDS_12";
NET "MGTSFPRX0_N" LOC = C7;
NET "MGTSFPRX0_N" IOSTANDARD = "LVDS_12";
NET "MGTSFPTX0_P" LOC = B6;
NET "MGTSFPTX0_P" IOSTANDARD = "LVDS_12";
NET "MGTSFPTX0_N" LOC = A6;
NET "MGTSFPTX0_N" IOSTANDARD = "LVDS_12";
##======================================
##-- ADDITIONAL PINS
##======================================
##--
##-- + HC CMOS 3.3V input
##-------------------
NET "FPGA_OE" LOC = R3;
NET "FPGA_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_OE" DRIVE = "4";
NET "FPGA_OE" SLEW = "QUIETIO";
NET "FPGA_BLO_OE" LOC = P5;
NET "FPGA_BLO_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_OE" DRIVE = "4";
NET "FPGA_BLO_OE" SLEW = "QUIETIO";
NET "FPGA_TRIG_TTL_OE" LOC = N3;
NET "FPGA_TRIG_TTL_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_TTL_OE" DRIVE = "4";
NET "FPGA_TRIG_TTL_OE" SLEW = "QUIETIO";
NET "FPGA_INV_OE" LOC = P6;
NET "FPGA_INV_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_INV_OE" DRIVE = "4";
NET "FPGA_INV_OE" SLEW = "QUIETIO";
##-------------------
##-- Configuration Switches
##
##-- Schematics name EXTRA_SWITCH_*
##---- renamed to EXTRA_SWITCH[*]
##-------------------
NET "EXTRA_SWITCH_1" LOC = F22;
NET "EXTRA_SWITCH_1" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_2" LOC = G22;
NET "EXTRA_SWITCH_2" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_3" LOC = H21;
NET "EXTRA_SWITCH_3" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_4" LOC = H22;
NET "EXTRA_SWITCH_4" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_5" LOC = J22;
NET "EXTRA_SWITCH_5" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_6" LOC = K21;
NET "EXTRA_SWITCH_6" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_7" LOC = K22;
NET "EXTRA_SWITCH_7" IOSTANDARD = "LVCMOS33";
NET "TTL/INV_TTL_N" LOC = L22;
NET "TTL/INV_TTL_N" IOSTANDARD = "LVCMOS33";
##-------------------
##-- Motherboard and piggyback IDs
##--
##-- + ACT: CMOS 3.3V input
##-------------------
NET "FPGA_RTMM0_N" LOC = V21;
NET "FPGA_RTMM0_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM1_N" LOC = V22;
NET "FPGA_RTMM1_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM2_N" LOC = U22;
NET "FPGA_RTMM2_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP0_N" LOC = W22;
NET "FPGA_RTMP0_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP1_N" LOC = Y22;
NET "FPGA_RTMP1_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP2_N" LOC = Y21;
NET "FPGA_RTMP2_N" IOSTANDARD = "LVCMOS33";
##-------------------
##-- General purpose
##--
##-- + ACT: CMOS 3.3V input
##-------------------
NET "FPGA_HEADER_OUT_N1" LOC = F15;
NET "FPGA_HEADER_OUT_N1" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N2" LOC = F16;
NET "FPGA_HEADER_OUT_N2" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N3" LOC = F17;
NET "FPGA_HEADER_OUT_N3" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N4" LOC = F14;
NET "FPGA_HEADER_OUT_N4" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N5" LOC = H14;
NET "FPGA_HEADER_OUT_N5" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N6" LOC = H13;
NET "FPGA_HEADER_OUT_N6" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N1" LOC = A17;
NET "FPGA_HEADER_IN_N1" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N2" LOC = A18;
NET "FPGA_HEADER_IN_N2" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N3" LOC = B18;
NET "FPGA_HEADER_IN_N3" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N4" LOC = A19;
NET "FPGA_HEADER_IN_N4" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N5" LOC = A20;
NET "FPGA_HEADER_IN_N5" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N6" LOC = B20;
NET "FPGA_HEADER_IN_N6" IOSTANDARD = "LVCMOS33";
hdl/IMAGES/image1/constraints/V1/FPGAbank.NET 0 → 100644
View file @ 06886f17
CLK20_VCXO IC15-E16
EXTRA_SWITCH_1 IC15-F22
EXTRA_SWITCH_2 IC15-G22
EXTRA_SWITCH_3 IC15-H21
EXTRA_SWITCH_4 IC15-H22
EXTRA_SWITCH_5 IC15-J22
EXTRA_SWITCH_6 IC15-K21
EXTRA_SWITCH_7 IC15-K22
FPGA_CLK_N IC15-G11
FPGA_CLK_P IC15-H12
FPGA_GA0 IC15-H20
FPGA_GA1 IC15-J20
FPGA_GA2 IC15-K19
FPGA_GA3 IC15-K20
FPGA_GA4 IC15-L19
FPGA_GAP IC15-H19
FPGA_INPUT_TTL1_N IC15-T3
FPGA_INPUT_TTL2_N IC15-U4
FPGA_INPUT_TTL3_N IC15-W3
FPGA_INPUT_TTL4_N IC15-W4
FPGA_INPUT_TTL5_N IC15-V3
FPGA_INPUT_TTL6_N IC15-U3
FPGA_INV_OE IC15-N4
FPGA_OE IC15-N3
FPGA_OUT_TTL1 IC15-D1
FPGA_OUT_TTL2 IC15-E1
FPGA_OUT_TTL3 IC15-F2
FPGA_OUT_TTL4 IC15-F1
FPGA_OUT_TTL5 IC15-G1
FPGA_OUT_TTL6 IC15-H2
FPGA_PLLDAC1_DIN IC15-Y14
FPGA_PLLDAC1_SCLK IC15-AA14
FPGA_PLLDAC1_SYNC_N IC15-AB15
FPGA_PLLDAC2_DIN IC15-AB13
FPGA_PLLDAC2_SCLK IC15-Y13
FPGA_PLLDAC2_SYNC_N IC15-AB14
FPGA_PROM_CCLK IC15-Y20
FPGA_PROM_CSO_B_N IC15-AA3
FPGA_PROM_DIN IC15-AA20
FPGA_PROM_MOSI IC15-AB20
FPGA_RS485_INA_TTL_1 IC15-Y12
FPGA_RS485_INA_TTL_2 IC15-AB12
FPGA_RS485_INA_TTL_3 IC15-AB11
FPGA_RS485_INA_TTL_4 IC15-AB10
FPGA_RS485_INA_TTL_5 IC15-AB9
FPGA_RS485_INA_TTL_6 IC15-AA8
FPGA_RS485_INB_TTL_1 IC15-AA12
FPGA_RS485_INB_TTL_2 IC15-Y11
FPGA_RS485_INB_TTL_3 IC15-Y10
FPGA_RS485_INB_TTL_4 IC15-AA10
FPGA_RS485_INB_TTL_5 IC15-AB8
FPGA_RS485_INB_TTL_6 IC15-AB7
FPGA_RS485_OE IC15-AB6
FPGA_RTMM0 IC15-V21
FPGA_RTMM1 IC15-V22
FPGA_RTMM2 IC15-U22
FPGA_RTMP0 IC15-W22
FPGA_RTMP1 IC15-Y22
FPGA_RTMP2 IC15-Y21
FPGA_SFP_LOS IC15-G3
FPGA_SFP_PRESENCE IC15-E3
FPGA_SFP_RATE_SELECT IC15-C4
FPGA_SFP_SCL IC15-F3
FPGA_SFP_SDA IC15-G4
FPGA_SYSRESET_N IC15-L20
FPGA_TRIG_RS485_1 IC15-W18
FPGA_TRIG_RS485_2 IC15-Y18
FPGA_TRIG_RS485_3 IC15-W17
FPGA_TRIG_RS485_4 IC15-Y17
FPGA_TRIG_RS485_5 IC15-Y16
FPGA_TRIG_RS485_6 IC15-Y15
FPGA_TRIG_TTL_OE IC15-M3
GND R134-2
INV_IN_1_N IC15-Y1
INV_IN_2_N IC15-Y2
INV_IN_3_N IC15-AA1
INV_IN_4_N IC15-AA2
INV_OUT_1 IC15-H1
INV_OUT_2 IC15-J1
INV_OUT_3 IC15-K2
INV_OUT_4 IC15-K1
LED_CTRL0 IC15-M5
LED_CTRL0_OEN IC15-M4
LED_CTRL1 IC15-K6
LED_CTRL1_OEN IC15-K5
LED_MULTICAST_2_0 IC15-F9
LED_MULTICAST_3_1 IC15-F10
LED_WR_GMT_TTL_TTLN IC15-E5
LED_WR_LINK_SYSERROR IC15-F7
LED_WR_OK_SYSPW IC15-F8
LED_WR_OWNADDR_I2C IC15-E6
MULTICAST_ADDR_1 IC15-B21
MULTICAST_ADDR_2 IC15-B22
MULTICAST_ADDR_3 IC15-C22
MULTICAST_ADDR_4 IC15-D21
P3V3 R100-2 R111-2 R133-2
PULSE_FRONT_LED1_N IC15-H3
PULSE_FRONT_LED2_N IC15-J4
PULSE_FRONT_LED3_N IC15-J3
PULSE_FRONT_LED4_N IC15-K3
PULSE_FRONT_LED5_N IC15-L4
PULSE_FRONT_LED6_N IC15-L3
PULSE_REAR_LED1 IC15-AB17
PULSE_REAR_LED2 IC15-AB19
PULSE_REAR_LED3 IC15-AA16
PULSE_REAR_LED4 IC15-AA18
PULSE_REAR_LED5 IC15-AB16
PULSE_REAR_LED6 IC15-AB18
RST IC15-M16
SCL_I IC15-F19
SCL_O IC15-E20
SCL_OE IC15-H18
SDA_I IC15-G20
SDA_O IC15-F20
SDA_OE IC15-J19
SFP_TX_DISABLE IC15-E4
SFP_TX_FAULT IC15-D2
THERMOMETER IC15-B1
TTL/INV_TTL_N IC15-L22
FPGA_HEADER_IN1 IC15-A17
FPGA_HEADER_IN2 IC15-A18
FPGA_HEADER_IN3 IC15-B18
FPGA_HEADER_IN4 IC15-A19
FPGA_HEADER_IN5 IC15-A20
FPGA_HEADER_IN6 IC15-B20
FPGA_HEADER_OUT1 IC15-F15
FPGA_HEADER_OUT2 IC15-F16
FPGA_HEADER_OUT3 IC15-F17
FPGA_HEADER_OUT4 IC15-F14
FPGA_HEADER_OUT5 IC15-H14
FPGA_HEADER_OUT6 IC15-H13
hdl/IMAGES/image1/constraints/V1/net2ucf.py 0 → 100644
View file @ 06886f17
#!/usr/bin/python
## @package net2ucf.py
# @author Matthieu Cattin, Carlos Gil Soriano.
# This is a modified net2ucf.py by Carlos Gil Soriano,
# previously done by Matthieu Cattin.
import re
## @class net2ucf class able to extract ucf files from an Altium NET files
class NET2UCF:
## @brief Constructor of the ucf extractor
# @param path_ucfFile Path to be written the ucf file
# @param path_excludedNetsFile A path with the nets files to be excluded
# @param ICid IC identificator to extract the ucf from
def __init__(self, path_netFile, path_ucfFile, path_excludedNetsFile, ICid):
if path_netFile.endswith('.NET'):
try:
self.netFile = open(path_netFile, "r")
except IOError as e:
print '.NET file does not exist!'
else:
raise Exception('Bad extension of the net file')
if path_ucfFile.endswith('.ucf'):
try:
self.ucfFile = open(path_ucfFile, "w")
except IOError as e:
print '.ucf file does not exist!'
else:
raise Exception('Bad extension of the ucf file')
if path_excludedNetsFile.endswith('.XNET'):
try:
self.excludedNetsFile = open(path_excludedNetsFile, "r")
except IOError as e:
print '.XNET file does not exist!'
print "I'm here!"
self.listExcludedNets = []
for line in self.excludedNetsFile:
ln = line.split()
self.listExcludedNets.append(ln[0])
print 'Excluded nets:\n' + str(self.listExcludedNets)
else:
raise Exception('Bad extension of the excluded nets file')
self.ICid = ICid
## @fn generateUCF(self)
# @brief Function that process the NET file and generates the UCF one.
def generateUCF(self):
for line in self.netFile:
ln = line.split()
skip = False
for item in self.listExcludedNets:
if ln[0].startswith(str(item)):
print str(ln[0])+'Omitted because is a excluded net'
skip = True
if skip == False:
try:
print ln;
if ln[1].startswith('IC15'):
self.ucfFile.write("NET \""+ln[0]+"\" LOC = "+ln[1].split('-')[1]+";\n")
except IOError as e:
print 'Bad line in FPGA.NET'
print '-------------------------------------'
print '-------- NET2UCF program --------'
print '-------------------------------------\n'
print 'Case sensitive!\n'
path_NetFile = raw_input('Insert the path of the NET file. Format is \n'+'-- [PATH]/[name].NET:\t')
path_ucfFile = raw_input('Insert path of the ucf file. Format is \n'+'-- [PATH]/[name].ucf:\t')
path_excludedNetsFile = raw_input('Insert path of the file containing nets not to be included'+ '-- [PATH]/[name].XNET:\t')
ICid = raw_input('Insert which IC to get the ucf file from:\t')
net2ucf_inst = NET2UCF(path_NetFile, path_ucfFile, path_excludedNetsFile, ICid)
net2ucf_inst.generateUCF()
hdl/IMAGES/image1/constraints/V1/rs485.ucf 0 → 100644
View file @ 06886f17
##---------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##----------------------------------------
NET "RST" LOC = M16;
NET "RST" IOSTANDARD = "LVCMOS33";
NET "FPGA_SYSRESET_N" LOC = L20;
NET "FPGA_SYSRESET_N" IOSTANDARD = "LVCMOS33";
NET "CLK20_VCXO" LOC = E16;
NET "CLK20_VCXO" IOSTANDARD = "LVCMOS33";
NET "CLK20_VCXO" TNM_NET = "CLK20_VCXO";
TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50%;
NET "FPGA_CLK_N" LOC = G11;
NET "FPGA_CLK_N" IOSTANDARD = "LVDS_25";
NET "FPGA_CLK_P" LOC = H12;
NET "FPGA_CLK_P" IOSTANDARD = "LVDS_25";
TIMESPEC TS_clk_i = PERIOD "FPGA_CLK_N" 125 MHz HIGH 50%;
TIMESPEC TS_clk_i = PERIOD "FPGA_CLK_P" 125 MHz HIGH 50%;
##======================================
##-- FRONT PANEL TTLS
##======================================
##-- LEDs
##--
##-- + UBT: LVTTL input
##-------------------
NET "LED_CTRL0" LOC = M5;
NET "LED_CTRL0" IOSTANDARD = "LVTTL";
NET "LED_CTRL0" DRIVE = "4";
NET "LED_CTRL0" SLEW = "QUIETIO";
NET "LED_CTRL0_OEN" LOC = M4;
NET "LED_CTRL0_OEN" IOSTANDARD = "LVTTL";
NET "LED_CTRL0_OEN" DRIVE = "4";
NET "LED_CTRL0_OEN" SLEW = "QUIETIO";
NET "LED_CTRL1" LOC = K6;
NET "LED_CTRL1" IOSTANDARD = "LVTTL";
NET "LED_CTRL1" DRIVE = "4";
NET "LED_CTRL1" SLEW = "QUIETIO";
NET "LED_CTRL1_OEN" LOC = K5;
NET "LED_CTRL1_OEN" IOSTANDARD = "LVTTL";
NET "LED_CTRL1_OEN" DRIVE = "4";
NET "LED_CTRL1_OEN" SLEW = "QUIETIO";
NET "LED_MULTICAST_2_0" LOC = F9;
NET "LED_MULTICAST_2_0" IOSTANDARD = "LVTTL";
NET "LED_MULTICAST_2_0" DRIVE = "4";
NET "LED_MULTICAST_2_0" SLEW = "QUIETIO";
NET "LED_MULTICAST_3_1" LOC = F10;
NET "LED_MULTICAST_3_1" IOSTANDARD = "LVTTL";
NET "LED_MULTICAST_3_1" DRIVE = "4";
NET "LED_MULTICAST_3_1" SLEW = "QUIETIO";
NET "LED_WR_GMT_TTL_TTLN" LOC = E5;
NET "LED_WR_GMT_TTL_TTLN" IOSTANDARD = "LVTTL";
NET "LED_WR_GMT_TTL_TTLN" DRIVE = "4";
NET "LED_WR_GMT_TTL_TTLN" SLEW = "QUIETIO";
NET "LED_WR_LINK_SYSERROR" LOC = F7;
NET "LED_WR_LINK_SYSERROR" IOSTANDARD = "LVTTL";
NET "LED_WR_LINK_SYSERROR" DRIVE = "4";
NET "LED_WR_LINK_SYSERROR" SLEW = "QUIETIO";
NET "LED_WR_OK_SYSPW" LOC = F8;
NET "LED_WR_OK_SYSPW" IOSTANDARD = "LVTTL";
NET "LED_WR_OK_SYSPW" DRIVE = "4";
NET "LED_WR_OK_SYSPW" SLEW = "QUIETIO";
NET "LED_WR_OWNADDR_I2C" LOC = E6;
NET "LED_WR_OWNADDR_I2C" IOSTANDARD = "LVTTL";
NET "LED_WR_OWNADDR_I2C" DRIVE = "4";
NET "LED_WR_OWNADDR_I2C" SLEW = "QUIETIO";
##-------------------
##-- Front channel LEDs
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "PULSE_FRONT_LED1_N" LOC = H3;
NET "PULSE_FRONT_LED1_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED1_N" DRIVE = "4";
NET "PULSE_FRONT_LED1_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED2_N" LOC = J4;
NET "PULSE_FRONT_LED2_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED2_N" DRIVE = "4";
NET "PULSE_FRONT_LED2_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED3_N" LOC = J3;
NET "PULSE_FRONT_LED3_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED3_N" DRIVE = "4";
NET "PULSE_FRONT_LED3_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED4_N" LOC = K3;
NET "PULSE_FRONT_LED4_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED4_N" DRIVE = "4";
NET "PULSE_FRONT_LED4_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED5_N" LOC = L4;
NET "PULSE_FRONT_LED5_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED5_N" DRIVE = "4";
NET "PULSE_FRONT_LED5_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED6_N" LOC = L3;
NET "PULSE_FRONT_LED6_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED6_N" DRIVE = "4";
NET "PULSE_FRONT_LED6_N" SLEW = "QUIETIO";
##-------------------
##-- Rear LEDs
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "PULSE_REAR_LED1" LOC = AB17;
NET "PULSE_REAR_LED1" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED1" DRIVE = "4";
NET "PULSE_REAR_LED1" SLEW = "QUIETIO";
NET "PULSE_REAR_LED2" LOC = AB19;
NET "PULSE_REAR_LED2" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED2" DRIVE = "4";
NET "PULSE_REAR_LED2" SLEW = "QUIETIO";
NET "PULSE_REAR_LED3" LOC = AA16;
NET "PULSE_REAR_LED3" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED3" DRIVE = "4";
NET "PULSE_REAR_LED3" SLEW = "QUIETIO";
NET "PULSE_REAR_LED4" LOC = AA18;
NET "PULSE_REAR_LED4" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED4" DRIVE = "4";
NET "PULSE_REAR_LED4" SLEW = "QUIETIO";
NET "PULSE_REAR_LED5" LOC = AB16;
NET "PULSE_REAR_LED5" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED5" DRIVE = "4";
NET "PULSE_REAR_LED5" SLEW = "QUIETIO";
NET "PULSE_REAR_LED6" LOC = AB18;
NET "PULSE_REAR_LED6" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED6" DRIVE = "4";
NET "PULSE_REAR_LED6" SLEW = "QUIETIO";
##-------------------
##-- TTL trigger inputs
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "FPGA_INPUT_TTL1_N" LOC = T3;
NET "FPGA_INPUT_TTL1_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL2_N" LOC = U4;
NET "FPGA_INPUT_TTL2_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL3_N" LOC = W3;
NET "FPGA_INPUT_TTL3_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL4_N" LOC = W4;
NET "FPGA_INPUT_TTL4_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL5_N" LOC = V3;
NET "FPGA_INPUT_TTL5_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL6_N" LOC = U3;
NET "FPGA_INPUT_TTL6_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL1" LOC = D1;
NET "FPGA_OUT_TTL1" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL2" LOC = E1;
NET "FPGA_OUT_TTL2" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL3" LOC = F2;
NET "FPGA_OUT_TTL3" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL4" LOC = F1;
NET "FPGA_OUT_TTL4" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL5" LOC = G1;
NET "FPGA_OUT_TTL5" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL6" LOC = H2;
NET "FPGA_OUT_TTL6" IOSTANDARD = "LVCMOS33";
##-------------------
##-- Bottomly allocated GPIOs
##--
##-- + IN ACT family: CMOS/TTL 3.3V inputs
##-- + OUT BCT family (BiCMOS): TTL inputs
##
##-- Schematics name: INV_IN_*
##---- renamed to INV_IN[*]
##-------------------
NET "INV_IN_1_N" LOC = Y1;
NET "INV_IN_1_N" IOSTANDARD = "LVCMOS33";
NET "INV_IN_2_N" LOC = Y2;
NET "INV_IN_2_N" IOSTANDARD = "LVCMOS33";
NET "INV_IN_3_N" LOC = AA2;
NET "INV_IN_3_N" IOSTANDARD = "LVCMOS33";
NET "INV_IN_4_N" LOC = AA2;
NET "INV_IN_4_N" IOSTANDARD = "LVCMOS33";
NET "INV_OUT_1" LOC = H1;
NET "INV_OUT_1" IOSTANDARD = "LVCMOS33";
NET "INV_OUT_2" LOC = J1;
NET "INV_OUT_2" IOSTANDARD = "LVCMOS33";
NET "INV_OUT_3" LOC = K2;
NET "INV_OUT_3" IOSTANDARD = "LVCMOS33";
NET "INV_OUT_4" LOC = K1;
NET "INV_OUT_4" IOSTANDARD = "LVCMOS33";
##======================================
##-- RTM signals
##======================================
##-- Blocking input to FPGA
##
##-------------------
NET "FPGA_RS485_INA_TTL_1" LOC = Y12;
NET "FPGA_RS485_INA_TTL_1" IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INA_TTL_2" LOC = AB12;
NET "FPGA_RS485_INA_TTL_2" IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INA_TTL_3" LOC = AB11;
NET "FPGA_RS485_INA_TTL_3" IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INA_TTL_4" LOC = AB10;
NET "FPGA_RS485_INA_TTL_4" IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INA_TTL_5" LOC = AB9;
NET "FPGA_RS485_INA_TTL_5" IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INA_TTL_6" LOC = AA8;
NET "FPGA_RS485_INA_TTL_6" IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INB_TTL_1" LOC = AA12;
NET "FPGA_RS485_INB_TTL_1" IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INB_TTL_2" LOC = Y11;
NET "FPGA_RS485_INB_TTL_2" IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INB_TTL_3" LOC = Y10;
NET "FPGA_RS485_INB_TTL_3" IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INB_TTL_4" LOC = AA10;
NET "FPGA_RS485_INB_TTL_4" IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INB_TTL_5" LOC = AB8;
NET "FPGA_RS485_INB_TTL_5" IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INB_TTL_6" LOC = AB7;
NET "FPGA_RS485_INB_TTL_6" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_RS485_1" LOC = W18;
NET "FPGA_TRIG_RS485_1" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_RS485_2" LOC = Y18;
NET "FPGA_TRIG_RS485_2" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_RS485_3" LOC = W17;
NET "FPGA_TRIG_RS485_3" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_RS485_4" LOC = Y17;
NET "FPGA_TRIG_RS485_4" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_RS485_5" LOC = Y16;
NET "FPGA_TRIG_RS485_5" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_RS485_6" LOC = Y15;
NET "FPGA_TRIG_RS485_6" IOSTANDARD = "LVCMOS33";
##======================================
##-- VME CONNECTOR SIGNALS
##======================================
##-- I2C lines
##--
##-- + UBT: LVTTL input
##-------------------
NET "SCL_I" LOC = F19;
NET "SCL_I" IOSTANDARD = "LVTTL";
NET "SCL_O" LOC = E20;
NET "SCL_O" IOSTANDARD = "LVTTL";
NET "SCL_O" DRIVE = "4";
NET "SCL_OE" LOC = H18;
NET "SCL_OE" IOSTANDARD = "LVTTL";
NET "SCL_OE" DRIVE = "4";
NET "SCL_OE" PULLDOWN;
NET "SDA_I" LOC = G20;
NET "SDA_I" IOSTANDARD = "LVTTL";
NET "SDA_O" LOC = F20;
NET "SDA_O" IOSTANDARD = "LVTTL";
NET "SDA_O" SLEW = "FAST";
NET "SDA_O" DRIVE = "4";
NET "SDA_O" PULLUP;
NET "SDA_OE" LOC = J19;
NET "SDA_OE" IOSTANDARD = "LVTTL";
NET "SDA_OE" SLEW = "FAST";
NET "SDA_OE" DRIVE = "4";
NET "SDA_OE" PULLDOWN;
##-------------------
##-- Geographical Address
##--
##-- + UBT: LVTTL input
##-------------------
NET "FPGA_GA0" LOC = H20;
NET "FPGA_GA0" IOSTANDARD = "LVTTL";
NET "FPGA_GA1" LOC = J20;
NET "FPGA_GA1" IOSTANDARD = "LVTTL";
NET "FPGA_GA2" LOC = K19;
NET "FPGA_GA2" IOSTANDARD = "LVTTL";
NET "FPGA_GA3" LOC = K20;
NET "FPGA_GA3" IOSTANDARD = "LVTTL";
NET "FPGA_GA4" LOC = L19;
NET "FPGA_GA4" IOSTANDARD = "LVTTL";
NET "FPGA_GAP" LOC = H19;
NET "FPGA_GAP" IOSTANDARD = "LVTTL";
##-------------------
##-- ROM memory
##-------------------
NET "FPGA_PROM_CCLK" LOC = Y20;
NET "FPGA_PROM_CCLK" IOSTANDARD = "LVTTL";
NET "FPGA_PROM_CSO_B_N" LOC = AA3;
NET "FPGA_PROM_CSO_B_N" IOSTANDARD = "LVTTL";
NET "FPGA_PROM_DIN" LOC = AA20;
NET "FPGA_PROM_DIN" IOSTANDARD = "LVTTL";
NET "FPGA_PROM_MOSI" LOC = AB20;
NET "FPGA_PROM_MOSI" IOSTANDARD = "LVTTL";
##======================================
##-- WHITE RABBIT
##======================================
##-------------------
##-- Thermo for UID
##-------------------
NET "THERMOMETER" LOC = B1;
NET "THERMOMETER" IOSTANDARD = "LVCMOS25";
##-------------------
##-- DACs control
##--
##-- + CMOS 3.3V input
##-------------------
NET "FPGA_PLLDAC1_DIN" LOC = Y14;
NET "FPGA_PLLDAC1_DIN" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC1_SCLK" LOC = AA14;
NET "FPGA_PLLDAC1_SCLK" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC1_SYNC_N" LOC = AB15;
NET "FPGA_PLLDAC1_SYNC_N" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC2_DIN" LOC = AB13;
NET "FPGA_PLLDAC2_DIN" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC2_SCLK" LOC = Y13;
NET "FPGA_PLLDAC2_SCLK" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC2_SYNC_N" LOC = AB14;
NET "FPGA_PLLDAC2_SYNC_N" IOSTANDARD = "LVCMOS25";
##-------------------
##-- SFP connection
##-------------------
NET "FPGA_SFP_LOS" LOC = G3;
NET "FPGA_SFP_LOS" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_PRESENCE" LOC = E3;
NET "FPGA_SFP_PRESENCE" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_RATE_SELECT" LOC = C4;
NET "FPGA_SFP_RATE_SELECT" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_SCL" LOC = F3;
NET "FPGA_SFP_SCL" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_SDA" LOC = G4;
NET "FPGA_SFP_SDA" IOSTANDARD = "LVCMOS33";
NET "SFP_TX_DISABLE" LOC = E4;
NET "SFP_TX_DISABLE" IOSTANDARD = "LVCMOS33";
NET "SFP_TX_FAULT" LOC = D2;
NET "SFP_TX_FAULT" IOSTANDARD = "LVCMOS33";
##-------------------
##-- FPGA MGT lines
##-------------------
NET "FPGAMGTCLK0_P" LOC = A10;
NET "FPGAMGTCLK0_P" IOSTANDARD = "LVDS_12";
NET "FPGAMGTCLK0_N" LOC = B10;
NET "FPGAMGTCLK0_N" IOSTANDARD = "LVDS_12";
NET "MGTSFPRX0_P" LOC = D7;
NET "MGTSFPRX0_P" IOSTANDARD = "LVDS_12";
NET "MGTSFPRX0_N" LOC = C7;
NET "MGTSFPRX0_N" IOSTANDARD = "LVDS_12";
NET "MGTSFPTX0_P" LOC = B6;
NET "MGTSFPTX0_P" IOSTANDARD = "LVDS_12";
NET "MGTSFPTX0_N" LOC = A6;
NET "MGTSFPTX0_N" IOSTANDARD = "LVDS_12";
##======================================
##-- ADDITIONAL PINS
##======================================
##--
##-- + HC CMOS 3.3V input
##-------------------
NET "FPGA_OE" LOC = N3;
NET "FPGA_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_OE" DRIVE = "4";
NET "FPGA_OE" SLEW = "QUIETIO";
NET "FPGA_RS485_OE" LOC = AB6;
NET "FPGA_RS485_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_OE" DRIVE = "4";
NET "FPGA_RS485_OE" SLEW = "QUIETIO";
NET "FPGA_TRIG_TTL_OE" LOC = M3;
NET "FPGA_TRIG_TTL_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_TTL_OE" DRIVE = "4";
NET "FPGA_TRIG_TTL_OE" SLEW = "QUIETIO";
NET "FPGA_INV_OE" LOC = N4;
NET "FPGA_INV_OE" IOSTANDARD = "LVCMOS33";
NET "FPGA_INV_OE" DRIVE = "4";
NET "FPGA_INV_OE" SLEW = "QUIETIO";
##-------------------
##-- Configuration Switches
##
##-------------------
NET "EXTRA_SWITCH_1" LOC = F22;
NET "EXTRA_SWITCH_1" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_2" LOC = G22;
NET "EXTRA_SWITCH_2" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_3" LOC = H21;
NET "EXTRA_SWITCH_3" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_4" LOC = H22;
NET "EXTRA_SWITCH_4" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_5" LOC = J22;
NET "EXTRA_SWITCH_5" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_6" LOC = K21;
NET "EXTRA_SWITCH_6" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_7" LOC = K22;
NET "EXTRA_SWITCH_7" IOSTANDARD = "LVCMOS33";
NET "TTL/INV_TTL_N" LOC = L22;
NET "TTL/INV_TTL_N" IOSTANDARD = "LVCMOS33";
NET "MULTICAST_ADDR_1" LOC = B21;
NET "MULTICAST_ADDR_1" IOSTANDARD = "LVCMOS33";
NET "MULTICAST_ADDR_2" LOC = B22;
NET "MULTICAST_ADDR_2" IOSTANDARD = "LVCMOS33";
NET "MULTICAST_ADDR_3" LOC = C22;
NET "MULTICAST_ADDR_3" IOSTANDARD = "LVCMOS33";
NET "MULTICAST_ADDR_4" LOC = D21;
NET "MULTICAST_ADDR_4" IOSTANDARD = "LVCMOS33";
##-------------------
##-- Motherboard and piggyback IDs
##--
##-- + ACT: CMOS 3.3V input
##-------------------
NET "FPGA_RTMM0" LOC = V21;
NET "FPGA_RTMM0" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM1" LOC = V22;
NET "FPGA_RTMM1" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM2" LOC = U22;
NET "FPGA_RTMM2" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP0" LOC = W22;
NET "FPGA_RTMP0" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP1" LOC = Y22;
NET "FPGA_RTMP1" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP2" LOC = Y21;
NET "FPGA_RTMP2" IOSTANDARD = "LVCMOS33";
##-------------------
##-- General purpose
##--
##-- + ACT: CMOS 3.3V input
##-------------------
NET "FPGA_HEADER_OUT1" LOC = F15;
NET "FPGA_HEADER_OUT1" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT2" LOC = F16;
NET "FPGA_HEADER_OUT2" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT3" LOC = F17;
NET "FPGA_HEADER_OUT3" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT4" LOC = F14;
NET "FPGA_HEADER_OUT4" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT5" LOC = H14;
NET "FPGA_HEADER_OUT5" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT6" LOC = H13;
NET "FPGA_HEADER_OUT6" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN1" LOC = A17;
NET "FPGA_HEADER_IN1" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN2" LOC = A18;
NET "FPGA_HEADER_IN2" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN3" LOC = B18;
NET "FPGA_HEADER_IN3" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN4" LOC = A19;
NET "FPGA_HEADER_IN4" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN5" LOC = A20;
NET "FPGA_HEADER_IN5" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN6" LOC = B20;
NET "FPGA_HEADER_IN6" IOSTANDARD = "LVCMOS33";
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