Commit 0e560f9a authored by gilsoriano@gmail.com's avatar gilsoriano@gmail.com

Schematics updated to revision 1

parent 902f7ddf
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-- SubModule Output_Unit_RS485
-- Created 04/04/2012 16:11:38
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library IEEE;
use IEEE.Std_Logic_1164.all;
entity Output_Unit_RS485 is port
(
RS485_L_N : out std_logic;
RS485_L_P : out std_logic;
RS485_C_N : out std_logic;
RS485_C_P : out std_logic;
RS485_R_N : out std_logic;
RS485_R_P : out std_logic;
FPGA_TRIG_RS485 : in std_logic;
FPGA_RS485_OUT_EN : in std_logic
);
end Output_Unit_RS485;
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architecture Structure of Output_Unit_RS485 is
-- Component Declarations
-- Signal Declarations
begin
end Structure;
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