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Conv TTL RS485
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Conv TTL RS485
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HW: TTL input pulse is stretched by hw before arriving to FPGA
#6
· opened
Nov 22, 2017
by
Denia Bouhired-Ferrag
bug
CLOSED
2
updated
Feb 12, 2019
Pull-down resistors required on rear LED lines
#7
· opened
Oct 06, 2017
by
Denia Bouhired-Ferrag
bug
CLOSED
3
updated
Feb 12, 2019
[V2-0] SFP I2C net names
#24
· opened
Nov 04, 2014
by
Theodor-Adrian Stana
bug
CLOSED
2
updated
Feb 12, 2019
[RTMP-V1] Front panel project reference wrong
#32
· opened
Jan 31, 2013
by
Theodor-Adrian Stana
bug
CLOSED
1
updated
Feb 12, 2019
[LEDs] Bicolour LEDs for RS485 RX line status
#35
· opened
Dec 04, 2012
by
Carlos Gil Soriano
bug
CLOSED
1
updated
Feb 12, 2019
[Serigraphy LEDs] Multicast
#36
· opened
Nov 16, 2012
by
Carlos Gil Soriano
bug
CLOSED
3
updated
Feb 12, 2019
[Array LEDs] Change Front Panel hole
#37
· opened
Nov 16, 2012
by
Carlos Gil Soriano
bug
CLOSED
1
updated
Feb 12, 2019
HW: Termination on i/p and o/p RS485 pairs
#4
· opened
Dec 13, 2017
by
Denia Bouhired-Ferrag
bug
CLOSED
2
updated
Feb 12, 2019
[RTMP-V1] RTMP recognition wrong in V1 panels
#33
· opened
Jan 31, 2013
by
Theodor-Adrian Stana
bug
CLOSED
1
updated
Feb 12, 2019
[RTM-V1] Guard traces between differential lines
#34
· opened
Jan 31, 2013
by
Theodor-Adrian Stana
bug
CLOSED
1
updated
Feb 12, 2019
[Top Overlay] Bad quality
#38
· opened
Nov 12, 2012
by
Carlos Gil Soriano
bug
CLOSED
2
updated
Feb 12, 2019
[Serigraphy] LEDs and WR text near SFP
#39
· opened
Nov 12, 2012
by
Carlos Gil Soriano
bug
CLOSED
2
updated
Feb 12, 2019
Unnecessary pull-up resisors on flash chip
#8
· opened
Oct 06, 2017
by
Denia Bouhired-Ferrag
bug
CLOSED
1
updated
Feb 12, 2019
[SFP] SFP+ connector
#40
· opened
Nov 12, 2012
by
Carlos Gil Soriano
bug
CLOSED
2
updated
Feb 12, 2019
PCB layout D-Sub9 RTM
#2
· opened
Mar 08, 2018
by
Denia Bouhired-Ferrag
bug
CLOSED
1
updated
Feb 12, 2019
[V2-0] Net names for general-purpose switches
#21
· opened
Dec 15, 2014
by
Theodor-Adrian Stana
bug
CLOSED
2
updated
Feb 12, 2019
[RTMP-V1] Web address on RTMP board is wrong
#31
· opened
Jan 31, 2013
by
Theodor-Adrian Stana
bug
CLOSED
1
updated
Feb 12, 2019
[FPGA] Rearrange FPGA pinout for SERDES triggers
#41
· opened
Nov 12, 2012
by
Carlos Gil Soriano
bug
1
updated
Feb 12, 2019