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Compact Universal Timing Endpoint based on White Rabbit
Commit d69dece1 authored by hongming's avatar hongming
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Add new branch for cute-wr test. 

    The top makefile cannot work.
    Open syn directory to compile the ise project.
parent 7d5e10f9
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View file @ d69dece1
syn
toolchain
*.tar.xz
.gitmodules
View file @ d69dece1
[submodule "submodules/wr-cores"]
path = submodules/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
branch = cute-wr
branch = cute-core-thu
[submodule "submodules/wrpc-sw"]
path = submodules/wrpc-sw
url = git://ohwr.org/hdl-core-lib/wr-cores/wrpc-sw.git
url = https://github.com/leehongming/wrpc_sw.git
branch = cure-core-thu
[submodule "submodules/hdl-make"]
path = submodules/hdl-make
url = git://ohwr.org/misc/hdl-make.git
......
Makefile
View file @ d69dece1
......@@ -69,13 +69,22 @@ program-clean:
rm -f *.bit
rm -f _impactbatch.log
# not for 64 bit arch
# lm32 compiler, not for 64 bit arch
gcc-4.5.3-lm32.tar.xz:
wget http://www.ohwr.org/attachments/1301/gcc-4.5.3-lm32.tar.xz
toolchain: gcc-4.5.3-lm32.tar.xz
tar xvJf gcc-4.5.3-lm32.tar.xz
# lm32 compiler, for 64 bit arch
lm32_gcc_host_64bit.tar.xz:
wget https://github.com/leehongming/lm32-gcc/raw/master/lm32_gcc_host_64bit.tar.xz
toolchain: gcc-4.5.3-lm32.tar.xz lm32_gcc_host_64bit.tar.xz
ifeq ($(shell getconf LONG_BIT),32) # For 32 bit os
tar -xvJf gcc-4.5.3-lm32.tar.xz
mv lm32 toolchain
else
tar -xvJf lm32_gcc_host_64bit.tar.xz # For 64 bit os
mv lm32-gcc-4.5.3 toolchain
endif
touch toolchain
toolchain-clean:
......
README.md
View file @ d69dece1
# CUTE-wr projects
## Add the commands into the .bashrc
### for xilinx ise
source /path/to/Xilinx/14.7/ISE_DS/settings64.sh
export XILINX=/path/to/Xilinx/14.7/ISE_DS/ISE
export PATH=$PATH:/path/to/Xilinx/14.7/ISE_DS/ISE/bin/lin64/
### for lm32 compiler
export PATH=$PATH:/path/to/current/dir/toolchain/bin
export CROSS_COMPILE="/path/to/current/dir/toolchain/bin/lm32-elf-"
## Code structure
* Gateware:
`submodules/wr-cores`
......
wr-cores @ f5e528e8
Subproject commit 581e8d024447dcee65be5a12ea3d421dc892d6b1
Subproject commit f5e528e8d8e984e1b8ee0f318c25b45c422adb01
wrpc-sw @ 86838291
Subproject commit 1c061f05778de9af7044d6fcb91c869cdf311508
Subproject commit 868382911acf359fe7301a09ed91029f916eed11
syn/cute_wr/wr_core_demo/Makefile
View file @ d69dece1
TARGET = cute_top
PROJECT = cute_top_wrc
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
include ../../../dir_list.mk
PROJECT := cute_top.xise
ISE_CRAP := *.b cute_top_summary.html *.tcl cute_top.bld cute_top.cmd_log *.drc cute_top.lso *.ncd cute_top.ngc cute_top.ngd cute_top.ngr cute_top.pad cute_top.par cute_top.pcf cute_top.prj cute_top.ptwx cute_top.stx cute_top.syr cute_top.twr cute_top.twx cute_top.gise $(PROJECT).gise cute_top.bgn cute_top.unroutes cute_top.ut cute_top.xpi cute_top.xst cute_top_bitgen.xwbt cute_top_envsettings.html cute_top_guide.ncd cute_top_map.map cute_top_map.mrp cute_top_map.ncd cute_top_map.ngm cute_top_map.xrpt cute_top_ngdbuild.xrpt cute_top_pad.csv cute_top_pad.txt cute_top_par.xrpt cute_top_summary.xml cute_top_usage.xml cute_top_xst.xrpt usage_statistics_webtalk.html par_usage_statistics.html webtalk.log webtalk_pn.xml run.tcl
.PHONY: all
all: $(TARGET)_wrc.bin
#target for performing local synthesis
local: syn_pre_cmd check_tool generate_tcl synthesis syn_post_cmd
$(PROJECT).xise: Manifest.py
python2.7 $(TOP)submodules/hdl-make/hdlmake ise-project
generate_tcl:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Synthesize - XST}" >> run.tcl
echo "process run {Translate}" >> run.tcl
echo "process run {Map}" >> run.tcl
echo "process run {Place & Route}" >> run.tcl
echo "process run {Generate Programming File}" >> run.tcl
# Xilinx UG658
$(TARGET)_wrc.bit: $(FW_DIR)/wrc.elf $(TARGET).bit $(TARGET)_bd.bmm
data2mem -bm $(word 3, $^) -bd $< -bt $(word 2, $^) -o b $@
synthesis:
/media/opt/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
$(TARGET)_wrc.bin: $(TARGET)_wrc.bit
promgen -u 0x0 $< -p bin -w -b
check_tool:
$(TARGET).bmm: $(GW_DIR)/top/cute_wr/wr_core_demo/cute.bmm
cp $< $@
syn_post_cmd:
$(TARGET)_bd.bmm $(TARGET).bit: $(PROJECT).xise $(TARGET).bmm
printf "project open $< \n\
project set {Hierarchy Separator} / \n\
xfile add $(word 2, $^) \n\
process run {Generate Programming File} -force rerun" | xtclsh
ISE_CRAP := *.b *.html $(TARGET).bgn $(TARGET).bld $(TARGET).cmd_log *.drc $(TARGET).lso *.ncd $(TARGET).ngc $(TARGET).ngd $(TARGET).ngr $(TARGET).pad $(TARGET).par $(TARGET).pcf $(TARGET).prj $(TARGET).ptwx $(TARGET).stx $(TARGET).syr $(TARGET).twr $(TARGET).twx $(TARGET).gise $(TARGET).unroutes $(TARGET).ut $(TARGET).xpi $(TARGET).xst $(TARGET)_bitgen.xwbt $(TARGET)_guide.ncd $(TARGET)_map.map $(TARGET)_map.mrp $(TARGET)_map.ncd $(TARGET)_map.ngm $(TARGET)_map.xrpt $(TARGET)_ngdbuild.xrpt $(TARGET)_pad.csv $(TARGET)_pad.txt $(TARGET)_par.xrpt $(TARGET)_summary.xml $(TARGET)_usage.xml $(TARGET)_xst.xrpt webtalk.log webtalk_pn.xml run.tcl $(PROJECT).gise $(TARGET)_wrc.prm $(TARGET)_wrc.cfi
syn_pre_cmd:
#target for cleaning all intermediate stuff
clean:
rm -f $(PROJECT).xise $(ISE_CRAP) *.bmm
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
USER:=$(HDLMAKE_RSYNTH_USER)# take the value from the environment
SERVER:=$(HDLMAKE_RSYNTH_SERVER)# take the value from the environment
ISE_PATH:=$(HDLMAKE_RSYNTH_ISE_PATH)
R_NAME:=hm/cute_top
PORT:=22
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
endif
ifeq (x$(ISE_PATH),x)
@echo "Remote synthesis server is not set. You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
endif
CWD := $(shell pwd)
FILES := ../../../submodules/wr-cores/top/cute_wrc/ip_cores/cute_wrc.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../submodules/wr-cores/modules/wr_dacs/spec_serial_dac.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../../submodules/wr-cores/modules/wr_tlu/tlu_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../../submodules/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd \
../../../submodules/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../../top/cute_wr/wr_core_demo/user_tcp_demo.vhd \
../../../submodules/wr-cores/modules/wrc_core/xwr_core.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_flags.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_sync_register.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wbgenplus/wb_skidpad.vhd \
../../../submodules/wr-cores/modules/wr_streamers/xtx_streamer.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../../submodules/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../../submodules/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc \
../../../submodules/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_offset.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd \
../../../submodules/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
run.tcl \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../../submodules/wr-cores/modules/fabric/xwrf_reg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/generic/inferred_sync_fifo.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_rx_path.vhd \
../../../submodules/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../../submodules/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd \
../../../submodules/wr-cores/modules/wrc_core/xcute_core.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_sdp.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_search.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../../submodules/wr-cores/modules/fabric/xwb_fabric_sink.vhd \
../../../submodules/wr-cores/top/cute_wrc/ip_cores/wrc.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../../submodules/wr-cores/modules/fabric/wr_fabric_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../../submodules/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_channel.vhd \
../../../submodules/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_tx_path.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_ac_wbm_auto.vhd \
../../../submodules/wr-cores/modules/wr_streamers/rx_streamer.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram_mixed.vhd \
../../../submodules/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd \
../../../submodules/wr-cores/modules/wr_streamers/xrx_streamer.vhd \
../../../submodules/wr-cores/modules/wrc_core/wb_reset.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../../submodules/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd \
../../../submodules/wr-cores/modules/wrc_core/wrc_dpram.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../../submodules/wr-cores/modules/wr_dacs/cute_serial_dac.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_wb_event.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../../submodules/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd \
../../../submodules/wr-cores/modules/wr_streamers/streamers_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_shiftreg_fifo.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_wr_time.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
../../../submodules/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../../submodules/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/matrix_pkg.vhd \
../../../submodules/wr-cores/modules/wrc_core/cute_core.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_ac_wbm.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_walker.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_gpio_channel.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
../../../submodules/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd \
../../../submodules/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
../../../submodules/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_scubus_channel.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../../submodules/wr-cores/modules/wrc_core/wrcore_pkg.vhd \
../../../submodules/wr-cores/modules/timing/dmtd_phase_meas.vhd \
../../../submodules/wr-cores/modules/wr_lhaaso_ed/lhaaso_ed_wb.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
../../../submodules/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd \
../../../submodules/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd \
../../../submodules/wr-cores/modules/wr_tlu/tlu.vhd \
../../../submodules/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd \
../../../submodules/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd \
../../../submodules/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../../submodules/wr-cores/modules/fabric/xwrf_mux.vhd \
../../../submodules/wr-cores/modules/wrc_core/wrc_periph.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_big_adder.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_reset.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd \
../../../submodules/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd \
../../../submodules/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd \
cute_top.xise \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../../submodules/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_queue_channel.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../../submodules/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd \
../../../top/cute_wr/wr_core_demo/cute_reset_gen.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd \
../../../submodules/wr-cores/modules/timing/dmtd_with_deglitcher.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd \
../../../submodules/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd \
../../../submodules/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd \
../../../submodules/wr-cores/modules/wrc_core/wr_core.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd \
../../../submodules/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../../submodules/wr-cores/modules/timing/pulse_stamper.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/wr_endpoint.vhd \
../../../submodules/wr-cores/modules/fabric/xwb_fabric_source.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd \
../../../submodules/wr-cores/modules/wr_streamers/dropping_buffer.vhd \
../../../submodules/wr-cores/modules/wr_dacs/cute_serial_dac_arb.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \
../../../submodules/wr-cores/modules/timing/pulse_gen.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_adder.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca_wb_channel.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
../../../submodules/wr-cores/modules/timing/hpll_period_detect.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd \
../../../submodules/wr-cores/modules/wr_streamers/gc_escape_detector.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd \
../../../submodules/wr-cores/modules/wr_lhaaso_ed/xwr_lhaaso_ed.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd \
../../../submodules/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../../submodules/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../../submodules/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd \
../../../submodules/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../../submodules/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd \
../../../submodules/wr-cores/modules/fabric/xwrf_loopback/wrf_loopback.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
../../../submodules/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../../top/cute_wr/wr_core_demo/xwr_com5402.ngc \
../../../submodules/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd \
../../../submodules/wr-cores/modules/wr_tlu/tlu_fsm.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd \
../../../submodules/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd \
../../../submodules/wr-cores/platform/xilinx/ext_pll_10_to_125m.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../../submodules/wr-cores/modules/wr_lhaaso_ed/wr_lhaaso_ed.vhd \
../../../submodules/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd \
../../../submodules/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../../submodules/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd \
../../../submodules/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd \
../../../submodules/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd \
../../../submodules/wr-cores/modules/wr_streamers/gc_escape_inserter.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../../top/cute_wr/wr_core_demo/cute_top.ucf \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
../../../top/cute_wr/wr_core_demo/cute_top.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../../submodules/wr-cores/modules/wr_streamers/tx_streamer.vhd \
../../../submodules/wr-cores/modules/wr_eca/wr_eca.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd
#target for running synthesis in the remote location
remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -e 'ssh -p $(PORT)' -Ravl $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ifeq (x$(HDLMAKE_RSYNTH_USE_SCREEN), x1)
ssh -t $(USER)@$(SERVER) 'screen bash -c "cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl"'
else
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl'
endif
sync:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)/$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
syn/cute_wr/wr_core_demo/Manifest.py
View file @ d69dece1
......@@ -6,10 +6,11 @@ syn_grade = "-3"
syn_package = "fgg484"
syn_top = "cute_top"
top_module = "cute_top"
syn_project = "cute_top_wrc.xise"
syn_project = "cute_top.xise"
syn_tool = "ise"
modules = {
"local" : [
"../../../submodules/wr-cores/top/cute_wr/wr_core_demo"
"../../../top/cute_wr/wr_core_demo"
]
}
syn/cute_wr/wr_core_demo/cute_top.xise 0 → 100644
View file @ d69dece1
This source diff could not be displayed because it is too large. You can view the blob instead.
top/cute_wr/wr_core_demo/Manifest.py 0 → 100644
View file @ d69dece1
files = ["cute_top.vhd", "cute_top.ucf", "cute_reset_gen.vhd","user_tcp_demo.vhd","xwr_com5402.ngc"]
modules = {
"local" : ["../../../submodules/wr-cores/top/cute_wrc/ip_cores/"]
}
top/cute_wr/wr_core_demo/cute_reset_gen.vhd 0 → 100644
View file @ d69dece1
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
entity cute_reset_gen is
port (
clk_sys_i : in std_logic;
rst_n_o : out std_logic
);
end cute_reset_gen;
architecture behavioral of cute_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal powerup_n : std_logic := '0';
begin -- behavioral
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n;
end behavioral;
top/cute_wr/wr_core_demo/cute_top.bmm 0 → 100644
View file @ d69dece1
/* FILE : cute_top.bmm
* Define a BRAM map for the LM32 memory "xwb_dpram".
* Run ISE Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
* attached to the ISE Project) to find out that there are 46 ramloops and each RAMB16
* Note: *THE RAMLOOP ORDER WITHIN A BUS_BLOCK IS VERY IMPORTANT!!!*
* Define ramloop 45 downto 0 and databits 31 downto 0 !!! Otherwise the memory
* content will be swapped and the program fails to execute. Aperently the ramloop
* number and bit definitions are not read by data2mem.
*
*
* Address space LM32 memory "xwb_dpram"
* g_dpram_size = 131072/4
* 64 stacks of size 2048 bytes is 131072 bytes
*
****************************************************************************************/
ADDRESS_SPACE lm32_wrpc_memory RAMB16 [0x00000000:0x0001FFFF]
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram1 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram2 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram3 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram4 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram5 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram6 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram7 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram8 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram9 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram10 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram11 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram12 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram13 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram14 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram15 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram16 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram17 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram18 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram19 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram20 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram21 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram22 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram23 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram24 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram25 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram26 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram27 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram28 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram29 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram30 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram31 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram32 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram33 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram34 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram35 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram36 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram37 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram38 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram39 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram40 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram41 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram42 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram43 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram44 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram45 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram46 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram47 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram48 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram49 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram50 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram51 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram52 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram53 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram54 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram55 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram56 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram57 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram58 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram59 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram60 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram61 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram62 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram63 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram64 [31:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
top/cute_wr/wr_core_demo/cute_top.ucf 0 → 100644
View file @ d69dece1
CONFIG VCCAUX = 3.3;
#bank 0
NET "clk_20m_vcxo_i" LOC = E16;
NET "clk_20m_vcxo_i" IOSTANDARD = LVCMOS33;
NET "clk_125m_pllref_n_i" LOC = F15;
NET "clk_125m_pllref_n_i" IOSTANDARD = LVDS_33;
NET "clk_125m_pllref_p_i" LOC = F14;
NET "clk_125m_pllref_p_i" IOSTANDARD = LVDS_33;
NET "fpga_pll_ref_clk_101_n_i" LOC = B10;
NET "fpga_pll_ref_clk_101_n_i" IOSTANDARD = LVDS_33;
NET "fpga_pll_ref_clk_101_p_i" LOC = A10;
NET "fpga_pll_ref_clk_101_p_i" IOSTANDARD = LVDS_33;
NET "dac_clr_n_o" LOC = B22;
NET "dac_clr_n_o" IOSTANDARD = LVCMOS33;
NET "dac_sclk_o" LOC = D22;
NET "dac_sclk_o" IOSTANDARD = LVCMOS33;
NET "dac_din_o" LOC = D21;
NET "dac_din_o" IOSTANDARD = LVCMOS33;
NET "dac_ldac_n_o" LOC = C22;
NET "dac_ldac_n_o" IOSTANDARD = LVCMOS33;
NET "dac_sync_n_o" LOC = E22;
NET "dac_sync_n_o" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def1_b" LOC = D1;
NET "sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def0_i" LOC = D2;
NET "sfp_mod_def0_i" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def2_b" LOC = E1;
NET "sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
NET "sfp_rate_select_b" LOC = C1;
NET "sfp_rate_select_b" IOSTANDARD = LVCMOS33;
NET "sfp_tx_fault_i" LOC = F1;
NET "sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
NET "sfp_tx_disable_o" LOC = F2;
NET "sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "sfp_los_i" LOC = B1;
NET "sfp_los_i" IOSTANDARD = LVCMOS33;
NET "sfp_rxp_i" LOC = D9;
NET "sfp_rxn_i" LOC = C9;
NET "sfp_txp_o" LOC = B8;
NET "sfp_txn_o" LOC = A8;
NET "pps_o" LOC = A5;
NET "pps_o" IOSTANDARD = LVCMOS33;
NET "fpga_scl_b" LOC = G22;
NET "fpga_scl_b" IOSTANDARD = LVCMOS33;
NET "fpga_sda_b" LOC = F22;
NET "fpga_sda_b" IOSTANDARD = LVCMOS33;
NET "thermo_id_b" LOC = F21;
NET "thermo_id_b" IOSTANDARD = LVCMOS33;
NET "led_red" LOC = A4;
NET "led_red" IOSTANDARD = LVCMOS33;
NET "led_green" LOC = C5;
NET "led_green" IOSTANDARD = LVCMOS33;
NET "led_test" LOC = A17;
NET "led_test" IOSTANDARD = LVCMOS33;
NET "uart_rxd_i" LOC = B3;
NET "uart_rxd_i" IOSTANDARD = LVCMOS33;
NET "uart_txd_o" LOC = A3;
NET "uart_txd_o" IOSTANDARD = LVCMOS33;
#---------------------------------------------------------------------------------------------
# CLOCK Period Information
#---------------------------------------------------------------------------------------------
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50 %;
NET "clk_125m_pllref_p_i" TNM_NET = "clk_125m_pllref_p_i";
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50 %;
NET "clk_125m_pllref_n_i" TNM_NET = "clk_125m_pllref_n_i";
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50 %;
NET "fpga_pll_ref_clk_101_p_i" TNM_NET = "fpga_pll_ref_clk_101_p_i";
TIMESPEC TS_fpga_pll_ref_clk_101_p_i = PERIOD "fpga_pll_ref_clk_101_p_i" 8 ns HIGH 50 %;
NET "fpga_pll_ref_clk_101_n_i" TNM_NET = "fpga_pll_ref_clk_101_n_i";
TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 8 ns HIGH 50 %;
#INST "U_WR_CORE/u_wr_core/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB =FORCE;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" TNM = "skew_limit";
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" TNM = "skew_limit";
#TIMESPEC TS_ = FROM "skew_limit" TO FFS 1 ns DATAPATHONLY;
#
#INST "U_WR_CORE/u_wr_core/WRPC/LM32_CORE" AREA_GROUP = "pblock_LM32_CORE";
#AREA_GROUP "pblock_LM32_CORE" RANGE=SLICE_X34Y0:SLICE_X59Y23, SLICE_X30Y2:SLICE_X33Y23;
#AREA_GROUP "pblock_LM32_CORE" RANGE=DSP48_X1Y0:DSP48_X1Y5;
#AREA_GROUP "pblock_LM32_CORE" RANGE=RAMB16_X2Y0:RAMB16_X3Y10;
#AREA_GROUP "pblock_LM32_CORE" RANGE=RAMB8_X2Y0:RAMB8_X3Y11;
#INST "U_WR_CORE/u_wr_core/WRPC/WB_CON" AREA_GROUP = "pblock_WB_CON";
#AREA_GROUP "pblock_WB_CON" RANGE=SLICE_X30Y24:SLICE_X59Y31;
#AREA_GROUP "pblock_WB_CON" RANGE=DSP48_X1Y6:DSP48_X1Y7;
#AREA_GROUP "pblock_WB_CON" RANGE=RAMB16_X2Y12:RAMB16_X3Y14;
#AREA_GROUP "pblock_WB_CON" RANGE=RAMB8_X2Y12:RAMB8_X3Y15;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0" BEL = AFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0" LOC = SLICE_X31Y63;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d0" BEL = AFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d0" LOC = SLICE_X31Y64;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d1" BEL = BFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d1" LOC = SLICE_X31Y64;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d3" BEL = DFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d3" LOC = SLICE_X31Y64;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d2" BEL = CFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d2" LOC = SLICE_X31Y64;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" BEL = A5FF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" LOC = SLICE_X30Y64;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" BEL = A5FF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" LOC = SLICE_X30Y63;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d2" BEL = DFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d2" LOC = SLICE_X31Y63;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" BEL = CFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" LOC = SLICE_X31Y63;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d1" BEL = BFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d1" LOC = SLICE_X31Y63;
top/cute_wr/wr_core_demo/cute_top.vhd 0 → 100644
View file @ d69dece1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wishbone_pkg.all;
use work.etherbone_pkg.all;
entity cute_top is
port
(
-- Global ports
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
fpga_pll_ref_clk_101_p_i : in std_logic; -- Dedicated clock for Xilinx GTP transceiver
fpga_pll_ref_clk_101_n_i : in std_logic;
-- Font panel LEDs
led_red : out std_logic;
led_green : out std_logic;
led_test : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
dac_clr_n_o : out std_logic;
dac_ldac_n_o : out std_logic;
dac_sync_n_o : out std_logic;
fpga_scl_b : inout std_logic;
fpga_sda_b : inout std_logic;
thermo_id_b : inout std_logic; -- 1-Wire interface to DS18B20
-------------------------------------------------------------------------
-- SFP pins
-------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_b : inout std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
-----------------------------------------
--UART
-----------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
----------------------------------------
-- PPS
---------------------------------------
pps_o : out std_logic
);
end cute_top;
architecture rtl of cute_top is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component cute_wrc is
generic
(
g_etherbone_enable: boolean:= true;
g_multiboot_enable: boolean:= true
);
port
(
clk_20m_i : in std_logic;
clk_sys_i : in std_logic; -- 62.5m system clock, from pll drived by clk_125m_pllref
clk_dmtd_i : in std_logic; -- 62.5m dmtd clock, from pll drived by clk_20m_vcxo
clk_ref_i : in std_logic; -- 125m reference clock
clk_gtp_i : in std_logic; -- dedicated clock for xilinx gtp transceiver
rst_n_i : in std_logic;
-- font panel leds
led_red : out std_logic;
led_green : out std_logic;
led_test : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
dac_clr_n_o : out std_logic;
dac_ldac_n_o : out std_logic;
dac_sync_n_o : out std_logic;
fpga_scl_i : in std_logic;
fpga_scl_o : out std_logic;
fpga_sda_i : in std_logic;
fpga_sda_o : out std_logic;
--button1_i : in std_logic := 'h';
--button2_i : in std_logic := 'h';
----------------------------------------
-- Flash memory SPI
---------------------------------------
fpga_prom_cclk_o : out std_logic;
fpga_prom_cso_b_n_o : out std_logic;
fpga_prom_mosi_o : out std_logic;
fpga_prom_miso_i : in std_logic:='1';
thermo_id_i : in std_logic;
thermo_id_o : out std_logic; -- 1-wire interface to ds18b20
-------------------------------------------------------------------------
-- sfp pins
-------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_i : in std_logic; -- scl
sfp_mod_def1_o : out std_logic; -- scl
sfp_mod_def2_i : in std_logic; -- sda
sfp_mod_def2_o : out std_logic; -- sda
sfp_rate_select_i : in std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
pps_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
-----------------------------------------
--uart
-----------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
------------------------------------------
-- external module
------------------------------------------
ext_snk_i : in t_wrf_sink_in;
ext_snk_o : out t_wrf_sink_out;
ext_src_o : out t_wrf_source_out;
ext_src_i : in t_wrf_source_in;
ext_master_i : in t_wishbone_master_in:=cc_unused_master_in;
ext_master_o : out t_wishbone_master_out
);
end component;
component xwr_com5402 is
generic(
g_use_wishbone_interface : boolean := true;
-- use wishbone interface to configure ip/mac addr
nudptx: integer range 0 to 1:= 1;
nudprx: integer range 0 to 1:= 1;
-- number of udp ports enabled for tx and rx
ntcpstreams: integer range 0 to 255 := 1;
-- number of concurrent tcp streams handled by this component
clk_frequency: integer := 120;
-- clk frequency in mhz. needed to compute actual delays.
tx_idle_timeout: integer range 0 to 50:= 50;
-- inactive input timeout, expressed in 4us units. -- 50*4us = 200us
-- controls the transmit stream segmentation: data in the elastic buffer will be transmitted if
-- no input is received within tx_idle_timeout, without waiting for the transmit frame to be filled with mss data bytes.
simulation: std_logic := '0'
-- 1 during simulation with wireshark .cap file, '0' otherwise
-- wireshark many not be able to collect offloaded checksum computations.
-- when simulation = '1': (a) ip header checksum is valid if 0000,
-- (b) tcp checksum computation is forced to a valid 00001 irrespective of the 16-bit checksum
-- captured by wireshark.
);
port(
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
udp_rx_data : out std_logic_vector(7 downto 0);
udp_rx_data_valid : out std_logic;
udp_rx_sof : out std_logic;
udp_rx_eof : out std_logic;
udp_tx_data : in std_logic_vector(7 downto 0):= (others=>'0');
udp_tx_data_valid : in std_logic:= '0';
udp_tx_sof : in std_logic:= '0';
udp_tx_eof : in std_logic:= '0';
udp_tx_cts : out std_logic;
udp_tx_ack : out std_logic;
udp_tx_nak : out std_logic;
--// user-initiated connection reset for stream i
connection_reset: in std_logic_vector((ntcpstreams-1) downto 0):=(others=>'0');
tcp_rx_data : out std_logic_vector(7 downto 0);
tcp_rx_data_valid : out std_logic;
tcp_rx_rts : out std_logic;
tcp_rx_cts : in std_logic:='1';
tcp_tx_data : in std_logic_vector(7 downto 0):= (others=>'0');
tcp_tx_data_valid : in std_logic:='0';
tcp_tx_cts : out std_logic;
cfg_slave_in : in t_wishbone_slave_in:=cc_dummy_slave_in;
cfg_slave_out : out t_wishbone_slave_out;
tcp_local_port_no: in std_logic_vector(15 downto 0):=x"dcba";
udp_rx_dest_port_no: in std_logic_vector(15 downto 0):=x"abcd";
udp_tx_dest_ip_addr: in std_logic_vector(31 downto 0):=x"c0ab0201";
udp_tx_source_port_no: in std_logic_vector(15 downto 0):=x"abcd";
udp_tx_dest_port_no: in std_logic_vector(15 downto 0):=x"abcd"
);
end component;
component cute_reset_gen is
port (
clk_sys_i : in std_logic;
rst_n_o : out std_logic);
end component;
component user_tcp_demo is
port (
clk_i : in std_logic;
rst_n_i: in std_logic;
tcp_rx_data: in std_logic_vector(7 downto 0);
tcp_rx_data_valid:in std_logic;
tcp_tx_data: out std_logic_vector(7 downto 0);
tcp_tx_data_valid:out std_logic;
tcp_tx_cts: in std_logic;
tcp_rx_rts: in std_logic
);
end component;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- Reset
signal rst_n_i:std_logic;
-- Clock
signal clk_125m_pllref_i:std_logic;
signal clk_ref_i,clk_sys_i: std_logic;
signal clk_gtp_i,clk_dmtd_i:std_logic;
signal clk_20m_vcxo_buf:std_logic;
signal pllout_clk_62_5,pllout_clk_125:std_logic;
signal pllout_clk_fb_ref,pllout_clk_fb_dmtd:std_logic;
signal pllout_clk_dmtd:std_logic;
signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal pps : std_logic;
signal pps_led : std_logic;
signal tm_utc : std_logic_vector(39 downto 0);
signal brd_temp:std_logic_vector(31 downto 0);
signal temp:std_logic_vector(31 downto 0);
signal brd_temp_valid:std_logic;
signal sfp_mod_def1_i,sfp_mod_def1_o:std_logic;
signal sfp_mod_def2_i,sfp_mod_def2_o:std_logic;
signal fpga_scl_o : std_logic;
signal fpga_scl_i : std_logic;
signal fpga_sda_o : std_logic;
signal fpga_sda_i : std_logic;
signal thermo_id_i: std_logic;
signal thermo_id_o: std_logic;
signal ext_snk_i : t_wrf_sink_in;
signal ext_snk_o : t_wrf_sink_out;
signal ext_src_o : t_wrf_source_out:=c_dummy_snk_in;
signal ext_src_i : t_wrf_source_in;
signal ext_slave_in:t_wishbone_slave_in;
signal ext_slave_out:t_wishbone_slave_out;
signal tcp_rx_data : std_logic_vector(7 downto 0):= (others=>'0');
signal tcp_rx_data_valid : std_logic;
signal tcp_rx_rts : std_logic;
signal tcp_rx_cts : std_logic;
signal tcp_tx_data : std_logic_vector(7 downto 0):= (others=>'0');
signal tcp_tx_data_valid : std_logic;
signal tcp_tx_cts : std_logic;
signal ext_my_mac_addr : std_logic_vector(47 downto 0):=x"2233076cb3b5"; -- debug mac address
signal ext_my_ip_addr : std_logic_vector(31 downto 0):=x"c0a80024";
signal ext_my_subnet_mask: std_logic_vector(31 downto 0):=x"ffffff00";
signal ext_my_gateway : std_logic_vector(31 downto 0):=x"c0a80001";
signal ext_tcp_local_port_no: std_logic_vector(15 downto 0):=x"dcba";
signal ext_udp_rx_dest_port_no: std_logic_vector(15 downto 0):=x"dcba";
signal ext_udp_tx_dest_ip_addr: std_logic_vector(31 downto 0):=x"c0a80001";
signal ext_udp_tx_source_port_no: std_logic_vector(15 downto 0):=x"abcd";
signal ext_udp_tx_dest_port_no: std_logic_vector(15 downto 0):=x"abcd";
begin
U_Reset_Gen : cute_reset_gen
port map (
clk_sys_i => clk_sys_i,
rst_n_o => rst_n_i
);
cmp_refclk_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref_i, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
cmp_clk_vcxo_buf : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i
);
cmp_gtp_dedicated_clk_buf : IBUFGDS
generic map(
DIFF_TERM => true,
IBUF_LOW_PWR => true,
IOSTANDARD => "DEFAULT")
port map (
O => clk_gtp_i,
I => fpga_pll_ref_clk_101_p_i,
IB => fpga_pll_ref_clk_101_n_i
);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 4, -- 250 MHz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_ref,
CLKOUT0 => pllout_clk_62_5,
CLKOUT1 => pllout_clk_125,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_ref,
CLKIN => clk_125m_pllref_i
);
cmp_dmtd_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 62.5 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_dmtd,
CLKOUT0 => pllout_clk_dmtd,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_dmtd,
CLKIN => clk_20m_vcxo_buf
);
cmp_clk_sys_buf : BUFG
port map (
O => clk_sys_i,
I => pllout_clk_62_5
);
cmd_clk_ref_buf: BUFG
port map(
O => clk_ref_i,
I => pllout_clk_125
);
cmp_clk_dmtd_buf : BUFG
port map (
O => clk_dmtd_i,
I => pllout_clk_dmtd
);
pps_o <= pps;
U_WR_CORE : cute_wrc
generic map(
g_etherbone_enable=>true,
g_multiboot_enable=>false
)
port map (
clk_20m_i => clk_20m_vcxo_buf,
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
clk_ref_i => clk_ref_i,
clk_gtp_i => clk_gtp_i,
rst_n_i => rst_n_i,
led_red => led_red,
led_green => led_green,
led_test => led_test,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o,
dac_clr_n_o => dac_clr_n_o,
dac_ldac_n_o=> dac_ldac_n_o,
dac_sync_n_o=> dac_sync_n_o,
fpga_scl_o => fpga_scl_o,
fpga_scl_i => fpga_scl_i,
fpga_sda_o => fpga_sda_o,
fpga_sda_i => fpga_sda_i,
thermo_id_i => thermo_id_i,
thermo_id_o => thermo_id_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i=> sfp_mod_def0_i,
sfp_mod_def1_i=> sfp_mod_def1_i,
sfp_mod_def1_o=> sfp_mod_def1_o,
sfp_mod_def2_i=> sfp_mod_def2_i,
sfp_mod_def2_o=> sfp_mod_def2_o,
sfp_rate_select_i=> '1',
sfp_rate_select_o=> open,
sfp_tx_fault_i=> sfp_tx_fault_i,
sfp_tx_disable_o=> sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
tm_tai_o => tm_utc,
pps_o => pps,
ext_snk_o => ext_src_i,
ext_snk_i => ext_src_o,
ext_src_o => ext_snk_i,
ext_src_i => ext_snk_o,
ext_master_i => ext_slave_out,
ext_master_o => ext_slave_in
);
u_xwr_com5402: xwr_com5402
port map(
rst_n_i => rst_n_i,
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
snk_i => ext_snk_i,
snk_o => ext_snk_o,
src_o => ext_src_o,
src_i => ext_src_i,
-- udp_rx_data => udp_rx_data,
-- udp_rx_data_valid => udp_rx_data_valid,
-- udp_rx_sof => udp_rx_sof,
-- udp_rx_eof => udp_rx_eof,
--
-- udp_tx_data => udp_tx_data,
-- udp_tx_data_valid => udp_tx_data_valid,
-- udp_tx_sof => udp_tx_sof,
-- udp_tx_eof => udp_tx_eof,
-- udp_tx_cts => udp_tx_cts,
-- udp_tx_ack => udp_tx_ack,
-- udp_tx_nak => udp_tx_nak,
connection_reset => (others=>'0'),
tcp_rx_data => tcp_rx_data,
tcp_rx_data_valid => tcp_rx_data_valid,
tcp_tx_data => tcp_tx_data,
tcp_tx_data_valid => tcp_tx_data_valid,
tcp_tx_cts => tcp_tx_cts,
cfg_slave_in => ext_slave_in,
cfg_slave_out => ext_slave_out
);
Inst_tcp_demo: user_tcp_demo
port map(
clk_i => clk_ref_i,
rst_n_i => rst_n_i,
tcp_rx_data => tcp_rx_data,
tcp_rx_data_valid => tcp_rx_data_valid,
tcp_tx_data => tcp_tx_data,
tcp_tx_data_valid => tcp_tx_data_valid,
tcp_tx_cts => tcp_tx_cts,
tcp_rx_rts => tcp_rx_rts
);
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if (brd_temp_valid='1') then
temp <= brd_temp;
else
temp <= (others=>'0');
end if;
end if;
end process;
fpga_scl_b <= '0' when fpga_scl_o = '0' else 'Z';
fpga_sda_b <= '0' when fpga_sda_o = '0' else 'Z';
fpga_scl_i <= fpga_scl_b;
fpga_sda_i <= fpga_sda_b;
sfp_mod_def1_b <= '0' when sfp_mod_def1_o = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_mod_def2_o = '0' else 'Z';
sfp_mod_def1_i <= sfp_mod_def1_b;
sfp_mod_def2_i <= sfp_mod_def2_b;
thermo_id_b <= '0' when thermo_id_o = '1' else 'Z';
thermo_id_i <= thermo_id_b;
end rtl;
top/cute_wr/wr_core_demo/user_tcp_demo.vhd 0 → 100644
View file @ d69dece1
-------------------------------------------------------------------------------
-- Title : Demo for TCP transmitting & receiving with cutewr-tcp
-- Project :
-------------------------------------------------------------------------------
-- File : user_tcp_demo.vhd
-- Author : lihm
-- Company : Tsinghua
-- Created : 2016-03-11
-- Last update: 2016-03-11
-- Platform : Xilinx Spartan 6
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple demo for TCP transmitting and receiving.
-- Usage: Send me a normal tcp connect request from ip_address:8000. Then I
-- will send out tcp frame as much as possible.
-------------------------------------------------------------------------------
--
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-11 1.0 lihm Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity user_tcp_demo is
port (
clk_i : in std_logic;
rst_n_i: in std_logic;
tcp_rx_data: in std_logic_vector(7 downto 0);
tcp_rx_data_valid:in std_logic;
tcp_tx_data: out std_logic_vector(7 downto 0);
tcp_tx_data_valid:out std_logic;
tcp_tx_cts: in std_logic;
tcp_rx_rts: in std_logic
) ;
end entity ; -- user_tcp_demo
architecture behavioral of user_tcp_demo is
signal tcp_data:std_logic_vector(7 downto 0);
signal tcp_data_valid:std_logic;
type t_tx_state is(T_IDLE,T_START,T_DATA,T_END);
signal tx_state : t_tx_state;
begin
tcp_tx_data_valid <= tcp_data_valid;
tcp_tx_data <= tcp_data;
U_tcp_tx_demo : process( clk_i )
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
tcp_data_valid <= '0';
tcp_data <= (others=>'0');
tx_state <= T_IDLE;
else
case( tx_state ) is
when T_IDLE =>
tcp_data_valid <= '0';
tcp_data <= (others=>'0');
if tcp_rx_data_valid = '1' and tcp_tx_cts = '1' then
tx_state<= T_START;
tcp_data_valid <= '1';
tcp_data <= tcp_rx_data;
end if ;
when T_START =>
tcp_data <= tcp_rx_data;
tcp_data_valid <= '1';
if tcp_rx_data_valid = '0' then
tx_state <= T_END;
tcp_data_valid <= '0';
tcp_data <= (others=>'0');
end if ;
when T_END =>
tcp_data_valid <= '0';
tcp_data <= (others=>'0');
tx_state <= T_IDLE;
when others =>
tx_state <= T_IDLE;
end case ;
end if ;
end if ;
end process ; -- U_tcp_tx_demo
end behavioral;
top/cute_wr/wr_core_demo/xwr_com5402.ngc 0 → 100644
View file @ d69dece1
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