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Compact Universal Timing Endpoint based on White Rabbit
Commit d69dece1 authored by hongming's avatar hongming
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Add new branch for cute-wr test. 

    The top makefile cannot work.
    Open syn directory to compile the ise project.
parent 7d5e10f9
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.gitignore 0 → 100644
View file @ d69dece1
syn
toolchain
*.tar.xz
.gitmodules
View file @ d69dece1
[submodule "submodules/wr-cores"]
path = submodules/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
branch = cute-wr
branch = cute-core-thu
[submodule "submodules/wrpc-sw"]
path = submodules/wrpc-sw
url = git://ohwr.org/hdl-core-lib/wr-cores/wrpc-sw.git
url = https://github.com/leehongming/wrpc_sw.git
branch = cure-core-thu
[submodule "submodules/hdl-make"]
path = submodules/hdl-make
url = git://ohwr.org/misc/hdl-make.git
......
Makefile
View file @ d69dece1
......@@ -69,13 +69,22 @@ program-clean:
rm -f *.bit
rm -f _impactbatch.log
# not for 64 bit arch
# lm32 compiler, not for 64 bit arch
gcc-4.5.3-lm32.tar.xz:
wget http://www.ohwr.org/attachments/1301/gcc-4.5.3-lm32.tar.xz
toolchain: gcc-4.5.3-lm32.tar.xz
tar xvJf gcc-4.5.3-lm32.tar.xz
# lm32 compiler, for 64 bit arch
lm32_gcc_host_64bit.tar.xz:
wget https://github.com/leehongming/lm32-gcc/raw/master/lm32_gcc_host_64bit.tar.xz
toolchain: gcc-4.5.3-lm32.tar.xz lm32_gcc_host_64bit.tar.xz
ifeq ($(shell getconf LONG_BIT),32) # For 32 bit os
tar -xvJf gcc-4.5.3-lm32.tar.xz
mv lm32 toolchain
else
tar -xvJf lm32_gcc_host_64bit.tar.xz # For 64 bit os
mv lm32-gcc-4.5.3 toolchain
endif
touch toolchain
toolchain-clean:
......
README.md
View file @ d69dece1
# CUTE-wr projects
## Add the commands into the .bashrc
### for xilinx ise
source /path/to/Xilinx/14.7/ISE_DS/settings64.sh
export XILINX=/path/to/Xilinx/14.7/ISE_DS/ISE
export PATH=$PATH:/path/to/Xilinx/14.7/ISE_DS/ISE/bin/lin64/
### for lm32 compiler
export PATH=$PATH:/path/to/current/dir/toolchain/bin
export CROSS_COMPILE="/path/to/current/dir/toolchain/bin/lm32-elf-"
## Code structure
* Gateware:
`submodules/wr-cores`
......
wr-cores @ f5e528e8
Subproject commit 581e8d024447dcee65be5a12ea3d421dc892d6b1
Subproject commit f5e528e8d8e984e1b8ee0f318c25b45c422adb01
wrpc-sw @ 86838291
Subproject commit 1c061f05778de9af7044d6fcb91c869cdf311508
Subproject commit 868382911acf359fe7301a09ed91029f916eed11
syn/cute_wr/wr_core_demo/Makefile
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This diff is collapsed.
syn/cute_wr/wr_core_demo/Manifest.py
View file @ d69dece1
......@@ -6,10 +6,11 @@ syn_grade = "-3"
syn_package = "fgg484"
syn_top = "cute_top"
top_module = "cute_top"
syn_project = "cute_top_wrc.xise"
syn_project = "cute_top.xise"
syn_tool = "ise"
modules = {
"local" : [
"../../../submodules/wr-cores/top/cute_wr/wr_core_demo"
"../../../top/cute_wr/wr_core_demo"
]
}
syn/cute_wr/wr_core_demo/cute_top.xise 0 → 100644
View file @ d69dece1
This source diff could not be displayed because it is too large. You can view the blob instead.
top/cute_wr/wr_core_demo/Manifest.py 0 → 100644
View file @ d69dece1
files = ["cute_top.vhd", "cute_top.ucf", "cute_reset_gen.vhd","user_tcp_demo.vhd","xwr_com5402.ngc"]
modules = {
"local" : ["../../../submodules/wr-cores/top/cute_wrc/ip_cores/"]
}
top/cute_wr/wr_core_demo/cute_reset_gen.vhd 0 → 100644
View file @ d69dece1
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
entity cute_reset_gen is
port (
clk_sys_i : in std_logic;
rst_n_o : out std_logic
);
end cute_reset_gen;
architecture behavioral of cute_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal powerup_n : std_logic := '0';
begin -- behavioral
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n;
end behavioral;
top/cute_wr/wr_core_demo/cute_top.bmm 0 → 100644
View file @ d69dece1
/* FILE : cute_top.bmm
* Define a BRAM map for the LM32 memory "xwb_dpram".
* Run ISE Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
* attached to the ISE Project) to find out that there are 46 ramloops and each RAMB16
* Note: *THE RAMLOOP ORDER WITHIN A BUS_BLOCK IS VERY IMPORTANT!!!*
* Define ramloop 45 downto 0 and databits 31 downto 0 !!! Otherwise the memory
* content will be swapped and the program fails to execute. Aperently the ramloop
* number and bit definitions are not read by data2mem.
*
*
* Address space LM32 memory "xwb_dpram"
* g_dpram_size = 131072/4
* 64 stacks of size 2048 bytes is 131072 bytes
*
****************************************************************************************/
ADDRESS_SPACE lm32_wrpc_memory RAMB16 [0x00000000:0x0001FFFF]
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram1 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram2 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram3 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram4 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram5 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram6 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram7 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram8 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram9 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram10 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram11 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram12 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram13 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram14 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram15 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram16 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram17 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram18 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram19 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram20 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram21 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram22 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram23 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram24 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram25 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram26 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram27 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram28 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram29 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram30 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram31 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram32 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram33 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram34 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram35 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram36 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram37 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram38 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram39 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram40 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram41 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram42 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram43 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram44 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram45 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram46 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram47 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram48 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram49 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram50 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram51 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram52 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram53 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram54 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram55 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram56 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram57 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram58 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram59 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram60 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram61 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram62 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram63 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/u_wr_core/WRPC/DPRAM/U_DPRAM/gen_lm32_single_clk.U_RAM_LM32_SC/Mram_ram64 [31:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
top/cute_wr/wr_core_demo/cute_top.ucf 0 → 100644
View file @ d69dece1
CONFIG VCCAUX = 3.3;
#bank 0
NET "clk_20m_vcxo_i" LOC = E16;
NET "clk_20m_vcxo_i" IOSTANDARD = LVCMOS33;
NET "clk_125m_pllref_n_i" LOC = F15;
NET "clk_125m_pllref_n_i" IOSTANDARD = LVDS_33;
NET "clk_125m_pllref_p_i" LOC = F14;
NET "clk_125m_pllref_p_i" IOSTANDARD = LVDS_33;
NET "fpga_pll_ref_clk_101_n_i" LOC = B10;
NET "fpga_pll_ref_clk_101_n_i" IOSTANDARD = LVDS_33;
NET "fpga_pll_ref_clk_101_p_i" LOC = A10;
NET "fpga_pll_ref_clk_101_p_i" IOSTANDARD = LVDS_33;
NET "dac_clr_n_o" LOC = B22;
NET "dac_clr_n_o" IOSTANDARD = LVCMOS33;
NET "dac_sclk_o" LOC = D22;
NET "dac_sclk_o" IOSTANDARD = LVCMOS33;
NET "dac_din_o" LOC = D21;
NET "dac_din_o" IOSTANDARD = LVCMOS33;
NET "dac_ldac_n_o" LOC = C22;
NET "dac_ldac_n_o" IOSTANDARD = LVCMOS33;
NET "dac_sync_n_o" LOC = E22;
NET "dac_sync_n_o" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def1_b" LOC = D1;
NET "sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def0_i" LOC = D2;
NET "sfp_mod_def0_i" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def2_b" LOC = E1;
NET "sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
NET "sfp_rate_select_b" LOC = C1;
NET "sfp_rate_select_b" IOSTANDARD = LVCMOS33;
NET "sfp_tx_fault_i" LOC = F1;
NET "sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
NET "sfp_tx_disable_o" LOC = F2;
NET "sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "sfp_los_i" LOC = B1;
NET "sfp_los_i" IOSTANDARD = LVCMOS33;
NET "sfp_rxp_i" LOC = D9;
NET "sfp_rxn_i" LOC = C9;
NET "sfp_txp_o" LOC = B8;
NET "sfp_txn_o" LOC = A8;
NET "pps_o" LOC = A5;
NET "pps_o" IOSTANDARD = LVCMOS33;
NET "fpga_scl_b" LOC = G22;
NET "fpga_scl_b" IOSTANDARD = LVCMOS33;
NET "fpga_sda_b" LOC = F22;
NET "fpga_sda_b" IOSTANDARD = LVCMOS33;
NET "thermo_id_b" LOC = F21;
NET "thermo_id_b" IOSTANDARD = LVCMOS33;
NET "led_red" LOC = A4;
NET "led_red" IOSTANDARD = LVCMOS33;
NET "led_green" LOC = C5;
NET "led_green" IOSTANDARD = LVCMOS33;
NET "led_test" LOC = A17;
NET "led_test" IOSTANDARD = LVCMOS33;
NET "uart_rxd_i" LOC = B3;
NET "uart_rxd_i" IOSTANDARD = LVCMOS33;
NET "uart_txd_o" LOC = A3;
NET "uart_txd_o" IOSTANDARD = LVCMOS33;
#---------------------------------------------------------------------------------------------
# CLOCK Period Information
#---------------------------------------------------------------------------------------------
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50 %;
NET "clk_125m_pllref_p_i" TNM_NET = "clk_125m_pllref_p_i";
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50 %;
NET "clk_125m_pllref_n_i" TNM_NET = "clk_125m_pllref_n_i";
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50 %;
NET "fpga_pll_ref_clk_101_p_i" TNM_NET = "fpga_pll_ref_clk_101_p_i";
TIMESPEC TS_fpga_pll_ref_clk_101_p_i = PERIOD "fpga_pll_ref_clk_101_p_i" 8 ns HIGH 50 %;
NET "fpga_pll_ref_clk_101_n_i" TNM_NET = "fpga_pll_ref_clk_101_n_i";
TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 8 ns HIGH 50 %;
#INST "U_WR_CORE/u_wr_core/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB =FORCE;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" TNM = "skew_limit";
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" TNM = "skew_limit";
#TIMESPEC TS_ = FROM "skew_limit" TO FFS 1 ns DATAPATHONLY;
#
#INST "U_WR_CORE/u_wr_core/WRPC/LM32_CORE" AREA_GROUP = "pblock_LM32_CORE";
#AREA_GROUP "pblock_LM32_CORE" RANGE=SLICE_X34Y0:SLICE_X59Y23, SLICE_X30Y2:SLICE_X33Y23;
#AREA_GROUP "pblock_LM32_CORE" RANGE=DSP48_X1Y0:DSP48_X1Y5;
#AREA_GROUP "pblock_LM32_CORE" RANGE=RAMB16_X2Y0:RAMB16_X3Y10;
#AREA_GROUP "pblock_LM32_CORE" RANGE=RAMB8_X2Y0:RAMB8_X3Y11;
#INST "U_WR_CORE/u_wr_core/WRPC/WB_CON" AREA_GROUP = "pblock_WB_CON";
#AREA_GROUP "pblock_WB_CON" RANGE=SLICE_X30Y24:SLICE_X59Y31;
#AREA_GROUP "pblock_WB_CON" RANGE=DSP48_X1Y6:DSP48_X1Y7;
#AREA_GROUP "pblock_WB_CON" RANGE=RAMB16_X2Y12:RAMB16_X3Y14;
#AREA_GROUP "pblock_WB_CON" RANGE=RAMB8_X2Y12:RAMB8_X3Y15;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0" BEL = AFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0" LOC = SLICE_X31Y63;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d0" BEL = AFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d0" LOC = SLICE_X31Y64;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d1" BEL = BFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d1" LOC = SLICE_X31Y64;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d3" BEL = DFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d3" LOC = SLICE_X31Y64;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d2" BEL = CFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d2" LOC = SLICE_X31Y64;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" BEL = A5FF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" LOC = SLICE_X30Y64;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" BEL = A5FF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" LOC = SLICE_X30Y63;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d2" BEL = DFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d2" LOC = SLICE_X31Y63;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" BEL = CFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" LOC = SLICE_X31Y63;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d1" BEL = BFF;
#INST "U_WR_CORE/u_wr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d1" LOC = SLICE_X31Y63;
top/cute_wr/wr_core_demo/cute_top.vhd 0 → 100644
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top/cute_wr/wr_core_demo/user_tcp_demo.vhd 0 → 100644
View file @ d69dece1
-------------------------------------------------------------------------------
-- Title : Demo for TCP transmitting & receiving with cutewr-tcp
-- Project :
-------------------------------------------------------------------------------
-- File : user_tcp_demo.vhd
-- Author : lihm
-- Company : Tsinghua
-- Created : 2016-03-11
-- Last update: 2016-03-11
-- Platform : Xilinx Spartan 6
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple demo for TCP transmitting and receiving.
-- Usage: Send me a normal tcp connect request from ip_address:8000. Then I
-- will send out tcp frame as much as possible.
-------------------------------------------------------------------------------
--
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-11 1.0 lihm Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity user_tcp_demo is
port (
clk_i : in std_logic;
rst_n_i: in std_logic;
tcp_rx_data: in std_logic_vector(7 downto 0);
tcp_rx_data_valid:in std_logic;
tcp_tx_data: out std_logic_vector(7 downto 0);
tcp_tx_data_valid:out std_logic;
tcp_tx_cts: in std_logic;
tcp_rx_rts: in std_logic
) ;
end entity ; -- user_tcp_demo
architecture behavioral of user_tcp_demo is
signal tcp_data:std_logic_vector(7 downto 0);
signal tcp_data_valid:std_logic;
type t_tx_state is(T_IDLE,T_START,T_DATA,T_END);
signal tx_state : t_tx_state;
begin
tcp_tx_data_valid <= tcp_data_valid;
tcp_tx_data <= tcp_data;
U_tcp_tx_demo : process( clk_i )
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
tcp_data_valid <= '0';
tcp_data <= (others=>'0');
tx_state <= T_IDLE;
else
case( tx_state ) is
when T_IDLE =>
tcp_data_valid <= '0';
tcp_data <= (others=>'0');
if tcp_rx_data_valid = '1' and tcp_tx_cts = '1' then
tx_state<= T_START;
tcp_data_valid <= '1';
tcp_data <= tcp_rx_data;
end if ;
when T_START =>
tcp_data <= tcp_rx_data;
tcp_data_valid <= '1';
if tcp_rx_data_valid = '0' then
tx_state <= T_END;
tcp_data_valid <= '0';
tcp_data <= (others=>'0');
end if ;
when T_END =>
tcp_data_valid <= '0';
tcp_data <= (others=>'0');
tx_state <= T_IDLE;
when others =>
tx_state <= T_IDLE;
end case ;
end if ;
end if ;
end process ; -- U_tcp_tx_demo
end behavioral;
top/cute_wr/wr_core_demo/xwr_com5402.ngc 0 → 100644
View file @ d69dece1
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