Main features and components
SoC / FPGA
Type | Component | How many | Other designs | Comments |
---|---|---|---|---|
Zynq Ultrascale+ ZU7 | XCZU7CG-1FFVF1517E | 1 | AFCZ |
Memories
Type | Component | How many | Other designs | Comments |
---|---|---|---|---|
PS DDR4 4GB (8Gb x5) | MT40A512M16LY-075:E | 5 with ECC | ||
PL DDR4 1GB | MT40A512M16LY-075:E | 1 | ||
QSPI 512Mbit | MT25QU512ABB | 2 | 7S, ZCU102 | NOR Flash. Xilinx recommends QSPI32 for flash size larger than 16MB (UG1085 v1.9 p233) |
eMMC 32Gb | IS21ES04G-JCLI | 1 | 7S | 4Gb x 8 |
micro-SD | 1 | To simplify board bring-up, later not mounted since eMMC will be used for filesystem. |
White Rabbit support
See SPEC sch (page 2, 16) and FASEC sch (page 22) for reference
Type | Component | How many | Other designs | Comments |
---|---|---|---|---|
SFP | 1 | RD/TD and control signals to FPGA, no need for SFP SYNCE REFCLK like in SPEC | ||
Link/Act LEDs | 2 | Placed close to SFP cage (probably SMDs on PCB bottom) | ||
DAC 16-bit | AD5662BRMZ-1 | 2 | SPEC, FASEC, AFCK, (WRS) | |
Main OSC | VM53S3-25.000-2.5/-30+75 | 1 | SPEC, FASEC, AFCK, WRS | 25 MHz TCXO |
Helper VCXO 25MHz | KV7050B25.0000C3GD00 | 1 | eRTM 14 | or compatible with KV7050B25.0000C3GD00 |
Helper ext PLL | CDCM61002RHBT | 1 | eRTM14 | Lower jitter than DMTD clock multiplied inside FPGA |
(optional) Helper programmable OSC | SI549 | 1 | Not mounted for CERN | |
Clock generator | Si5341 | ZCU102, AFCZ | See Clocking scheme. Clock distribution for all GTH transceivers (WR, FMC, Backplane); UG576 (p. 30-33) 1 clk reference per Quad is enough; even 1 clk reference for multiple Quands is enough, but this is too constraining | |
WRS | Not enough clock inputs | |||
Startup OSC | FNETHE025 | 1 | WRS | |
I2C EEPROM | 24AA64T-I/MC | 1 | FASEC, HT FMC mezzanines | for WRPC configuration |
I2C Unique ID | 24AA025E48 | 1 | SPEC7 | on the same I2C bus with EEPROM |
1-PPS OUT buffers | SN74LVT125DW | 3 | WRS | see SCB v3.4 (page 3) for reference, pin header with 1-PPS and Abscal Will be used for WR calibration. |
ABSCAL OUT buffers | SN74LVT125DW | 3 | WRS | see SCB v3.4 (page 3) for reference, pin header with 1-PPS and Abscal Will be used for WR calibration. |
Other oscillators / clock generators
Type | Component | How many | Other designs | Comments |
---|---|---|---|---|
PS REF CLK | 48 MHz | 1 | AFCZ | anything between 27MHz-60MHz (DS925, p.32) |
PS RTC crystal | 32.768 kHz | 1 | ZCU102, AFCZ | DS925 p.33 |
Power
Type | Component | How many | Other designs | Comments |
---|---|---|---|---|
Multi-level solution | IRPS5401 | Avnet UltraZed | Infineon PMIC | |
Maxim power solutions for Xilinx |
Miscellaneous
Type | Component | How many | Other designs | Comments |
---|---|---|---|---|
12V aux power connector | 4-pin Molex | 1 | -- | For external powering during first tests |
Xilinx JTAG connector | MOLEX 87832-1420 | 1 | -- | |
Self power-cycle circuit driving backplane PS_ON# | 1 | In normal operation PS_ON# has to be grounded, if driven high or open-circuited PSU shuts off 12V rail | ||
External watchdog chip for PL | LTC2917HMS-B1#PBF | 1 | FASEC | |
Thermometers | LM75A | 3? | ||
12V header connector for FPGA fan | 1 | +12V PWM-driven from FPGA, with tachometer pin | ||
FPGA fan control and monitoring | MAX6639AEE+ | 1 | Provides SMBus interface | |
Mounting holes for FPGA heatsink | AAVID 342947 | 1 | AFCZ, PXIe FMC carrier | 2 holes for mounting |
USB UART | CP2108 | 1 | ZCU106 | connected to PS UART and PL pins for dual-USB-UART |
Aux clock input | MMCX connector | 1 | Not mounted on CERN execution of the board. Required by Sinara. |
LPC FMC slot with 4 MGTs
- 68 user-defined I/Os (34 diff-pairs)
- Voltage translators - Ultrascale has 48 HD I/Os (3.3V max) and 416 HP I/Os (1.8V max)
- I2C SCL and SDA
- Present signal
- 1 LPC MGT
- 3 HPC MGTs (required for FRAS, EN-SMM)
- (optional) more HPC MGTs, to be decided later, depending if it will complicate PCB routing
- FMC clocks connected to dedicated clocking pins of FPGA I/O banks
- Vadj and I/Os fixed at 1.8V
Mechanics
- Board dimensions: 100mm x 220mm
- EDA-03828 to be used as a reference and mechanical template
- Mechanics of the board shall be compliant with section 3.5.1 of CPCI-S.0 specification.
- Mechanics of the front panel shall be compliant with sections 3.5.5, 3.5.7 of CPCI-S.0 specification.
- FMC connector in the front to host a communication mezzanine
- SFP cage in the front for White Rabbit support
- CPCIs backplane connectors P1 - P6 in the back
- ESD strips on both sides of the board, along the bottom edge of the PCB with discharge resistors according to section 3.5.10 of CPCI-S.0 specification.
- The length of ESD strip segment 2 shall be 115mm.
Compact PCI Serial backplane connectors
- 287 FPGA I/Os in total
- 8 MGTs (1 MGT per slot)
- In CERN execution of the board, MGT Tx connected through a capacitor to the backplane connector.
- As Sinara requires an additional LVDS pair, there will be an option to mount a 0R (L-shaped arrangements of pads with the CAP) instead of the capacitor to connect MGT Tx pair from the backplane to regular PL I/Os.
- In CERN execution of the board, MGT Tx connected through a capacitor to the backplane connector.
- I2C SCL and SDA (P1.B2; P1.C2) shall be pulled-up to 3.3V
- PS_ON# (P1.E2) shall be connected to an external watchdog/self-reset circuit for remote power-cycling the whole crate
- RST# (P1.F2), WAKE_IN# (P1.I2) pulled-up to 3.3V
- PRST# (P1.H2) - ESD-protected through 3.3V TVS diode
- PWRBTN# (P1.C3) - ESD-protected through 3.3V TVS diode
- Monitoring I/Os (PS_ON#, PWRFAIL, P_PRES, M_SDA, M_SCL, P_RST, P_IO0-2, F_RST, F_IO0-1) - ESD-protected through 3.3V TVS diode
- P_PRES0, P_PRES1, M_SDA, M_SCL pulled-up to 3.3V
- SATA_SDI, SATA_SDO, SATA_SL, SATA_SCL - shall be pulled-up to 3.3V
Clocking scheme
ZU7 HD (3.3V) and HP (1.8V) I/O planning
I/O connector | I/O name | I/O index | No of pins | ZU7 I/O bank type |
---|---|---|---|---|
CPCIs backplane | I2C | P1.B2, P1.C2 | 2 | HD |
CPCIs backplane | RST# | P1.F2 | 1 | HD |
CPCIs backplane | PWRFAIL# | P1.F2 | 1 | HD |
CPCIs backplane | WAKE_IN# | P1.I2 | 1 | HD |
CPCIs backplane | Monitoring I/Os | P2 rows 7,8 | 11 | HD |
CPCIs backplane | Serial GPIO | P1.G3, P1.H3, P1.J3, P1.K3 | 4 | HD |
CPCIs backplane | PCIe presence detect | P5.A6, P5.C5, P5.D6, P5.F5, P5.G6, P5.I5, P5.J6, P5.L5 | 8 | HD |
CPCIs backplane | PWRBTN# | P1.C3 | 1 | HD |
CPCIs backplane | PRST# | P1.H2 | 1 | HD |
CPCIs backplane | PCIe/USB/SATA/Eth | * | 288 | HP |
FMC connector | User-defined signals | LA[00..33]_P/N | 68 | HP |