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DIOT WIC Gateware
DIOT WIC Gateware
Commit bb956743 authored by Tristan Gingold's avatar Tristan Gingold
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Add a PLL, add more pipelining.

parent 958a4281
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Showing with 164 additions and 88 deletions
hdl/rtl/urv_wic/fip_urv.vhd
View file @ bb956743
......@@ -84,11 +84,15 @@ architecture arch of fip_urv is
signal dm_data_select : std_logic_vector(3 downto 0);
signal dm_load, dm_store, dm_load_done, dm_store_done : std_logic;
signal dm_cycle_in_progress, dm_is_wishbone : std_logic;
signal reg_dm_addr, reg_dm_data_s : std_logic_vector(31 downto 0);
signal reg_dm_data_select : std_logic_vector(3 downto 0);
signal reg_dm_load, reg_dm_store : std_logic;
signal dm_cycle_in_progress, reg_dm_is_wishbone : std_logic;
signal dm_mem_rdata, dm_wb_rdata : std_logic_vector(31 downto 0);
signal dm_wb_write, dm_select_wb : std_logic;
signal dm_data_write : std_logic;
signal reg_dm_data_write : std_logic;
signal dwb_out : t_wishbone_master_out;
begin
......@@ -126,6 +130,22 @@ begin
dbg_mbx_write_i => '0',
dbg_mbx_data_o => open);
process (clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
reg_dm_load <= '0';
reg_dm_store <= '0';
else
reg_dm_load <= dm_load;
reg_dm_store <= dm_store;
reg_dm_addr <= dm_addr;
reg_dm_data_s <= dm_data_s;
reg_dm_data_select <= dm_data_select;
end if;
end if;
end process;
p_rom: process (clk_sys_i)
is
constant IRAM_WSIZE : natural := 2 ** (g_IRAM_LOG_SIZE - 2);
......@@ -138,9 +158,9 @@ begin
end process;
-- 1st MByte of the mem is the IRAM
dm_is_wishbone <= '1' when dm_addr(31 downto 20) /= x"000" else '0';
reg_dm_is_wishbone <= '1' when reg_dm_addr(31 downto 20) /= x"000" else '0';
dm_data_write <= not dm_is_wishbone and dm_store;
reg_dm_data_write <= not reg_dm_is_wishbone and reg_dm_store;
dm_data_l <= dm_wb_rdata when dm_select_wb = '1' else dm_mem_rdata;
p_ram: process (clk_sys_i)
......@@ -149,12 +169,12 @@ begin
variable addr : natural range mem'range;
begin
if rising_edge(clk_sys_i) then
addr := to_integer(unsigned(dm_addr(g_DRAM_LOG_SIZE - 1 downto 2)));
addr := to_integer(unsigned(reg_dm_addr(g_DRAM_LOG_SIZE - 1 downto 2)));
dm_mem_rdata <= mem(addr);
if dm_data_write = '1' then
if reg_dm_data_write = '1' then
for i in 0 to 3 loop
if dm_data_select (i) = '1' then
mem(addr)(8*i + 7 downto 8*i) := dm_data_s(8*i + 7 downto 8*i);
if reg_dm_data_select (i) = '1' then
mem(addr)(8*i + 7 downto 8*i) := reg_dm_data_s(8*i + 7 downto 8*i);
end if;
end loop;
end if;
......@@ -179,13 +199,13 @@ begin
else
if dm_cycle_in_progress = '0' then
if dm_is_wishbone = '0' then
if reg_dm_is_wishbone = '0' then
-- Internal access
if dm_store = '1' then
if reg_dm_store = '1' then
dm_load_done <= '0';
dm_store_done <= '1';
dm_select_wb <= '0';
elsif dm_load = '1' then
elsif reg_dm_load = '1' then
dm_load_done <= '1';
dm_store_done <= '0';
dm_select_wb <= '0';
......@@ -196,14 +216,14 @@ begin
end if;
else
-- Wishbone access
if dm_load = '1' or dm_store = '1' then
if reg_dm_load = '1' or reg_dm_store = '1' then
dwb_out.cyc <= '1';
dwb_out.stb <= '1';
dwb_out.we <= dm_store;
dm_wb_write <= dm_store;
dwb_out.adr <= dm_addr;
dwb_out.dat <= dm_data_s;
dwb_out.sel <= dm_data_select;
dwb_out.we <= reg_dm_store;
dm_wb_write <= reg_dm_store;
dwb_out.adr <= reg_dm_addr;
dwb_out.dat <= reg_dm_data_s;
dwb_out.sel <= reg_dm_data_select;
dm_load_done <= '0';
dm_store_done <= '0';
dm_cycle_in_progress <= '1';
......
hdl/rtl/urv_wic/plc_urv.vhd
View file @ bb956743
......@@ -57,15 +57,19 @@ architecture arch of plc_urv is
signal im_data : std_logic_vector(31 downto 0);
signal im_valid : std_logic;
signal dm_addr, dm_data_s, dm_data_l : std_logic_vector(31 downto 0);
signal dm_data_select : std_logic_vector(3 downto 0);
signal dm_addr, dm_data_s, dm_data_l : std_logic_vector(31 downto 0);
signal dm_data_select : std_logic_vector(3 downto 0);
signal dm_load, dm_store, dm_load_done, dm_store_done : std_logic;
signal dm_cycle_in_progress, dm_is_wishbone : std_logic;
signal reg_dm_addr, reg_dm_data_s : std_logic_vector(31 downto 0);
signal reg_dm_data_select : std_logic_vector(3 downto 0);
signal reg_dm_load, reg_dm_store : std_logic;
signal dm_cycle_in_progress, reg_dm_is_wishbone : std_logic;
signal dm_mem_rdata, dm_wb_rdata : std_logic_vector(31 downto 0);
signal dm_wb_write, dm_select_wb : std_logic;
signal dm_data_write : std_logic;
signal reg_dm_data_write : std_logic;
signal dwb_out : t_wishbone_master_out;
begin
......@@ -103,6 +107,22 @@ begin
dbg_mbx_write_i => '0',
dbg_mbx_data_o => open);
process (clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
reg_dm_load <= '0';
reg_dm_store <= '0';
else
reg_dm_load <= dm_load;
reg_dm_store <= dm_store;
reg_dm_addr <= dm_addr;
reg_dm_data_s <= dm_data_s;
reg_dm_data_select <= dm_data_select;
end if;
end if;
end process;
p_iram: process (clk_sys_i)
is
constant IRAM_WSIZE : natural := 2 ** (g_IRAM_LOG_SIZE - 2);
......@@ -124,9 +144,9 @@ begin
ram_wb_o.stall <= '0';
-- 1st MByte of the mem is the IRAM
dm_is_wishbone <= '1' when dm_addr(31 downto 20) /= x"000" else '0';
reg_dm_is_wishbone <= '1' when reg_dm_addr(31 downto 20) /= x"000" else '0';
dm_data_write <= not dm_is_wishbone and dm_store;
reg_dm_data_write <= not reg_dm_is_wishbone and reg_dm_store;
dm_data_l <= dm_wb_rdata when dm_select_wb = '1' else dm_mem_rdata;
p_ram: process (clk_sys_i)
......@@ -135,12 +155,12 @@ begin
variable addr : natural range mem'range;
begin
if rising_edge(clk_sys_i) then
addr := to_integer(unsigned(dm_addr(g_DRAM_LOG_SIZE - 1 downto 2)));
addr := to_integer(unsigned(reg_dm_addr(g_DRAM_LOG_SIZE - 1 downto 2)));
dm_mem_rdata <= mem(addr);
if dm_data_write = '1' then
if reg_dm_data_write = '1' then
for i in 0 to 3 loop
if dm_data_select (i) = '1' then
mem(addr)(8*i + 7 downto 8*i) := dm_data_s(8*i + 7 downto 8*i);
if reg_dm_data_select (i) = '1' then
mem(addr)(8*i + 7 downto 8*i) := reg_dm_data_s(8*i + 7 downto 8*i);
end if;
end loop;
end if;
......@@ -165,13 +185,13 @@ begin
else
if dm_cycle_in_progress = '0' then
if dm_is_wishbone = '0' then
if reg_dm_is_wishbone = '0' then
-- Internal access
if dm_store = '1' then
if reg_dm_store = '1' then
dm_load_done <= '0';
dm_store_done <= '1';
dm_select_wb <= '0';
elsif dm_load = '1' then
elsif reg_dm_load = '1' then
dm_load_done <= '1';
dm_store_done <= '0';
dm_select_wb <= '0';
......@@ -182,14 +202,14 @@ begin
end if;
else
-- Wishbone access
if dm_load = '1' or dm_store = '1' then
if reg_dm_load = '1' or reg_dm_store = '1' then
dwb_out.cyc <= '1';
dwb_out.stb <= '1';
dwb_out.we <= dm_store;
dm_wb_write <= dm_store;
dwb_out.adr <= dm_addr;
dwb_out.dat <= dm_data_s;
dwb_out.sel <= dm_data_select;
dwb_out.we <= reg_dm_store;
dm_wb_write <= reg_dm_store;
dwb_out.adr <= reg_dm_addr;
dwb_out.dat <= reg_dm_data_s;
dwb_out.sel <= reg_dm_data_select;
dm_load_done <= '0';
dm_store_done <= '0';
dm_cycle_in_progress <= '1';
......
hdl/syn/diot_urv_demo/diot_wic_demo.sdc
View file @ bb956743
......@@ -2,7 +2,9 @@
# Clocks
create_clock -name {diot_wic_top|clk_25m_i} -period 40.000000 -waveform {0.000000 20.000000} clk_25m_i
create_clock -name {clk_25m_i} -period 40.000000 -waveform {0.000000 20.000000} clk_25m_i
create_generated_clock -name {main_clk} -multiply_by 8 -divide_by 6 -source clk_25m_i inst_pll/Core:GLA
create_generated_clock -name {wb_clk_2} -multiply_by 8 -divide_by 8 -source clk_25m_i inst_pll/Core:GLB
# False Paths Between Clocks
......
hdl/top/diot_urv_demo/diot_urv_top.vhd
View file @ bb956743
......@@ -31,6 +31,8 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
library proasic3e;
use proasic3e.all;
entity diot_urv_top is
port (
......@@ -129,9 +131,8 @@ architecture rtl of diot_urv_top is
signal por_n_buf : std_logic;
signal por_n_d : std_logic_vector(1 downto 0);
signal leds : std_logic_vector(5 downto 0);
subtype t_rst_cnt is natural range 0 to 15;
signal rst_cnt : t_rst_cnt;
signal rst_n : std_logic;
signal arst : std_logic;
signal plc_rst_n : std_logic;
......@@ -171,9 +172,18 @@ architecture rtl of diot_urv_top is
signal mbox_in_rd : std_logic;
signal mbox_in_rdy : std_logic;
signal fip_cyc : std_logic;
signal fip_stb : std_logic;
signal fip_we : std_logic;
signal fip_ack : std_logic;
signal fip_adr : std_logic_vector (9 downto 0);
signal fip_dato : std_logic_vector (7 downto 0);
signal fip_dati : std_logic_vector (7 downto 0);
signal clk_25m_in : std_logic;
signal clk : std_logic;
signal pll_lock : std_logic;
signal clk_2 : std_logic;
begin
inst_clk_pad : PLLINT
port map (
......@@ -186,7 +196,8 @@ begin
powerdown => '1',
clka => clk_25m_in,
lock => pll_lock,
gla => clk
gla => clk,
glb => clk_2
);
-------------------------------------------------------------------------------
......@@ -213,18 +224,18 @@ begin
clr => por_n_buf,
q => por_n_d(1));
process(clk)
begin
if rising_edge(clk) then
if (por_n_d(1) = '0' or button_i = '1') then
rst_cnt <= t_rst_cnt'high;
elsif rst_cnt /= 0 then
rst_cnt <= rst_cnt - 1;
end if;
end if;
end process;
rst_n <= '1' when rst_cnt = 0 and pll_lock = '1' else
'0';
arst <= not por_n_d(1) or not pll_lock or button_i;
inst_reset: entity work.gc_reset_multi_aasd
generic map (
g_CLOCKS => 1,
g_RST_LEN => 16
)
port map (
arst_i => arst,
clks_i (0) => clk,
rst_n_o (0) => rst_n
);
-------------------------------------------------------------------------------
-- Synchronizers for RDY signals (40MHz clock domain in nanoFIP
......@@ -350,26 +361,48 @@ begin
boards_pins_5_i (31 downto 16) => slots_relays(5)(15 downto 0),
boards_pins_6_i => x"00_00_00_00",
boards_pins_7_i => x"00_00_00_00",
fip_reg_i.dat (7 downto 0) => dat_i,
fip_reg_i.dat (7 downto 0) => fip_dati,
fip_reg_i.dat (31 downto 8) => x"00_00_00",
fip_reg_i.ack => ack_i,
fip_reg_i.ack => fip_ack,
fip_reg_i.err => '0',
fip_reg_i.rty => '0',
fip_reg_i.stall => '0',
fip_reg_o.dat (7 downto 0) => dat_o,
fip_reg_o.dat (7 downto 0) => fip_dato,
fip_reg_o.dat (31 downto 8) => unc_dat,
fip_reg_o.adr (1 downto 0) => unc_adr (1 downto 0),
fip_reg_o.adr (11 downto 2) => adr_o,
fip_reg_o.adr (11 downto 2) => fip_adr,
fip_reg_o.adr (31 downto 12) => unc_adr (31 downto 12),
fip_reg_o.cyc => cyc_o,
fip_reg_o.stb => stb_o,
fip_reg_o.cyc => fip_cyc,
fip_reg_o.stb => fip_stb,
fip_reg_o.sel => sel,
fip_reg_o.we => we_o,
fip_reg_o.we => fip_we,
plc_mem_i => wb_mem_out,
plc_mem_o => wb_mem_in
);
wclk_o <= clk;
-- Simple speed adapter for WB with nanofip.
process (clk_2)
begin
if rising_edge(clk_2) then
if rst_n = '0' then
cyc_o <= '0';
stb_o <= '0';
we_o <= '0';
fip_ack <= '0';
else
cyc_o <= fip_cyc;
stb_o <= fip_stb;
we_o <= fip_we;
dat_o <= fip_dato;
adr_o <= fip_adr;
fip_ack <= ack_i;
fip_dati <= dat_i;
end if;
end if;
end process;
wclk_o <= clk_2;
rst_o <= not rst_n;
nostat_o <= '1';
rstin_o <= rst_n;
......
hdl/top/diot_urv_demo/pll_25_50.vhd
View file @ bb956743
......@@ -10,7 +10,8 @@ entity PLL_25_50 is
port( POWERDOWN : in std_logic;
CLKA : in std_logic;
LOCK : out std_logic;
GLA : out std_logic
GLA : out std_logic;
GLB : out std_logic
);
end PLL_25_50;
......@@ -124,37 +125,37 @@ begin
\VCC\ <= VCC_power_net1;
Core : PLL
generic map(VCOFREQUENCY => 50.000)
generic map(VCOFREQUENCY => 198.077)
port map(CLKA => CLKA,
EXTFB => \GND\,
POWERDOWN => POWERDOWN,
GLA => GLA,
LOCK => LOCK,
GLB => OPEN,
GLB => GLB,
YB => OPEN,
GLC => OPEN,
YC => OPEN,
OADIV0 => \GND\,
OADIV1 => \GND\,
OADIV2 => \GND\,
OADIV0 => \VCC\, -- Primary output divider. val = oadiv + 1
OADIV1 => \GND\, -- / 6
OADIV2 => \VCC\,
OADIV3 => \GND\,
OADIV4 => \GND\,
OAMUX0 => \GND\,
OAMUX0 => \GND\, -- GLA output select: 0 shift
OAMUX1 => \GND\,
OAMUX2 => \VCC\,
DLYGLA0 => \GND\,
DLYGLA0 => \GND\, -- Delay: 225ps
DLYGLA1 => \GND\,
DLYGLA2 => \GND\,
DLYGLA3 => \GND\,
DLYGLA4 => \GND\,
OBDIV0 => \GND\,
OBDIV1 => \GND\,
OBDIV2 => \GND\,
OBDIV0 => \VCC\, -- Secondary 1 output divider
OBDIV1 => \VCC\, -- / 8
OBDIV2 => \VCC\,
OBDIV3 => \GND\,
OBDIV4 => \GND\,
OBMUX0 => \GND\,
OBMUX1 => \GND\,
OBMUX0 => \GND\, -- GLB output select: 0 shift
OBMUX1 => \VCC\,
OBMUX2 => \GND\,
DLYYB0 => \GND\,
DLYYB1 => \GND\,
......@@ -166,12 +167,12 @@ begin
DLYGLB2 => \GND\,
DLYGLB3 => \GND\,
DLYGLB4 => \GND\,
OCDIV0 => \GND\,
OCDIV0 => \GND\, -- Secondary 2 output divider
OCDIV1 => \GND\,
OCDIV2 => \GND\,
OCDIV3 => \GND\,
OCDIV4 => \GND\,
OCMUX0 => \GND\,
OCMUX0 => \GND\, -- GLC output select
OCMUX1 => \GND\,
OCMUX2 => \GND\,
DLYYC0 => \GND\,
......@@ -184,22 +185,22 @@ begin
DLYGLC2 => \GND\,
DLYGLC3 => \GND\,
DLYGLC4 => \GND\,
FINDIV0 => \GND\,
FINDIV1 => \GND\,
FINDIV0 => \GND\, -- Input divider. val = findiv + 1
FINDIV1 => \GND\, -- / 13
FINDIV2 => \VCC\,
FINDIV3 => \GND\,
FINDIV3 => \VCC\,
FINDIV4 => \GND\,
FINDIV5 => \GND\,
FINDIV6 => \GND\,
FBDIV0 => \VCC\,
FBDIV1 => \GND\,
FBDIV2 => \GND\,
FBDIV3 => \VCC\,
FBDIV0 => \GND\, -- Feedback divider. val = fbdiv + 1
FBDIV1 => \VCC\, -- / 102
FBDIV2 => \VCC\,
FBDIV3 => \GND\,
FBDIV4 => \GND\,
FBDIV5 => \GND\,
FBDIV6 => \GND\,
FBDLY0 => \GND\,
FBDLY1 => \GND\,
FBDIV5 => \VCC\,
FBDIV6 => \VCC\,
FBDLY0 => \GND\, -- Feedback delay
FBDLY1 => \GND\, -- 600ps
FBDLY2 => \GND\,
FBDLY3 => \GND\,
FBDLY4 => \GND\,
......@@ -207,8 +208,8 @@ begin
FBSEL1 => \GND\,
XDLYSEL => \GND\,
VCOSEL0 => \GND\,
VCOSEL1 => \VCC\,
VCOSEL2 => \GND\);
VCOSEL1 => \VCC\, -- VCO: 135-350Mhz
VCOSEL2 => \VCC\);
GND_power_inst1 : GND
port map( Y => GND_power_net1);
......
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