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EtherBone Core
Commit 3ac7cefc authored by Mathias Kreider's avatar Mathias Kreider
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fix for cycle address bug

parent 08b55da9
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Showing with 30 additions and 8 deletions
hdl/eb_master_core/eb_master_tb.vhd
View file @ 3ac7cefc
......@@ -14,6 +14,20 @@ END test_tb;
ARCHITECTURE behavior OF test_tb IS
component eb_master_top is
generic(g_adr_bits_hi : natural := 8;
g_mtu : natural := 32);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out
);
end component;
......@@ -200,11 +214,19 @@ slave_stall <= master_i.stall;
wb_wr(c_OPA_HI, x"00000000", '1');
wb_wr(c_EB_OPT, x"00000000", '0');
wb_wr(x"00300000", x"DEADBEE0", '0');
wb_wr(x"00300004", x"DEADBEE1", '0');
wb_wr(x"00380008", x"DEADBEE2", '0');
wb_wr(x"0030000C", x"DEADBEE3", '0');
wb_wr(x"00300010", x"DEADBEE4", '0');
wb_wr(x"00300000", x"DEADBEE0", '1');
master_o.adr <= (others => '0');
wait for clk_period*1;
wb_wr(x"00300004", x"DEADBEE1", '1');
master_o.adr <= (others => '0');
wait for clk_period*1;
wb_wr(x"00380008", x"DEADBEE2", '1');
master_o.adr <= (others => '0');
wait for clk_period*1;
wb_wr(x"0038000C", x"DEADBEE3", '1');
master_o.adr <= (others => '0');
wait for clk_period*1;
wb_wr(x"00380010", x"DEADBEE4", '1');
wait for clk_period*500;
wb_wr(c_FLUSH, x"00000001", '0');
wait;
......
hdl/eb_master_core/eb_master_top.vhd
View file @ 3ac7cefc
......@@ -140,7 +140,6 @@ begin
);
s_slave_i.stb <= slave_i.stb;
s_slave_i.dat <= slave_i.dat;
s_slave_i.sel <= slave_i.sel;
......@@ -156,10 +155,11 @@ begin
-- | Write |
-- |_________|
s_tx_send_now <= '1' when slave_i.adr(c_dat_bit) = '0' and slave_i.adr(7 downto 0) = x"04"
s_tx_send_now <= '1' when slave_i.adr(c_dat_bit) = '0' and slave_i.stb = '1' and slave_i.adr(7 downto 0) = x"04"
else '0';
s_slave_i.cyc <= slave_i.cyc and (slave_i.adr(c_dat_bit) or s_tx_send_now);
s_slave_i.cyc <= slave_i.cyc or s_tx_send_now;
s_slave_i.stb <= slave_i.stb and slave_i.adr(c_dat_bit);
s_slave_i.we <= slave_i.adr(c_rw_bit);
s_slave_i.adr <= s_adr_hi(s_adr_hi'left downto s_adr_hi'length-g_adr_bits_hi) & slave_i.adr(slave_i.adr'left-g_adr_bits_hi downto 0);
......
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