ebm: v1.2 hardware tested. new flow control, added bit of documentation in top

59370989 · Mathias Kreider · 01af0122 · 59370989 · 59370989 · 59370989
Commit 59370989 authored Jun 04, 2014 by Mathias Kreider
9 changed files
--- a/hdl/eb_master_core/eb_commit_len_fifo.vhd
+++ b/hdl/eb_master_core/eb_commit_len_fifo.vhd
@@ -131,6 +131,7 @@ begin
        w_idx     <= w_idx1 +1;
      elsif w_abort_i = '1' then
        r_len <= (others => '0');
+        r_cnt <= (others => '0');
        w_idx <= e_idx + 1;
      else
        w_idx <= w_idx1;    

--- a/hdl/eb_master_core/eb_framer.vhd
+++ b/hdl/eb_master_core/eb_framer.vhd
--- a/hdl/eb_master_core/eb_master_eth_tx.vhd
+++ b/hdl/eb_master_core/eb_master_eth_tx.vhd
@@ -25,6 +25,7 @@ entity eb_master_eth_tx is
    port_i       : in  std_logic_vector(15 downto 0);
    skip_stb_i   : in  std_logic;
    skip_stall_o : out std_logic;
+    --fifo_cnt_o   : out std_logic(f_ceil_log2( (g_mtu+c_eth_len)/2 ) downto 0); 
    my_mac_i     : in  std_logic_vector(47 downto 0);
    my_ip_i      : in  std_logic_vector(31 downto 0);
    my_port_i    : in  std_logic_vector(15 downto 0));
@@ -281,6 +282,7 @@ begin
          
        
        when S_SKIP =>
+          r_hdr_stb <= '0';
          r_state <= S_ETHERNET;
        
        when S_PUSH =>
@@ -294,6 +296,11 @@ begin
          end if;
          
      end case;
+      
+      --get us out if nothing else helps
+      if skip_stb_i = '1' then
+         r_state <= S_SKIP;
+      end if;
    end if;
  end process;


--- a/hdl/eb_master_core/eb_master_tb.vhd
+++ b/hdl/eb_master_core/eb_master_tb.vhd
--- a/hdl/eb_master_core/eb_master_top.vhd
+++ b/hdl/eb_master_core/eb_master_top.vhd
--- a/hdl/eb_master_core/eb_master_wb_if.vhd
+++ b/hdl/eb_master_core/eb_master_wb_if.vhd
--- a/hdl/eb_master_core/eb_record_gen.vhd
+++ b/hdl/eb_master_core/eb_record_gen.vhd
--- a/hdl/eb_slave_core/eb_internals_pkg.vhd
+++ b/hdl/eb_slave_core/eb_internals_pkg.vhd
@@ -298,23 +298,26 @@ package eb_internals_pkg is

 
   component eb_master_wb_if is
-   generic(g_adr_bits_hi : natural := 8);
-   port(
+    generic(g_adr_bits_hi : natural;
+      g_mtu         : natural);
+    port(
      clk_i       : in  std_logic;
      rst_n_i     : in  std_logic;
-
+      
+      slave_i     : in  t_wishbone_slave_in;
+      slave_o     : out t_wishbone_slave_out;
+      
+      byte_cnt_i  : in std_logic_vector(15 downto 0);
+      error_i     : in std_logic_vector(0 downto 0);
+      
+      
      clear_o     : out std_logic;
      flush_o     : out std_logic;
-
-      slave_i     : in  t_wishbone_slave_in;
-      slave_dat_o : out t_wishbone_data;
-      slave_ack_o : out  std_logic;
-      slave_err_o : out  std_logic;
-
+      
      my_mac_o    : out std_logic_vector(47 downto 0);
      my_ip_o     : out std_logic_vector(31 downto 0);
      my_port_o   : out std_logic_vector(15 downto 0);
-
+      
      his_mac_o   : out std_logic_vector(47 downto 0); 
      his_ip_o    : out std_logic_vector(31 downto 0);
      his_port_o  : out std_logic_vector(15 downto 0); 
@@ -327,19 +330,23 @@ package eb_internals_pkg is
  
   component eb_framer is
   port(
-      clk_i           : in  std_logic;            
-      rst_n_i         : in  std_logic;           
+    clk_i           : in   std_logic;            -- WB Clock
+    rst_n_i         : in   std_logic;            -- async reset

-      slave_i         : in  t_wishbone_slave_in;  
-      slave_stall_o   : out std_logic;       
-      tx_send_now_i   : in  std_logic;
-
-      master_o        : out t_wishbone_master_out;
-      master_i        : in  t_wishbone_master_in; 
-      tx_flush_o      : out std_logic;
-      max_ops_i       : in unsigned(15 downto 0);
-      length_i        : in unsigned(15 downto 0); 
-      cfg_rec_hdr_i   : in t_rec_hdr);   
+    slave_i         : in   t_wishbone_slave_in;  -- WB op. -> not WB compliant, but the record format is convenient
+    slave_o         : out  t_wishbone_slave_out;  -- flow control    
+    master_o        : out  t_wishbone_master_out;
+    master_i        : in   t_wishbone_master_in; 
+    
+    byte_cnt_o      : out  std_logic_vector(15 downto 0);
+    ovf_o           : out  std_logic;
+       
+    tx_send_now_i   : in   std_logic;
+    tx_flush_o      : out  std_logic; 
+    max_ops_i       : in   unsigned(15 downto 0);
+    length_i        : in   unsigned(15 downto 0); 
+    cfg_rec_hdr_i   : in   t_rec_hdr -- EB cfg information, eg read from cfg space etc
+   );    
   end component;
  
   component eb_record_gen is
@@ -349,13 +356,14 @@ package eb_internals_pkg is

      slave_i         : in  t_wishbone_slave_in;  
      slave_stall_o   : out std_logic;              
-
+      slave_ack_o     : out std_logic;
+      
      rec_valid_o     : out std_logic;            
      rec_hdr_o       : out t_rec_hdr;          
      rec_adr_rd_o    : out t_wishbone_data; 
      rec_adr_wr_o    : out t_wishbone_address; 
      rec_ack_i       : in std_logic;             
-      max_ops_i       : in unsigned(15 downto 0); 
+      byte_cnt_o    : out unsigned(15 downto 0); 
      cfg_rec_hdr_i   : in t_rec_hdr);   
   end component ;
  

--- a/hdl/eb_slave_core/etherbone_pkg.vhd
+++ b/hdl/eb_slave_core/etherbone_pkg.vhd
@@ -35,9 +35,9 @@ package etherbone_pkg is
    product => (
    vendor_id     => x"0000000000000651", -- GSI
    device_id     => x"00000815",
-    version       => x"00000001",
-    date          => x"20130615",
-    name          => "ETHERBONE_MASTER   ")));
+    version       => x"00000002",
+    date          => x"20140615",
+    name          => "Etherbone_Master   ")));
  
  component eb_raw_slave is
    generic(
@@ -139,6 +139,9 @@ port(
  slave_i       : in  t_wishbone_slave_in;
  slave_o       : out t_wishbone_slave_out;
  
+  framer_in   : out t_wishbone_slave_in;
+  framer_out  : out t_wishbone_slave_out;
+  
  src_i         : in  t_wrf_source_in;
  src_o         : out t_wrf_source_out
 );