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E
EtherBone Core
Commit 79a60811 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: Eradicate INT from wishbone records and peripheral ports.

parent 84894459
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Showing with 2 additions and 5 deletions
hdl/eb_slave_core/eb_cfg_fifo.vhd
View file @ 79a60811
......@@ -6,7 +6,7 @@
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-04-08
-- Last update: 2013-04-08
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -84,7 +84,6 @@ architecture rtl of eb_cfg_fifo is
begin
cfg_o.int <= '0';
cfg_o.err <= '0';
cfg_o.rty <= '0';
cfg_o.stall <= '0';
......
hdl/eb_slave_core/eb_eth_tx.vhd
View file @ 79a60811
......@@ -135,7 +135,6 @@ begin
r_dat_o(15 downto 0) => s_tx_dat);
slave_o.ack <= r_ack;
slave_o.int <= '0';
slave_o.rty <= '0';
slave_o.err <= '0';
slave_o.stall <= s_stall;
......
hdl/eb_slave_core/eb_slave_top.vhd
View file @ 79a60811
......@@ -6,7 +6,7 @@
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-04-08
-- Last update: 2013-04-08
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -92,7 +92,6 @@ begin
EB_RX_o.ack <= EB_RX_i.cyc and EB_RX_i.stb and not rx_stall;
EB_RX_o.err <= '0';
EB_RX_o.rty <= '0';
EB_RX_o.int <= '0';
EB_RX_o.stall <= rx_stall;
EB_RX_o.dat <= (others => '0');
......
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