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EtherBone Core
Commit b7f02ca3 authored by Mathias Kreider's avatar Mathias Kreider
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ebm: finally squashed record split bug

parent beb44546
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Showing with 316 additions and 216 deletions
hdl/eb_master_core/eb_framer.vhd
View file @ b7f02ca3
......@@ -133,8 +133,8 @@ variable ret : std_logic;
begin
ret := '0';
for I in 0 to slv_in'left loop
ret := ret or slv_in(I);
end loop;
ret := ret or slv_in(I);
end loop;
return ret;
end function or_all;
......@@ -157,6 +157,7 @@ begin
s_recgen_slave_i.adr <= adr;
s_recgen_slave_i.dat <= dat;
rgen: eb_record_gen
PORT MAP (
......
hdl/eb_master_core/eb_master_tb.vhd
View file @ b7f02ca3
......@@ -38,24 +38,24 @@ end component;
constant c_dummy_master_out : t_wishbone_master_out := c_dummy_slave_in;
--declare inputs and initialize them
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
signal master_o : t_wishbone_master_out;
signal master_i : t_wishbone_master_in;
signal src_i : t_wrf_source_in;
signal src_o : t_wrf_source_out;
signal slave_stall : std_logic;
signal cfg_rec_hdr : t_rec_hdr;
signal cfg_mtu : natural;
signal count : natural;
signal data : std_logic_vector(c_wishbone_data_width-1 downto 0);
signal en : std_logic;
signal eop : std_logic;
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
signal master_o : t_wishbone_master_out;
signal master_i : t_wishbone_master_in;
signal src_i : t_wrf_source_in;
signal src_o : t_wrf_source_out;
signal slave_stall : std_logic;
signal cfg_rec_hdr : t_rec_hdr;
signal cfg_mtu : natural;
signal count : natural;
signal data : std_logic_vector(c_wishbone_data_width-1 downto 0);
signal en : std_logic;
signal eop : std_logic;
constant c_RESET : unsigned(31 downto 0) := x"86000000";
constant c_FLUSH : unsigned(31 downto 0) := c_RESET +4; --wo 04
constant c_STATUS : unsigned(31 downto 0) := c_FLUSH +4; --rw 08
......@@ -77,7 +77,7 @@ constant c_EB_OPT : unsigned(31 downto 0) := c_ROA_BASE +4; --rw 40
constant c_adr_hi_bits : natural := 10;
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
......@@ -87,16 +87,14 @@ uut: eb_master_top
GENERIC MAP(g_adr_bits_hi => c_adr_hi_bits,
g_mtu => 32)
PORT MAP (
clk_i => clk,
rst_n_i => rst_n,
clk_i => clk,
rst_n_i => rst_n,
slave_i => master_o,
slave_o => master_i,
slave_i => master_o,
slave_o => master_i,
src_o => src_o,
src_i => src_i
);
src_i => src_i);
slave_stall <= master_i.stall;
......@@ -192,11 +190,11 @@ slave_stall <= master_i.stall;
rst_n <= '0';
eop <= '0';
src_i <= c_dummy_src_in;
master_o <= c_dummy_master_out;
master_o.sel <= x"f";
cfg_rec_hdr <= c_rec_init;
master_o <= c_dummy_master_out;
master_o.sel <= x"f";
cfg_rec_hdr <= c_rec_init;
wait for clk_period*2;
rst_n <= '1';
wait until rising_edge(clk);
......@@ -215,27 +213,110 @@ slave_stall <= master_i.stall;
wb_wr(c_EB_OPT, x"00000000", '0');
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C000E0", x"10000000", '1');
wb_wr(x"86C00000", x"10000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*1;
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C000E4", x"20000000", '1');
wb_wr(x"86C00000", x"20000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*1;
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C000E8", x"30000000", '1');
wb_wr(x"86C00000", x"30000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*1;
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"40000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"50000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"60000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"70000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"80000000", '1');
wait for clk_period*10;
wb_wr(c_FLUSH, x"00000001", '0');
wait for clk_period*10;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"10000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C000EC", x"40000000", '1');
wb_wr(x"86C00000", x"20000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*1;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C000F0", x"50000000", '1');
wb_wr(x"86C00000", x"30000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*30;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"40000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*25;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"50000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*7;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"60000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*8;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"70000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*5;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"80000000", '1');
wait for clk_period*10;
wb_wr(c_FLUSH, x"00000001", '0');
wait for clk_period*10;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"10000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"20000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"30000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"40000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"50000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"60000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"70000000", '1');
master_o.adr <= (others => '0');
wait for clk_period*15;
wb_wr(c_OPA_HI, x"10000000", '1');
wb_wr(x"86C00000", x"80000000", '1');
wait for clk_period*10;
wb_wr(c_FLUSH, x"00000001", '1');
wait;
wb_wr(c_FLUSH, x"00000001", '0');
wait for clk_period*10;
end process;
END;
hdl/eb_master_core/eb_master_top.vhd
View file @ b7f02ca3
......@@ -166,18 +166,17 @@ begin
framer: eb_framer
PORT MAP (
clk_i => clk_i,
rst_n_i => s_rst_n,
slave_i => s_slave_i,
slave_stall_o => s_stall,
tx_send_now_i => s_tx_send_now,
clk_i => clk_i,
rst_n_i => s_rst_n,
slave_i => s_slave_i,
slave_stall_o => s_stall,
tx_send_now_i => s_tx_send_now,
master_o => s_framer2narrow,
master_i => s_narrow2framer,
tx_flush_o => s_tx_flush,
max_ops_i => s_max_ops,
length_i => s_length,
cfg_rec_hdr_i => s_cfg_rec_hdr
);
cfg_rec_hdr_i => s_cfg_rec_hdr);
......@@ -195,8 +194,6 @@ narrow : eb_stream_narrow
master_i => s_tx2narrow,
master_o => s_narrow2tx);
tx : eb_eth_tx
generic map(
g_mtu => 1500)
......@@ -222,9 +219,9 @@ narrow : eb_stream_narrow
p_main : process (clk_i, rst_n_i) is
begin
if rst_n_i = '0' then
if rst_n_i = '0' then
elsif rising_edge(clk_i) then
elsif rising_edge(clk_i) then
end if;
......
hdl/eb_master_core/eb_master_wb_if.vhd
View file @ b7f02ca3
......@@ -63,7 +63,6 @@ port(
end eb_master_wb_if;
architecture rtl of eb_master_wb_if is
constant c_ctrl_reg_spc_width : natural := 5; --fix me: need log2 function
......@@ -153,20 +152,20 @@ begin
end procedure rd;
begin
if rising_edge(clk_i) then
if rising_edge(clk_i) then
if rst_n_i = '0' then
slave_dat_o <= (others => '0');
r_rst_n <= '0';
--set everything except MTU to zero
for I in c_STATUS to c_PAC_LEN-1 loop
r_ctrl(I) <= (others => '0');
end loop;
r_ctrl(c_PAC_LEN) <= t_wishbone_data(to_unsigned(512, 32));
for I in c_PAC_LEN+1 to c_LAST loop
r_ctrl(I) <= (others => '0');
end loop;
else
slave_dat_o <= (others => '0');
r_rst_n <= '0';
--set everything except MTU to zero
for I in c_STATUS to c_PAC_LEN-1 loop
r_ctrl(I) <= (others => '0');
end loop;
r_ctrl(c_PAC_LEN) <= t_wishbone_data(to_unsigned(512, 32));
for I in c_PAC_LEN+1 to c_LAST loop
r_ctrl(I) <= (others => '0');
end loop;
else
r_ack <= '0';
r_err <= '0';
r_rst_n <= '1';
......@@ -196,7 +195,7 @@ begin
when c_OPS_MAX => wr(v_adr);
when c_EB_OPT => wr(v_adr, x"0000FFFF");
when others => report "write to adr in cmd space not mapped";
r_err <= '1';
r_err <= '1';
end case;
else
......@@ -217,7 +216,7 @@ begin
when c_ROA_BASE => rd(v_adr);
when c_EB_OPT => rd(v_adr);
when others => report "read to adr in cmd space not mapped";
r_err <= '1';
r_err <= '1';
end case;
end if;
--STAGING AREA
......@@ -231,7 +230,6 @@ begin
--end if;
r_ack <= '1';
else
r_err <= '1'; -- a read on the framer ?! That's forbidden, give the user a scolding
end if;
end if;
......
hdl/eb_master_core/eb_record_gen.vhd
View file @ b7f02ca3
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