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Commit 9a0e5a45 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Add ZedBoard board definition file

parent 196268f2
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hdl/modules/AvnetBoards/ZedBoard/1.1/board_part.xml 0 → 100755
View file @ 9a0e5a45
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<board_part board_name="zed" board_revision="d" board_part="part0" schema_version="1.0" vendor="em.avnet.com" version="1.1">
<part_info part_name="xc7z020clg484-1" jtag_position="1" silicon_version="1.0" />
<board_info description="ZedBoard Zynq Evaluation and Development Kit" display_name="ZedBoard Zynq Evaluation and Development Kit" url="http://www.zedboard.org"/>
<interfaces>
<interface mode="master" name="btns_5bits" type="xilinx.com:interface:gpio_rtl:1.0">
<port_maps>
<port_map logical_port="TRI_I" physical_port="btns_5bits_tri_i"/>
</port_maps>
</interface>
<interface mode="master" name="leds_8bits" type="xilinx.com:interface:gpio_rtl:1.0">
<port_maps>
<port_map logical_port="TRI_O" physical_port="leds_8bits_tri_o"/>
</port_maps>
</interface>
<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0">
<preset_file name="ps7.tcl"/>
</interface>
<interface mode="master" name="sws_8bits" type="xilinx.com:interface:gpio_rtl:1.0">
<port_maps>
<port_map logical_port="TRI_I" physical_port="sws_8bits_tri_i"/>
</port_maps>
</interface>
<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0">
<port_maps>
<port_map logical_port="CLK" physical_port="sys_clk"/>
</port_maps>
<parameters>
<parameter name="frequency" value="100000000"/>
</parameters>
</interface>
</interfaces>
<ports>
<port dir="in" left="4" name="btns_5bits_tri_i" right="0">
<pins>
<pin index="0" iostandard="LVCMOS25" loc="P16"/>
<pin index="1" iostandard="LVCMOS25" loc="R16"/>
<pin index="2" iostandard="LVCMOS25" loc="N15"/>
<pin index="3" iostandard="LVCMOS25" loc="R18"/>
<pin index="4" iostandard="LVCMOS25" loc="T18"/>
</pins>
</port>
<port dir="out" left="7" name="leds_8bits_tri_o" right="0">
<pins>
<pin index="0" iostandard="LVCMOS33" loc="T22"/>
<pin index="1" iostandard="LVCMOS33" loc="T21"/>
<pin index="2" iostandard="LVCMOS33" loc="U22"/>
<pin index="3" iostandard="LVCMOS33" loc="U21"/>
<pin index="4" iostandard="LVCMOS33" loc="V22"/>
<pin index="5" iostandard="LVCMOS33" loc="W22"/>
<pin index="6" iostandard="LVCMOS33" loc="U19"/>
<pin index="7" iostandard="LVCMOS33" loc="U14"/>
</pins>
</port>
<port dir="in" left="7" name="sws_8bits_tri_i" right="0">
<pins>
<pin index="0" iostandard="LVCMOS25" loc="F22"/>
<pin index="1" iostandard="LVCMOS25" loc="G22"/>
<pin index="2" iostandard="LVCMOS25" loc="H22"/>
<pin index="3" iostandard="LVCMOS25" loc="F21"/>
<pin index="4" iostandard="LVCMOS25" loc="H19"/>
<pin index="5" iostandard="LVCMOS25" loc="H18"/>
<pin index="6" iostandard="LVCMOS25" loc="H17"/>
<pin index="7" iostandard="LVCMOS25" loc="M15"/>
</pins>
</port>
<port dir="in" name="sys_clk">
<pins>
<pin iostandard="LVCMOS33" loc="Y9"/>
</pins>
</port>
</ports>
</board_part>
hdl/modules/AvnetBoards/ZedBoard/1.1/ps7.tcl 0 → 100755
View file @ 9a0e5a45
proc apply_ps7_board_setting { ps7_ip } {
set_property CONFIG.preset {ZedBoard} [get_bd_cells $ps7_ip]
}
######## ZedBoard board preset settings ########
#set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD0_GRP_CD_ENABLE {1} CONFIG.PCW_SD0_GRP_WP_ENABLE {1} CONFIG.PCW_SD0_GRP_POW_ENABLE {0} CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} CONFIG.PCW_SD0_GRP_WP_IO {MIO 46} CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} CONFIG.PCW_TTC0_TTC0_IO {EMIO} CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_MIO_0_SLEW {slow} CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_0_PULLUP {disabled} CONFIG.PCW_MIO_1_SLEW {fast} CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_1_PULLUP {disabled} CONFIG.PCW_MIO_2_SLEW {fast} CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_2_PULLUP {disabled} CONFIG.PCW_MIO_3_SLEW {fast} CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_3_PULLUP {disabled} CONFIG.PCW_MIO_4_SLEW {fast} CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_4_PULLUP {disabled} CONFIG.PCW_MIO_5_SLEW {fast} CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_5_PULLUP {disabled} CONFIG.PCW_MIO_6_SLEW {fast} CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_6_PULLUP {disabled} CONFIG.PCW_MIO_7_SLEW {slow} CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_7_PULLUP {disabled} CONFIG.PCW_MIO_8_SLEW {fast} CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_8_PULLUP {disabled} CONFIG.PCW_MIO_9_SLEW {slow} CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_9_PULLUP {disabled} CONFIG.PCW_MIO_10_SLEW {slow} CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_10_PULLUP {disabled} CONFIG.PCW_MIO_11_SLEW {slow} CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_11_PULLUP {disabled} CONFIG.PCW_MIO_12_SLEW {slow} CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_12_PULLUP {disabled} CONFIG.PCW_MIO_13_SLEW {slow} CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_13_PULLUP {disabled} CONFIG.PCW_MIO_14_SLEW {slow} CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_14_PULLUP {disabled} CONFIG.PCW_MIO_15_SLEW {slow} CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} CONFIG.PCW_MIO_15_PULLUP {disabled} CONFIG.PCW_MIO_16_SLEW {fast} CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_16_PULLUP {disabled} CONFIG.PCW_MIO_17_SLEW {fast} CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_17_PULLUP {disabled} CONFIG.PCW_MIO_18_SLEW {fast} CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_18_PULLUP {disabled} CONFIG.PCW_MIO_19_SLEW {fast} CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_19_PULLUP {disabled} CONFIG.PCW_MIO_20_SLEW {fast} CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_20_PULLUP {disabled} CONFIG.PCW_MIO_21_SLEW {fast} CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_21_PULLUP {disabled} CONFIG.PCW_MIO_22_SLEW {fast} CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_22_PULLUP {disabled} CONFIG.PCW_MIO_23_SLEW {fast} CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_23_PULLUP {disabled} CONFIG.PCW_MIO_24_SLEW {fast} CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_24_PULLUP {disabled} CONFIG.PCW_MIO_25_SLEW {fast} CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_25_PULLUP {disabled} CONFIG.PCW_MIO_26_SLEW {fast} CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_26_PULLUP {disabled} CONFIG.PCW_MIO_27_SLEW {fast} CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_27_PULLUP {disabled} CONFIG.PCW_MIO_28_SLEW {fast} CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_28_PULLUP {disabled} CONFIG.PCW_MIO_29_SLEW {fast} CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_29_PULLUP {disabled} CONFIG.PCW_MIO_30_SLEW {fast} CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_30_PULLUP {disabled} CONFIG.PCW_MIO_31_SLEW {fast} CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_31_PULLUP {disabled} CONFIG.PCW_MIO_32_SLEW {fast} CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_32_PULLUP {disabled} CONFIG.PCW_MIO_33_SLEW {fast} CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_33_PULLUP {disabled} CONFIG.PCW_MIO_34_SLEW {fast} CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_34_PULLUP {disabled} CONFIG.PCW_MIO_35_SLEW {fast} CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_35_PULLUP {disabled} CONFIG.PCW_MIO_36_SLEW {fast} CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_36_PULLUP {disabled} CONFIG.PCW_MIO_37_SLEW {fast} CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_37_PULLUP {disabled} CONFIG.PCW_MIO_38_SLEW {fast} CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_38_PULLUP {disabled} CONFIG.PCW_MIO_39_SLEW {fast} CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_39_PULLUP {disabled} CONFIG.PCW_MIO_40_SLEW {fast} CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_40_PULLUP {disabled} CONFIG.PCW_MIO_41_SLEW {fast} CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_41_PULLUP {disabled} CONFIG.PCW_MIO_42_SLEW {fast} CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_42_PULLUP {disabled} CONFIG.PCW_MIO_43_SLEW {fast} CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_43_PULLUP {disabled} CONFIG.PCW_MIO_44_SLEW {fast} CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_44_PULLUP {disabled} CONFIG.PCW_MIO_45_SLEW {fast} CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_45_PULLUP {disabled} CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_46_PULLUP {disabled} CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_47_PULLUP {disabled} CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_48_PULLUP {disabled} CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_49_PULLUP {disabled} CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_50_PULLUP {disabled} CONFIG.PCW_MIO_50_DIRECTION {in} CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_51_PULLUP {disabled} CONFIG.PCW_MIO_51_DIRECTION {in} CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_52_PULLUP {disabled} CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} CONFIG.PCW_MIO_53_PULLUP {disabled} CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} CONFIG.PCW_UIPARAM_DDR_BL {8} CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333313} CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {14} CONFIG.PCW_UIPARAM_DDR_CL {7} CONFIG.PCW_UIPARAM_DDR_CWL {6} CONFIG.PCW_UIPARAM_DDR_T_RCD {7} CONFIG.PCW_UIPARAM_DDR_T_RP {7} CONFIG.PCW_UIPARAM_DDR_T_RC {49.5} CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {36} CONFIG.PCW_UIPARAM_DDR_T_FAW {45} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.025} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.028} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.061} CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J128M16 HA-15E} CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.41} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.411} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.341} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.358} CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666667} CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.000000} CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {150.000000} CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50.000000} CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200.000000} CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {50} CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} ] [get_bd_cells $ps7_ip]
hdl/modules/AvnetBoards/ZedBoard/1.2/board_part.xml 0 → 100755
View file @ 9a0e5a45
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<board_part board_name="zed" board_revision="d" board_part="part0" schema_version="1.1" vendor="em.avnet.com" version="1.2" preset_file="preset.xml">
<part_info part_name="xc7z020clg484-1" jtag_position="1" silicon_version="1.0" />
<board_info description="ZedBoard Zynq Evaluation and Development Kit" display_name="ZedBoard Zynq Evaluation and Development Kit" url="http://www.zedboard.org"/>
<interfaces>
<interface mode="master" name="btns_5bits" type="xilinx.com:interface:gpio_rtl:1.0">
<port_maps>
<port_map logical_port="TRI_I" physical_port="btns_5bits_tri_i"/>
</port_maps>
</interface>
<interface mode="master" name="leds_8bits" type="xilinx.com:interface:gpio_rtl:1.0">
<port_maps>
<port_map logical_port="TRI_O" physical_port="leds_8bits_tri_o"/>
</port_maps>
</interface>
<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" preset_proc_name="ps7_preset">
</interface>
<interface mode="master" name="sws_8bits" type="xilinx.com:interface:gpio_rtl:1.0">
<port_maps>
<port_map logical_port="TRI_I" physical_port="sws_8bits_tri_i"/>
</port_maps>
</interface>
<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0">
<port_maps>
<port_map logical_port="CLK" physical_port="sys_clk"/>
</port_maps>
<parameters>
<parameter name="frequency" value="100000000"/>
</parameters>
</interface>
</interfaces>
<ports>
<port dir="in" left="4" name="btns_5bits_tri_i" right="0">
<pins>
<pin index="0" iostandard="LVCMOS25" loc="P16"/>
<pin index="1" iostandard="LVCMOS25" loc="R16"/>
<pin index="2" iostandard="LVCMOS25" loc="N15"/>
<pin index="3" iostandard="LVCMOS25" loc="R18"/>
<pin index="4" iostandard="LVCMOS25" loc="T18"/>
</pins>
</port>
<port dir="out" left="7" name="leds_8bits_tri_o" right="0">
<pins>
<pin index="0" iostandard="LVCMOS33" loc="T22"/>
<pin index="1" iostandard="LVCMOS33" loc="T21"/>
<pin index="2" iostandard="LVCMOS33" loc="U22"/>
<pin index="3" iostandard="LVCMOS33" loc="U21"/>
<pin index="4" iostandard="LVCMOS33" loc="V22"/>
<pin index="5" iostandard="LVCMOS33" loc="W22"/>
<pin index="6" iostandard="LVCMOS33" loc="U19"/>
<pin index="7" iostandard="LVCMOS33" loc="U14"/>
</pins>
</port>
<port dir="in" left="7" name="sws_8bits_tri_i" right="0">
<pins>
<pin index="0" iostandard="LVCMOS25" loc="F22"/>
<pin index="1" iostandard="LVCMOS25" loc="G22"/>
<pin index="2" iostandard="LVCMOS25" loc="H22"/>
<pin index="3" iostandard="LVCMOS25" loc="F21"/>
<pin index="4" iostandard="LVCMOS25" loc="H19"/>
<pin index="5" iostandard="LVCMOS25" loc="H18"/>
<pin index="6" iostandard="LVCMOS25" loc="H17"/>
<pin index="7" iostandard="LVCMOS25" loc="M15"/>
</pins>
</port>
<port dir="in" name="sys_clk">
<pins>
<pin iostandard="LVCMOS33" loc="Y9"/>
</pins>
</port>
</ports>
</board_part>
hdl/modules/AvnetBoards/ZedBoard/1.2/preset.xml 0 → 100755
View file @ 9a0e5a45
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ip_presets schema="1.0">
<ip_preset preset_proc_name="ps7_preset">
<ip vendor="xilinx.com" library="ip" name="processing_system7" version="5.4">
<user_parameters>
<user_parameter name="CONFIG.preset" value="ZedBoard"/>
</user_parameters>
</ip>
</ip_preset>
</ip_presets>
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