This card is a carrier for two low pin count FPGA Mezzanine Cards (VITA
57) with additional 200 kSPS bipolar analog inputs, Ethernet
connectivity and fail-safe functionality.
The card has been developed within CERN's TE-ABT
for the Fast Interlocks Detection System (FIDS) project.
The main controller is a System-on-a-Chip from Xilinx, the Zynq XCZ030
that consists of two silicon ARM cores and FPGA fabric. The idea is to
implement fast interlocking logic (<100ns reaction time, 1 ns
resolution measurements) in the FPGA while the processor, running
Embedded GNU/Linux, runs user applications to control deterministically
the equipment and communicate with other devices and CERN's Controls
MiddleWare (CMW). Additionally there is DDR3L memory, clocking resources
and support for the White Rabbit timing and control network. Stand-alone
board for use in a 19" rack 1U crate (aka
XC7Z030 controller, SoC with Kintex-7 logic (called PL, i.e.
Programmable Logic) and Dual ARM Cortex-A9 MPCore at 1 GHz (called
PS, i.e. Processing System)
Two Low-Pin Count FMC slots
FMC1 connectivity: Vadj fixed to 2.5V, 34 differential pairs, 1
GTP transceiver with clock, 2 clock pairs, JTAG, I2C
A COTS METcase product, M6219145, has been modified for the FASEC with cut-outs and serigraph text for the connectors. The design drawings for the modifications can be found here: metacse_M6219145_fasec_modifs.zip.
Because this design is used in fast pulsed systems with racks that have a low-impedance connection to the pulsed ground in front, a conductive front-panel has been requested from the supplier. This is achieved through a Interlox 338 coating on the aluminium.
The crate is equipped with a Sunon MF35101V2 fan with a female Molex 22-01-2027 connector.
As indicated in the schematics, the card's power supply should meet the following specifications:
The Artesyn LPT102-M is the suggested power supply, that meets the above specification and integrates nicely in the enclosure.
All price indications come from the latest x25 pieces V3 production.