enable/disable channels through DCR enable bit

This patch addresses the performance problem reported
by Christophe Chanavat (a single call to fdelay_config_pulse
takes 2.1ms to complete).

The time is spent in driving the GPIO enable line that
controls the output stage decoupling. This is done via SPI,
and each spi_xfer takes 420us, which add up to the reported
delay.

The fix leaves the enable pins always on, so the output relay
is not used to control whether the outputs are enabled/disabled;
it is the DCR enable bit who takes this role instead.

This results in an average 8us time for output delay configuration,
3us for output disable.

Conflicts:
	kernel/fd-zio.c
parent ced80103
......@@ -129,7 +129,7 @@ int fd_probe(struct fmc_device *fmc)
struct fd_dev *fd;
struct device *dev = &fmc->dev;
char *fwname;
int i, index, ret;
int i, index, ret, ch;
fd = kzalloc(sizeof(*fd), GFP_KERNEL);
if (!fd) {
......@@ -258,6 +258,10 @@ int fd_probe(struct fmc_device *fmc)
ts3.tv_sec, ts3.tv_nsec);
}
set_bit(FD_FLAG_INITED, &fd->flags);
/* set all output enable stages */
for (ch = 1; ch <= FD_CH_NUMBER; ch++)
fd_gpio_set(fd, FD_GPIO_OUTPUT_EN(ch));
return 0;
err:
......
......@@ -435,7 +435,9 @@ static void __fd_zio_output(struct fd_dev *fd, int index1_4, uint32_t *attrs)
int dcr;
if (mode == FD_OUT_MODE_DISABLED) {
fd_gpio_clr(fd, FD_GPIO_OUTPUT_EN(index1_4));
/* disable output via DCR register */
dcr = 0;
fd_ch_writel(fd, ch, dcr, FD_REG_DCR);
return;
}
......@@ -538,11 +540,9 @@ static void __fd_zio_output(struct fd_dev *fd, int index1_4, uint32_t *attrs)
fd_ch_writel(fd, ch, dcr, FD_REG_DCR);
fd_ch_writel(fd, ch, dcr | FD_DCR_UPDATE, FD_REG_DCR);
fd_ch_writel(fd, ch, dcr | FD_DCR_ENABLE, FD_REG_DCR);
if (mode == FD_OUT_MODE_PULSE)
fd_ch_writel(fd, ch, dcr | FD_DCR_ENABLE | FD_DCR_PG_ARM,
FD_REG_DCR);
fd_gpio_set(fd, FD_GPIO_OUTPUT_EN(index1_4));
if (mode == FD_OUT_MODE_PULSE) {
fd_ch_writel(fd, ch, dcr | FD_DCR_ENABLE | FD_DCR_PG_ARM, FD_REG_DCR);
}
}
/* This is called on user write */
......
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