Propogation delay of buffer in feedback loop of PLL
Current design contains an AND gate, used to buffer the signal from the mezzanine clock to the carrier board to 2.5V.
This adds a 2ns propogation delay to the feedback loop. Needs to be investigated to see if this will be problamatic for synchronisation of the clocks on the carrier and mezzanine.
Perhaps not even required in the design as the IO bank on the FPGA is powered by 2.5V however it can be driven by 3.3V, which is the output of the VCXO before it has been buffered.