SPI master and AD5662BRMZ-1 DAC bug
Bug observed when setting the register in the AD5662BRMZ-1 DAC. Wires were soldered to the board to observe the SPI lines with an oscilloscope, and the waveform appeared as expected. When investigating the problem it was found that setting the top data bit high (bit 15), of the DAC data register (bits 15:0), a value was instead being written to the part of the register which controls the mode of operation (bits 17:16). This would place the DAC into power down mode. This behaviour seems dependand on the firmware version despite using the same SPI master.
It is suggested that the SPI master is configured differently using the
clock polarity and clock phase fields in the control