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mcattin authored
Now the interrupt is generated when the DDR interface write FIFO is empty. This is to avoid read request from the host before all data are written to the DDR memory. Add synthesis, p&r and timing reports. Remove generated simulation files from repo. git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@123 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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