-
hdl: removed carrier one-wire master (now handled by WR PTP core), introduced SPI Flash interface for WR PTP core, migrated all carrier HDL to 62.5MHz clock (FMC-ADC and DMA datapath still on 125MHz)
cff7f492
hdl: removed carrier one-wire master (now handled by WR PTP core), introduced SPI Flash interface for WR PTP core, migrated all carrier HDL to 62.5MHz clock (FMC-ADC and DMA datapath still on 125MHz)