hdl, doc, sim: Fix sdb bridge offset address, add config ok flag, update doc in progress.

0580effb · Matthieu Cattin · b48832a9 · 0580effb · 0580effb · 0580effb
Commit 0580effb authored Dec 20, 2013 by Matthieu Cattin
21 changed files
--- a/documentation/figures/acq_fsm.dia
+++ b/documentation/figures/acq_fsm.dia
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--- a/documentation/manuals/firmware/fmc_adc_100Ms_csr.tex
+++ b/documentation/manuals/firmware/fmc_adc_100Ms_csr.tex
@@ -180,7 +180,12 @@ SerDes PLL status
 @code{SERDES_SYNCED}
 @tab @code{X} @tab 
 SerDes synchronization status
-@item @code{31...5}
+@item @code{5}
+@tab R/O @tab
+@code{ACQ_CFG}
+@tab @code{X} @tab 
+Acquisition configuration status
+@item @code{31...6}
 @tab R/O @tab
 @code{RESERVED}
 @tab @code{X} @tab 
@@ -188,9 +193,10 @@ Reserved
 @end multitable
 @multitable @columnfractions 0.15 0.85
 @headitem Field @tab Description
-@item @code{fsm} @tab States:@*0: illegal@*1: IDLE@*2: PRE_TRIG@*3: WAIT_TRIG@*4: POST_TRIG@*5: DECR_SHOT@*6: illegal@*7: illegal
+@item @code{fsm} @tab States:@*0: illegal@*1: IDLE@*2: PRE_TRIG@*3: WAIT_TRIG@*4: POST_TRIG@*5: TRIG_TAG@*6: DECR_SHOT@*7: illegal
 @item @code{serdes_pll} @tab Sampling clock recovery PLL.@*0: not locked@*1: locked
 @item @code{serdes_synced} @tab 0: bitslip in progress@*1: serdes synchronized
+@item @code{acq_cfg} @tab 0: Unauthorised acquisition configuration (will prevent acquisition to start)@*1: Valid acquisition configuration@*@bullet{}  Shot number > 0@*@bullet{}  Post-trigger sample > 0
 @item @code{reserved} @tab Ignore on read, write with 0's
 @end multitable
 @regsection @code{trig_cfg} - Trigger configuration
@@ -240,7 +246,7 @@ Threshold for internal trigger
 @item @code{sw_trig_en} @tab 0: disable@*1: enable
 @item @code{int_trig_sel} @tab 00: channel 1@*01: channel 2@*10: channel 3@*11: channel 4
 @item @code{reserved} @tab Ignore on read, write with 0's
-@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data
+@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data.
 @end multitable
 @regsection @code{trig_dly} - Trigger delay
 @multitable @columnfractions .10 .10 .15 .10 .55
@@ -321,7 +327,7 @@ Pre-trigger samples
 @end multitable
 @multitable @columnfractions 0.15 0.85
 @headitem Field @tab Description
-@item @code{pre_samples} @tab Number of requested pre-trigger samples
+@item @code{pre_samples} @tab Number of requested pre-trigger samples (>1).
 @end multitable
 @regsection @code{post_samples} - Post-trigger samples
 @multitable @columnfractions .10 .10 .15 .10 .55
@@ -334,7 +340,7 @@ Post-trigger samples
 @end multitable
 @multitable @columnfractions 0.15 0.85
 @headitem Field @tab Description
-@item @code{post_samples} @tab Number of requested post-trigger samples
+@item @code{post_samples} @tab Number of requested post-trigger samples (>1).
 @end multitable
 @regsection @code{samples_cnt} - Samples counter
 @multitable @columnfractions .10 .10 .15 .10 .55

--- a/documentation/manuals/firmware/fmcadc100m14b4cha_firmware_manual.in
+++ b/documentation/manuals/firmware/fmcadc100m14b4cha_firmware_manual.in
@@ -420,6 +420,10 @@ Those two counters are accessible in read/write mode via registers.
 To time-tag the events, the ADC core sends pulses to the time-tagging core.
 The following events are time-tagged; trigger, acquisition start, acquisition stop and acquisition end.

+@quotation Note
+The trigger time tag corresponds to the moment when the acquisition FSM leaves the @code{WAIT_TRIG} state.
+@end quotation
+
 @quotation Note
 In this release, the meta-data register is NOT used, set to zero.
 @end quotation
@@ -876,7 +880,11 @@ The LED labeled @code{ACQ} is turned ON when the acquisition state machine is @b
 The LED labeled @code{TRIG} flashes when a valid trigger is detected @b{and} the acquisition state machine is in the @code{WAIT_TRIG} state.

 @quotation Note
-In addition to the requested pre/post-trigger samples, an addition sample, corresponding to the trigger, will be recoded.
+The number of pre-trigger sample can be zero, but there @b{must} be at least one post-trigger sample.
+@end quotation
+
+@quotation Note
+In addition to the requested pre/post-trigger samples, an additional sample, corresponding to the trigger, will be recoded.
 @end quotation

 @c --------------------------------------------------------------------------

--- a/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
@@ -172,7 +172,8 @@ architecture rtl of fmc_adc_100Ms_core is
      fmc_adc_core_sta_fsm_i                 : in  std_logic_vector(2 downto 0);
      fmc_adc_core_sta_serdes_pll_i          : in  std_logic;
      fmc_adc_core_sta_serdes_synced_i       : in  std_logic;
-      fmc_adc_core_sta_reserved_i            : in  std_logic_vector(26 downto 0);
+      fmc_adc_core_sta_acq_cfg_i             : in  std_logic;
+      fmc_adc_core_sta_reserved_i            : in  std_logic_vector(25 downto 0);
      fmc_adc_core_trig_cfg_hw_trig_sel_o    : out std_logic;
      fmc_adc_core_trig_cfg_hw_trig_pol_o    : out std_logic;
      fmc_adc_core_trig_cfg_hw_trig_en_o     : out std_logic;
@@ -372,12 +373,13 @@ architecture rtl of fmc_adc_100Ms_core is
  signal acq_in_wait_trig      : std_logic;
  signal acq_in_post_trig      : std_logic;
  signal acq_in_trig_tag       : std_logic;
+  signal acq_in_trig_tag_d     : std_logic;
  signal samples_wr_en         : std_logic;
+  signal acq_config_ok         : std_logic;

  -- Trigger tag insertion in data
-  signal trig_tag_done     : std_logic;
-  signal trig_tag_data     : std_logic_vector(63 downto 0);
-  signal trig_tag_progress : std_logic_vector(1 downto 0);
+  signal trig_tag_done : std_logic;
+  signal trig_tag_data : std_logic_vector(63 downto 0);

  -- pre/post trigger and shots counters
  signal pre_trig_value       : std_logic_vector(31 downto 0);
@@ -705,6 +707,7 @@ begin
      fmc_adc_core_sta_fsm_i                 => acq_fsm_state,
      fmc_adc_core_sta_serdes_pll_i          => locked_out,
      fmc_adc_core_sta_serdes_synced_i       => serdes_synced,
+      fmc_adc_core_sta_acq_cfg_i             => acq_config_ok,
      fmc_adc_core_sta_reserved_i            => (others => '0'),
      fmc_adc_core_trig_cfg_hw_trig_sel_o    => hw_trig_sel,
      fmc_adc_core_trig_cfg_hw_trig_pol_o    => hw_trig_pol,
@@ -1013,24 +1016,6 @@ begin
  ------------------------------------------------------------------------------
  -- Pre-trigger counter
  ------------------------------------------------------------------------------
-  --p_pre_trig_cnt : process (sys_clk_i, sys_rst_n_i)
-  --begin
-  --  if sys_rst_n_i = '0' then
-  --    pre_trig_cnt  <= to_unsigned(1, pre_trig_cnt'length);
-  --    pre_trig_done <= '0';
-  --  elsif rising_edge(sys_clk_i) then
-  --    if (acq_start = '1' or pre_trig_done = '1') then
-  --      pre_trig_cnt  <= unsigned(pre_trig_value);
-  --      pre_trig_done <= '0';
-  --    elsif pre_trig_cnt = to_unsigned(0, pre_trig_cnt'length) then
-  --      pre_trig_done <= '1';
-  --    elsif (acq_in_pre_trig = '1' and sync_fifo_valid = '1') then
-  --      pre_trig_cnt <= pre_trig_cnt - 1;
-  --    end if;
-  --  end if;
-  --end process p_pre_trig_cnt;
-
-
  p_pre_trig_cnt : process (sys_clk_i, sys_rst_n_i)
  begin
    if sys_rst_n_i = '0' then
@@ -1055,35 +1040,13 @@ begin
  ------------------------------------------------------------------------------
  -- Post-trigger counter
  ------------------------------------------------------------------------------
-  --p_post_trig_cnt : process (sys_clk_i, sys_rst_n_i)
-  --begin
-  --  if sys_rst_n_i = '0' then
-  --    post_trig_cnt  <= to_unsigned(1, post_trig_cnt'length);
-  --    post_trig_done <= '0';
-  --  elsif rising_edge(sys_clk_i) then
-  --    if (acq_start = '1' or post_trig_done = '1') then
-  --      post_trig_cnt  <= unsigned(post_trig_value);
-  --      post_trig_done <= '0';
-  --    elsif post_trig_cnt = to_unsigned(0, post_trig_cnt'length) then
-  --      post_trig_done <= '1';
-  --    elsif (acq_in_post_trig = '1' and sync_fifo_valid = '1') then
-  --      post_trig_cnt <= post_trig_cnt - 1;
-  --    end if;
-  --  end if;
-  --end process p_post_trig_cnt;
-
-
  p_post_trig_cnt : process (sys_clk_i, sys_rst_n_i)
  begin
    if sys_rst_n_i = '0' then
      post_trig_cnt <= to_unsigned(1, post_trig_cnt'length);
    elsif rising_edge(sys_clk_i) then
      if (acq_start = '1' or post_trig_done = '1') then
-        if unsigned(post_trig_value) = to_unsigned(0, post_trig_value'length) then
-          post_trig_cnt <= (others => '0');
-        else
-          post_trig_cnt <= unsigned(post_trig_value) - 1;
-        end if;
+        post_trig_cnt <= unsigned(post_trig_value) - 1;
      elsif (acq_in_post_trig = '1' and sync_fifo_valid = '1') then
        post_trig_cnt <= post_trig_cnt - 1;
      end if;
@@ -1136,7 +1099,15 @@ begin
  acq_start <= '1' when fsm_cmd_wr = '1' and fsm_cmd = "01" else '0';
  acq_stop  <= '1' when fsm_cmd_wr = '1' and fsm_cmd = "10" else '0';
  acq_trig  <= sync_fifo_valid and sync_fifo_dout(64) and acq_in_wait_trig;
-  acq_end   <= shots_done and post_trig_done;
+  acq_end   <= trig_tag_done and shots_done;
+
+  -- Check acquisition configuration
+  --   Post-trigger sample must be > 0
+  --   Shot number must be > 0
+  acq_config_ok <= '0' when
+                   unsigned(post_trig_value) = to_unsigned(0, post_trig_value'length) and
+                   unsigned(shots_value) = to_unsigned(0, shots_value'length)
+                   else '1';

  -- FSM transitions
  p_acq_fsm_transitions : process(sys_clk_i, sys_rst_n_i)
@@ -1148,7 +1119,7 @@ begin
      case acq_fsm_current_state is

        when IDLE =>
-          if acq_start = '1' then
+          if acq_start = '1' and acq_config_ok = '1' then
            acq_fsm_current_state <= PRE_TRIG;
          end if;

@@ -1277,279 +1248,271 @@ begin
  ------------------------------------------------------------------------------
  -- Inserting trigger time-tag after post_trigger samples
  ------------------------------------------------------------------------------
-  -- ###
-    p_insert_trig_tag : process (sys_clk_i, sys_rst_n_i)
-    begin
-      if sys_rst_n_i = '0' then
-        trig_tag_data <= (others => '0');
-        trig_tag_progress <= (others => '0');
-      elsif rising_edge(sys_clk_i) then
-        trig_tag_done <= acq_in_trig_tag;
-        if trig_tag_done = '0' then
-          trig_tag_data <= trigger_tag_i.seconds & trigger_tag_i.meta;
-        elsif trig_tag_done = '1' then
-          trig_tag_data <= trigger_tag_i.fine & trigger_tag_i.coarse;
-        end if;
-      end if;
-    end process p_insert_trig_tag;
-    -- ###
+  p_trig_tag_done : process (sys_clk_i, sys_rst_n_i)
+  begin
+    if sys_rst_n_i = '0' then
+      acq_in_trig_tag_d <= '0';
+    elsif rising_edge(sys_clk_i) then
+      acq_in_trig_tag_d <= acq_in_trig_tag;
+    end if;
+  end process p_trig_tag_done;

-    ------------------------------------------------------------------------------
-    -- Dual DPRAM buffers for multi-shots acquisition
-    ------------------------------------------------------------------------------
+  trig_tag_done <= acq_in_trig_tag and acq_in_trig_tag_d;

-    -- DPRAM input address counter
-    p_dpram_addra_cnt : process (sys_clk_i, sys_rst_n_i)
-    begin
-      if sys_rst_n_i = '0' then
-        dpram_addra_cnt       <= (others => '0');
-        dpram_addra_trig      <= (others => '0');
-        dpram_addra_post_done <= (others => '0');
-      elsif rising_edge(sys_clk_i) then
-        if shots_decr = '1' then
-          dpram_addra_cnt <= to_unsigned(0, dpram_addra_cnt'length);
-        elsif (samples_wr_en = '1' and sync_fifo_valid = '1') then
-          dpram_addra_cnt <= dpram_addra_cnt + 1;
-        end if;
-        if acq_trig = '1' then
-          dpram_addra_trig <= dpram_addra_cnt;
-        end if;
-        if post_trig_done = '1' then
-          if unsigned(post_trig_value) = to_unsigned(0, post_trig_value'length) then
-            dpram_addra_post_done <= dpram_addra_cnt - 1;
-          else
-            dpram_addra_post_done <= dpram_addra_cnt;
-          end if;
-        end if;
+  trig_tag_data <= trigger_tag_i.fine & trigger_tag_i.coarse when trig_tag_done = '1' else
+                   trigger_tag_i.seconds & trigger_tag_i.meta;
+
+  ------------------------------------------------------------------------------
+  -- Dual DPRAM buffers for multi-shots acquisition
+  ------------------------------------------------------------------------------
+
+  -- DPRAM input address counter
+  p_dpram_addra_cnt : process (sys_clk_i, sys_rst_n_i)
+  begin
+    if sys_rst_n_i = '0' then
+      dpram_addra_cnt       <= (others => '0');
+      dpram_addra_trig      <= (others => '0');
+      dpram_addra_post_done <= (others => '0');
+    elsif rising_edge(sys_clk_i) then
+      if shots_decr = '1' then
+        dpram_addra_cnt <= to_unsigned(0, dpram_addra_cnt'length);
+      elsif (samples_wr_en = '1' and sync_fifo_valid = '1') or (acq_in_trig_tag = '1') then
+        dpram_addra_cnt <= dpram_addra_cnt + 1;
      end if;
-    end process p_dpram_addra_cnt;
-
-    -- DPRAM inputs
-    dpram0_addra <= std_logic_vector(dpram_addra_cnt);
-    dpram1_addra <= std_logic_vector(dpram_addra_cnt);
-    dpram0_dina  <= sync_fifo_dout(63 downto 0)                          when acq_in_trig_tag = '0'      else trig_tag_data;  -- ###
-    dpram1_dina  <= sync_fifo_dout(63 downto 0)                          when acq_in_trig_tag = '0'      else trig_tag_data;  -- ###;
-    dpram0_wea   <= (samples_wr_en and sync_fifo_valid) or acq_in_trig_tag when multishot_buffer_sel = '0' else '0';            -- ###
-    dpram1_wea   <= (samples_wr_en and sync_fifo_valid) or acq_in_trig_tag when multishot_buffer_sel = '1' else '0';            -- ###
-
-    -- DPRAMs
-    cmp_multishot_dpram0 : generic_dpram
-      generic map
-      (
-        g_data_width               => 64,
-        g_size                     => g_multishot_ram_size,
-        g_with_byte_enable         => false,
-        g_addr_conflict_resolution => "read_first",
-        g_dual_clock               => true
-        -- default values for the rest of the generics are okay
-        )
-      port map
-      (
-        rst_n_i => sys_rst_n_i,
-        clka_i  => sys_clk_i,
-        bwea_i  => open,
-        wea_i   => dpram0_wea,
-        aa_i    => dpram0_addra,
-        da_i    => dpram0_dina,
-        qa_o    => open,
-        clkb_i  => sys_clk_i,
-        bweb_i  => open,
-        ab_i    => dpram0_addrb,
-        -- db_i    => (others => '0'),
-        qb_o    => dpram0_doutb
-        );
+      if acq_trig = '1' then
+        dpram_addra_trig <= dpram_addra_cnt;
+      end if;
+      if post_trig_done = '1' then
+        dpram_addra_post_done <= dpram_addra_cnt;
+      end if;
+    end if;
+  end process p_dpram_addra_cnt;
+
+  -- DPRAM inputs
+  dpram0_addra <= std_logic_vector(dpram_addra_cnt);
+  dpram1_addra <= std_logic_vector(dpram_addra_cnt);
+  dpram0_dina  <= sync_fifo_dout(63 downto 0)                            when acq_in_trig_tag = '0'      else trig_tag_data;
+  dpram1_dina  <= sync_fifo_dout(63 downto 0)                            when acq_in_trig_tag = '0'      else trig_tag_data;
+  dpram0_wea   <= (samples_wr_en and sync_fifo_valid) or acq_in_trig_tag when multishot_buffer_sel = '0' else '0';
+  dpram1_wea   <= (samples_wr_en and sync_fifo_valid) or acq_in_trig_tag when multishot_buffer_sel = '1' else '0';
+
+  -- DPRAMs
+  cmp_multishot_dpram0 : generic_dpram
+    generic map
+    (
+      g_data_width               => 64,
+      g_size                     => g_multishot_ram_size,
+      g_with_byte_enable         => false,
+      g_addr_conflict_resolution => "read_first",
+      g_dual_clock               => true
+      -- default values for the rest of the generics are okay
+      )
+    port map
+    (
+      rst_n_i => sys_rst_n_i,
+      clka_i  => sys_clk_i,
+      bwea_i  => open,
+      wea_i   => dpram0_wea,
+      aa_i    => dpram0_addra,
+      da_i    => dpram0_dina,
+      qa_o    => open,
+      clkb_i  => sys_clk_i,
+      bweb_i  => open,
+      ab_i    => dpram0_addrb,
+      -- db_i    => (others => '0'),
+      qb_o    => dpram0_doutb
+      );

-    cmp_multishot_dpram1 : generic_dpram
-      generic map
-      (
-        g_data_width               => 64,
-        g_size                     => g_multishot_ram_size,
-        g_with_byte_enable         => false,
-        g_addr_conflict_resolution => "read_first",
-        g_dual_clock               => false
-        -- default values for the rest of the generics are okay
-        )
-      port map
-      (
-        rst_n_i => sys_rst_n_i,
-        clka_i  => sys_clk_i,
-        bwea_i  => open,
-        wea_i   => dpram1_wea,
-        aa_i    => dpram1_addra,
-        da_i    => dpram1_dina,
-        qa_o    => open,
-        clkb_i  => sys_clk_i,
-        bweb_i  => open,
-        ab_i    => dpram1_addrb,
-        -- db_i    => (others => '0'),
-        qb_o    => dpram1_doutb
-        );
+  cmp_multishot_dpram1 : generic_dpram
+    generic map
+    (
+      g_data_width               => 64,
+      g_size                     => g_multishot_ram_size,
+      g_with_byte_enable         => false,
+      g_addr_conflict_resolution => "read_first",
+      g_dual_clock               => false
+      -- default values for the rest of the generics are okay
+      )
+    port map
+    (
+      rst_n_i => sys_rst_n_i,
+      clka_i  => sys_clk_i,
+      bwea_i  => open,
+      wea_i   => dpram1_wea,
+      aa_i    => dpram1_addra,
+      da_i    => dpram1_dina,
+      qa_o    => open,
+      clkb_i  => sys_clk_i,
+      bweb_i  => open,
+      ab_i    => dpram1_addrb,
+      -- db_i    => (others => '0'),
+      qb_o    => dpram1_doutb
+      );

-    -- DPRAM output address counter
-    p_dpram_addrb_cnt : process (sys_clk_i, sys_rst_n_i)
-    begin
-      if sys_rst_n_i = '0' then
-        dpram_addrb_cnt <= (others => '0');
-        dpram_valid_t   <= '0';
-        dpram_valid     <= '0';
-      elsif rising_edge(sys_clk_i) then
-        if post_trig_done = '1' then
-          dpram_addrb_cnt <= dpram_addra_trig - unsigned(pre_trig_value(c_dpram_depth-1 downto 0));
-          dpram_valid_t   <= '1';
-        elsif (dpram_addrb_cnt = dpram_addra_post_done) then
-          dpram_valid_t <= '0';
-        else
-          dpram_addrb_cnt <= dpram_addrb_cnt + 1;
-        end if;
-        dpram_valid <= dpram_valid_t;
+  -- DPRAM output address counter
+  p_dpram_addrb_cnt : process (sys_clk_i, sys_rst_n_i)
+  begin
+    if sys_rst_n_i = '0' then
+      dpram_addrb_cnt <= (others => '0');
+      dpram_valid_t   <= '0';
+      dpram_valid     <= '0';
+    elsif rising_edge(sys_clk_i) then
+      if trig_tag_done = '1' then
+        dpram_addrb_cnt <= dpram_addra_trig - unsigned(pre_trig_value(c_dpram_depth-1 downto 0));
+        dpram_valid_t   <= '1';
+      elsif (dpram_addrb_cnt = dpram_addra_post_done + 2) then  -- reads 2 extra addresses -> trigger time-tag
+        dpram_valid_t <= '0';
+      else
+        dpram_addrb_cnt <= dpram_addrb_cnt + 1;
      end if;
-    end process p_dpram_addrb_cnt;
-
-    -- DPRAM output mux
-    dpram_dout   <= dpram0_doutb when multishot_buffer_sel = '1' else dpram1_doutb;
-    dpram0_addrb <= std_logic_vector(dpram_addrb_cnt);
-    dpram1_addrb <= std_logic_vector(dpram_addrb_cnt);
-
-    ------------------------------------------------------------------------------
-    -- Flow control FIFO for data to DDR
-    ------------------------------------------------------------------------------
-    cmp_wb_ddr_fifo : generic_sync_fifo
-      generic map (
-        g_data_width             => 65,
-        g_size                   => 64,
-        g_show_ahead             => false,
-        g_with_empty             => true,
-        g_with_full              => true,
-        g_with_almost_empty      => false,
-        g_with_almost_full       => false,
-        g_with_count             => false,
-        g_almost_empty_threshold => 0,
-        g_almost_full_threshold  => 0
-        )
-      port map(
-        rst_n_i        => sys_rst_n_i,
-        clk_i          => sys_clk_i,
-        d_i            => wb_ddr_fifo_din,
-        we_i           => wb_ddr_fifo_wr,
-        q_o            => wb_ddr_fifo_dout,
-        rd_i           => wb_ddr_fifo_rd,
-        empty_o        => wb_ddr_fifo_empty,
-        full_o         => wb_ddr_fifo_full,
-        almost_empty_o => open,
-        almost_full_o  => open,
-        count_o        => open
-        );
+      dpram_valid <= dpram_valid_t;
+    end if;
+  end process p_dpram_addrb_cnt;

-    -- One clock cycle delay for the FIFO's VALID signal. Since the General Cores
-    -- package does not offer the possibility to use the FWFT feature of the FIFOs,
-    -- we simulate the valid flag here according to Figure 4-7 in ref. [1].
-    p_wb_ddr_fifo_valid : process (sys_clk_i) is
-    begin
-      if rising_edge(sys_clk_i) then
-        wb_ddr_fifo_valid <= wb_ddr_fifo_rd;
-        if (wb_ddr_fifo_empty = '1') then
-          wb_ddr_fifo_valid <= '0';
-        end if;
+  -- DPRAM output mux
+  dpram_dout   <= dpram0_doutb when multishot_buffer_sel = '1' else dpram1_doutb;
+  dpram0_addrb <= std_logic_vector(dpram_addrb_cnt);
+  dpram1_addrb <= std_logic_vector(dpram_addrb_cnt);
+
+  ------------------------------------------------------------------------------
+  -- Flow control FIFO for data to DDR
+  ------------------------------------------------------------------------------
+  cmp_wb_ddr_fifo : generic_sync_fifo
+    generic map (
+      g_data_width             => 65,
+      g_size                   => 64,
+      g_show_ahead             => false,
+      g_with_empty             => true,
+      g_with_full              => true,
+      g_with_almost_empty      => false,
+      g_with_almost_full       => false,
+      g_with_count             => false,
+      g_almost_empty_threshold => 0,
+      g_almost_full_threshold  => 0
+      )
+    port map(
+      rst_n_i        => sys_rst_n_i,
+      clk_i          => sys_clk_i,
+      d_i            => wb_ddr_fifo_din,
+      we_i           => wb_ddr_fifo_wr,
+      q_o            => wb_ddr_fifo_dout,
+      rd_i           => wb_ddr_fifo_rd,
+      empty_o        => wb_ddr_fifo_empty,
+      full_o         => wb_ddr_fifo_full,
+      almost_empty_o => open,
+      almost_full_o  => open,
+      count_o        => open
+      );
+
+  -- One clock cycle delay for the FIFO's VALID signal. Since the General Cores
+  -- package does not offer the possibility to use the FWFT feature of the FIFOs,
+  -- we simulate the valid flag here according to Figure 4-7 in ref. [1].
+  p_wb_ddr_fifo_valid : process (sys_clk_i) is
+  begin
+    if rising_edge(sys_clk_i) then
+      wb_ddr_fifo_valid <= wb_ddr_fifo_rd;
+      if (wb_ddr_fifo_empty = '1') then
+        wb_ddr_fifo_valid <= '0';
      end if;
-    end process;
+    end if;
+  end process;

-    p_wb_ddr_fifo_input : process (sys_clk_i, sys_rst_n_i)
-    begin
-      if sys_rst_n_i = '0' then
-        wb_ddr_fifo_din   <= (others => '0');
-        wb_ddr_fifo_wr_en <= '0';
-      elsif rising_edge(sys_clk_i) then
-        if single_shot = '1' then
-          if acq_in_trig_tag = '1' then
-            wb_ddr_fifo_din   <= trig_tag_data;                           -- ###
-            wb_ddr_fifo_wr_en <= acq_in_trig_tag;                           -- ###
-          else
-            wb_ddr_fifo_din   <= acq_trig & sync_fifo_dout(63 downto 0);  -- trigger + data
-            wb_ddr_fifo_wr_en <= samples_wr_en and sync_fifo_valid;
-          end if;
+  p_wb_ddr_fifo_input : process (sys_clk_i, sys_rst_n_i)
+  begin
+    if sys_rst_n_i = '0' then
+      wb_ddr_fifo_din   <= (others => '0');
+      wb_ddr_fifo_wr_en <= '0';
+    elsif rising_edge(sys_clk_i) then
+      if single_shot = '1' then
+        if acq_in_trig_tag = '1' then
+          wb_ddr_fifo_din   <= '0' & trig_tag_data;
+          wb_ddr_fifo_wr_en <= acq_in_trig_tag;
        else
-          wb_ddr_fifo_din   <= '0' & dpram_dout;
-          wb_ddr_fifo_wr_en <= dpram_valid;
+          wb_ddr_fifo_din   <= acq_trig & sync_fifo_dout(63 downto 0);  -- trigger + data
+          wb_ddr_fifo_wr_en <= samples_wr_en and sync_fifo_valid;
        end if;
+      else
+        wb_ddr_fifo_din   <= '0' & dpram_dout;
+        wb_ddr_fifo_wr_en <= dpram_valid;
      end if;
-    end process p_wb_ddr_fifo_input;
-    --wb_ddr_fifo_din   <= sync_fifo_dout(63 downto 0) when single_shot = '1' else dpram_dout;
-    --wb_ddr_fifo_wr_en <= samples_wr_en               when single_shot = '1' else dpram_valid;
-    wb_ddr_fifo_wr <= wb_ddr_fifo_wr_en and not(wb_ddr_fifo_full);
-
-    wb_ddr_fifo_rd   <= wb_ddr_fifo_dreq and not(wb_ddr_fifo_empty) and not(wb_ddr_stall_t);
-    wb_ddr_fifo_dreq <= '1';
-
-    ------------------------------------------------------------------------------
-    -- RAM address counter (32-bit word address)
-    ------------------------------------------------------------------------------
-    p_ram_addr_cnt : process (wb_ddr_clk_i, sys_rst_n_i)
-    begin
-      if sys_rst_n_i = '0' then
+    end if;
+  end process p_wb_ddr_fifo_input;
+
+  wb_ddr_fifo_wr <= wb_ddr_fifo_wr_en and not(wb_ddr_fifo_full);
+
+  wb_ddr_fifo_rd   <= wb_ddr_fifo_dreq and not(wb_ddr_fifo_empty) and not(wb_ddr_stall_t);
+  wb_ddr_fifo_dreq <= '1';
+
+  ------------------------------------------------------------------------------
+  -- RAM address counter (32-bit word address)
+  ------------------------------------------------------------------------------
+  p_ram_addr_cnt : process (wb_ddr_clk_i, sys_rst_n_i)
+  begin
+    if sys_rst_n_i = '0' then
+      ram_addr_cnt <= (others => '0');
+    elsif rising_edge(wb_ddr_clk_i) then
+      if acq_start = '1' then
        ram_addr_cnt <= (others => '0');
-      elsif rising_edge(wb_ddr_clk_i) then
-        if acq_start = '1' then
-          ram_addr_cnt <= (others => '0');
-        elsif wb_ddr_fifo_valid = '1' then
-          ram_addr_cnt <= ram_addr_cnt + 1;
-        end if;
+      elsif wb_ddr_fifo_valid = '1' then
+        ram_addr_cnt <= ram_addr_cnt + 1;
      end if;
-    end process p_ram_addr_cnt;
+    end if;
+  end process p_ram_addr_cnt;

-    ------------------------------------------------------------------------------
-    -- Store trigger DDR address
-    ------------------------------------------------------------------------------
-    p_trig_addr : process (wb_ddr_clk_i, sys_rst_n_i)
-    begin
-      if sys_rst_n_i = '0' then
-        trig_addr <= (others => '0');
-      elsif rising_edge(wb_ddr_clk_i) then
-        if wb_ddr_fifo_dout(64) = '1' and wb_ddr_fifo_valid = '1' then
-          trig_addr <= "0000000" & std_logic_vector(ram_addr_cnt);
-        end if;
+  ------------------------------------------------------------------------------
+  -- Store trigger DDR address
+  ------------------------------------------------------------------------------
+  p_trig_addr : process (wb_ddr_clk_i, sys_rst_n_i)
+  begin
+    if sys_rst_n_i = '0' then
+      trig_addr <= (others => '0');
+    elsif rising_edge(wb_ddr_clk_i) then
+      if wb_ddr_fifo_dout(64) = '1' and wb_ddr_fifo_valid = '1' then
+        trig_addr <= "0000000" & std_logic_vector(ram_addr_cnt);
      end if;
-    end process p_trig_addr;
+    end if;
+  end process p_trig_addr;

-    ------------------------------------------------------------------------------
-    -- Wishbone master (to DDR)
-    ------------------------------------------------------------------------------
-    p_wb_master : process (wb_ddr_clk_i, sys_rst_n_i)
-    begin
-      if sys_rst_n_i = '0' then
-        wb_ddr_cyc_o   <= '0';
-        wb_ddr_we_o    <= '0';
-        wb_ddr_stb_o   <= '0';
-        wb_ddr_adr_o   <= (others => '0');
-        wb_ddr_dat_o   <= (others => '0');
-        wb_ddr_stall_t <= '0';
-      elsif rising_edge(wb_ddr_clk_i) then
-
-        if wb_ddr_fifo_valid = '1' then  --if (wb_ddr_fifo_valid = '1') and (wb_ddr_stall_i = '0') then
-          wb_ddr_stb_o <= '1';
-          wb_ddr_adr_o <= "0000000" & std_logic_vector(ram_addr_cnt);
-          if test_data_en = '1' then
-            wb_ddr_dat_o <= x"00000000" & "0000000" & std_logic_vector(ram_addr_cnt);
-          else
-            wb_ddr_dat_o <= wb_ddr_fifo_dout(63 downto 0);
-          end if;
+  ------------------------------------------------------------------------------
+  -- Wishbone master (to DDR)
+  ------------------------------------------------------------------------------
+  p_wb_master : process (wb_ddr_clk_i, sys_rst_n_i)
+  begin
+    if sys_rst_n_i = '0' then
+      wb_ddr_cyc_o   <= '0';
+      wb_ddr_we_o    <= '0';
+      wb_ddr_stb_o   <= '0';
+      wb_ddr_adr_o   <= (others => '0');
+      wb_ddr_dat_o   <= (others => '0');
+      wb_ddr_stall_t <= '0';
+    elsif rising_edge(wb_ddr_clk_i) then
+
+      if wb_ddr_fifo_valid = '1' then   --if (wb_ddr_fifo_valid = '1') and (wb_ddr_stall_i = '0') then
+        wb_ddr_stb_o <= '1';
+        wb_ddr_adr_o <= "0000000" & std_logic_vector(ram_addr_cnt);
+        if test_data_en = '1' then
+          wb_ddr_dat_o <= x"00000000" & "0000000" & std_logic_vector(ram_addr_cnt);
        else
-          wb_ddr_stb_o <= '0';
+          wb_ddr_dat_o <= wb_ddr_fifo_dout(63 downto 0);
        end if;
+      else
+        wb_ddr_stb_o <= '0';
+      end if;

-        if wb_ddr_fifo_valid = '1' then
-          wb_ddr_cyc_o <= '1';
-          wb_ddr_we_o  <= '1';
-          --elsif (wb_ddr_fifo_empty = '1') and (acq_end = '1') then
-        elsif (wb_ddr_fifo_empty = '1') and (acq_fsm_state = "001") then
-          wb_ddr_cyc_o <= '0';
-          wb_ddr_we_o  <= '0';
-        end if;
+      if wb_ddr_fifo_valid = '1' then
+        wb_ddr_cyc_o <= '1';
+        wb_ddr_we_o  <= '1';
+        --elsif (wb_ddr_fifo_empty = '1') and (acq_end = '1') then
+      elsif (wb_ddr_fifo_empty = '1') and (acq_fsm_state = "001") then
+        wb_ddr_cyc_o <= '0';
+        wb_ddr_we_o  <= '0';
+      end if;

-        wb_ddr_stall_t <= wb_ddr_stall_i;
+      wb_ddr_stall_t <= wb_ddr_stall_i;

-      end if;
-    end process p_wb_master;
+    end if;
+  end process p_wb_master;

-    wb_ddr_sel_o <= X"FF";
+  wb_ddr_sel_o <= X"FF";

-    end rtl;
+end rtl;
--- a/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ../rtl/fmc_adc_100Ms_csr.vhd
 -- Author         : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created        : Wed Aug  7 17:44:15 2013
+-- Created        : Tue Dec 17 09:57:20 2013
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
@@ -51,8 +51,10 @@ entity fmc_adc_100Ms_csr is
    fmc_adc_core_sta_serdes_pll_i            : in     std_logic;
 -- Port for BIT field: 'SerDes synchronization status' in reg: 'Status register'
    fmc_adc_core_sta_serdes_synced_i         : in     std_logic;
+-- Port for BIT field: 'Acquisition configuration status' in reg: 'Status register'
+    fmc_adc_core_sta_acq_cfg_i               : in     std_logic;
 -- Port for std_logic_vector field: 'Reserved' in reg: 'Status register'
-    fmc_adc_core_sta_reserved_i              : in     std_logic_vector(26 downto 0);
+    fmc_adc_core_sta_reserved_i              : in     std_logic_vector(25 downto 0);
 -- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger selection' in reg: 'Trigger configuration'
    fmc_adc_core_trig_cfg_hw_trig_sel_o      : out    std_logic;
 -- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger polarity' in reg: 'Trigger configuration'
@@ -429,7 +431,8 @@ begin
            rddata_reg(2 downto 0) <= fmc_adc_core_sta_fsm_i;
            rddata_reg(3) <= fmc_adc_core_sta_serdes_pll_i;
            rddata_reg(4) <= fmc_adc_core_sta_serdes_synced_i;
-            rddata_reg(31 downto 5) <= fmc_adc_core_sta_reserved_i;
+            rddata_reg(5) <= fmc_adc_core_sta_acq_cfg_i;
+            rddata_reg(31 downto 6) <= fmc_adc_core_sta_reserved_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00010" => 
@@ -745,6 +748,7 @@ begin
 -- State machine status
 -- SerDes PLL status
 -- SerDes synchronization status
+-- Acquisition configuration status
 -- Reserved
 -- Hardware trigger selection
 -- synchronizer chain for field : Hardware trigger selection (type RW/RO, clk_sys_i <-> fs_clk_i)

--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
@@ -3,7 +3,7 @@

  * File           : fmc_adc_100Ms_csr.h
  * Author         : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-  * Created        : Wed Aug  7 17:44:15 2013
+  * Created        : Tue Dec 17 09:57:20 2013
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
@@ -77,11 +77,14 @@
 /* definitions for field: SerDes synchronization status in reg: Status register */
 #define FMC_ADC_CORE_STA_SERDES_SYNCED        WBGEN2_GEN_MASK(4, 1)

+/* definitions for field: Acquisition configuration status in reg: Status register */
+#define FMC_ADC_CORE_STA_ACQ_CFG              WBGEN2_GEN_MASK(5, 1)
+
 /* definitions for field: Reserved in reg: Status register */
-#define FMC_ADC_CORE_STA_RESERVED_MASK        WBGEN2_GEN_MASK(5, 27)
-#define FMC_ADC_CORE_STA_RESERVED_SHIFT       5
-#define FMC_ADC_CORE_STA_RESERVED_W(value)    WBGEN2_GEN_WRITE(value, 5, 27)
-#define FMC_ADC_CORE_STA_RESERVED_R(reg)      WBGEN2_GEN_READ(reg, 5, 27)
+#define FMC_ADC_CORE_STA_RESERVED_MASK        WBGEN2_GEN_MASK(6, 26)
+#define FMC_ADC_CORE_STA_RESERVED_SHIFT       6
+#define FMC_ADC_CORE_STA_RESERVED_W(value)    WBGEN2_GEN_WRITE(value, 6, 26)
+#define FMC_ADC_CORE_STA_RESERVED_R(reg)      WBGEN2_GEN_READ(reg, 6, 26)

 /* definitions for register: Trigger configuration */


--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
@@ -809,7 +809,24 @@ fmc_adc_core_sta_serdes_synced_i

 </td>
 <td  class="td_pblock_right">
-fmc_adc_core_sta_reserved_i[26:0]
+fmc_adc_core_sta_acq_cfg_i
+</td>
+<td  class="td_arrow_right">
+&larr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+
+</td>
+<td  class="td_pblock_left">
+
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+fmc_adc_core_sta_reserved_i[25:0]
 </td>
 <td  class="td_arrow_right">
 &lArr;
@@ -2849,7 +2866,7 @@ STA
 </tr>
 <tr>
 <td style="border: solid 1px black;" colspan=8  class="td_field">
-RESERVED[26:19]
+RESERVED[25:18]
 </td>
 <td >

@@ -2903,7 +2920,7 @@ RESERVED[26:19]
 </tr>
 <tr>
 <td style="border: solid 1px black;" colspan=8  class="td_field">
-RESERVED[18:11]
+RESERVED[17:10]
 </td>
 <td >

@@ -2957,7 +2974,7 @@ RESERVED[18:11]
 </tr>
 <tr>
 <td style="border: solid 1px black;" colspan=8  class="td_field">
-RESERVED[10:3]
+RESERVED[9:2]
 </td>
 <td >

@@ -3010,8 +3027,11 @@ RESERVED[10:3]
 </td>
 </tr>
 <tr>
-<td style="border: solid 1px black;" colspan=3  class="td_field">
-RESERVED[2:0]
+<td style="border: solid 1px black;" colspan=2  class="td_field">
+RESERVED[1:0]
+</td>
+<td style="border: solid 1px black;" colspan=1  class="td_field">
+ACQ_CFG
 </td>
 <td style="border: solid 1px black;" colspan=1  class="td_field">
 SERDES_SYNCED
@@ -3030,9 +3050,6 @@ FSM[2:0]
 </td>
 <td >

-</td>
-<td >
-
 </td>
 </tr>
 </table>
@@ -3040,7 +3057,7 @@ FSM[2:0]
 <li><b>
 FSM
 </b>[<i>read-only</i>]: State machine status
-<br>States:<br>0: illegal<br>1: IDLE<br>2: PRE_TRIG<br>3: WAIT_TRIG<br>4: POST_TRIG<br>5: DECR_SHOT<br>6: illegal<br>7: illegal
+<br>States:<br>0: illegal<br>1: IDLE<br>2: PRE_TRIG<br>3: WAIT_TRIG<br>4: POST_TRIG<br>5: TRIG_TAG<br>6: DECR_SHOT<br>7: illegal
 <li><b>
 SERDES_PLL
 </b>[<i>read-only</i>]: SerDes PLL status
@@ -3050,6 +3067,10 @@ SERDES_SYNCED
 </b>[<i>read-only</i>]: SerDes synchronization status
 <br>0: bitslip in progress<br>1: serdes synchronized
 <li><b>
+ACQ_CFG
+</b>[<i>read-only</i>]: Acquisition configuration status
+<br>0: Unauthorised acquisition configuration (will prevent acquisition to start)<br>1: Valid acquisition configuration<br>- Shot number > 0<br>- Post-trigger sample > 0
+<li><b>
 RESERVED
 </b>[<i>read-only</i>]: Reserved
 <br>Ignore on read, write with 0's
@@ -3334,7 +3355,7 @@ RESERVED
 <li><b>
 INT_TRIG_THRES
 </b>[<i>read/write</i>]: Threshold for internal trigger
-<br>Treated as binary two's complement and compared to raw ADC data
+<br>Treated as binary two's complement and compared to raw ADC data.
 </ul>
 <a name="TRIG_DLY"></a>
 <h3><a name="sect_3_4">3.4. Trigger delay</a></h3>
@@ -4888,7 +4909,7 @@ PRE_SAMPLES[7:0]
 <li><b>
 PRE_SAMPLES
 </b>[<i>read/write</i>]: Pre-trigger samples
-<br>Number of requested pre-trigger samples
+<br>Number of requested pre-trigger samples (>1).
 </ul>
 <a name="POST_SAMPLES"></a>
 <h3><a name="sect_3_10">3.10. Post-trigger samples</a></h3>
@@ -5146,7 +5167,7 @@ POST_SAMPLES[7:0]
 <li><b>
 POST_SAMPLES
 </b>[<i>read/write</i>]: Post-trigger samples
-<br>Number of requested post-trigger samples
+<br>Number of requested post-trigger samples (>1).
 </ul>
 <a name="SAMPLES_CNT"></a>
 <h3><a name="sect_3_11">3.11. Samples counter</a></h3>

--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
@@ -86,7 +86,7 @@ peripheral {

    field {
      name = "State machine status";
-      description = "States:\n0: illegal\n1: IDLE\n2: PRE_TRIG\n3: WAIT_TRIG\n4: POST_TRIG\n5: DECR_SHOT\n6: illegal\n7: illegal";
+      description = "States:\n0: illegal\n1: IDLE\n2: PRE_TRIG\n3: WAIT_TRIG\n4: POST_TRIG\n5: TRIG_TAG\n6: DECR_SHOT\n7: illegal";
      prefix = "fsm";
      type = SLV;
      size = 3;
@@ -112,12 +112,21 @@ peripheral {
      access_dev = WRITE_ONLY;
    };

+    field {
+      name = "Acquisition configuration status";
+      description = "0: Unauthorised acquisition configuration (will prevent acquisition to start)\n1: Valid acquisition configuration\n- Shot number > 0\n- Post-trigger sample > 0";
+      prefix = "acq_cfg";
+      type = BIT;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
-      size = 27;
+      size = 26;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
@@ -190,7 +199,7 @@ peripheral {

    field {
      name = "Threshold for internal trigger";
-      description = "Treated as binary two's complement and compared to raw ADC data";
+      description = "Treated as binary two's complement and compared to raw ADC data.";
      prefix = "int_trig_thres";
      type = SLV;
      size = 16;
@@ -288,7 +297,7 @@ peripheral {

    field {
      name = "Pre-trigger samples";
-      description = "Number of requested pre-trigger samples";
+      description = "Number of requested pre-trigger samples (>1).";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
@@ -302,7 +311,7 @@ peripheral {

    field {
      name = "Post-trigger samples";
-      description = "Number of requested post-trigger samples";
+      description = "Number of requested post-trigger samples (>1).";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;

--- a/hdl/spec/rtl/carrier_csr.vhd
+++ b/hdl/spec/rtl/carrier_csr.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ../rtl/carrier_csr.vhd
 -- Author         : auto-generated by wbgen2 from carrier_csr.wb
-- Created        : Thu Aug  8 14:54:22 2013
+-- Created        : Wed Dec 11 11:55:04 2013
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb

--- a/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+++ b/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
@@ -347,8 +347,8 @@ architecture rtl of spec_top_fmc_adc_100Ms is
        name      => "WB-FMC-ADC.EIC     ")));

  -- f_xwb_bridge_manual_sdb(size, sdb_addr)
-  -- Note: sdb_addr is the sdb records address relative to the parent interconnect
-  constant c_fmc0_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00004000");
+  -- Note: sdb_addr is the sdb records address relative to the bridge base address
+  constant c_fmc0_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");

  -- sdb header address
  constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";

--- a/hdl/spec/sim/Makefile
+++ b/hdl/spec/sim/Makefile
@@ -12,21 +12,19 @@ VCOM_FLAGS := -quiet -modelsimini modelsim.ini
 VSIM_FLAGS :=
 VLOG_FLAGS := -quiet -modelsimini modelsim.ini 
 VERILOG_SRC := sim_models/2048Mb_ddr3/ddr3.v \
-../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
-../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
-../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
-../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
-../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
-../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
-../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
-../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
-../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
-../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v \
-../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
-../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v \
-../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
-../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v \
-../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v \

 VERILOG_OBJ := work/ddr3/.ddr3_v \
 work/sockit_owm/.sockit_owm_v \
@@ -38,9 +36,7 @@ work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v \
 work/jtag_cores/.jtag_cores_v \
 work/lm32_adder/.lm32_adder_v \
 work/lm32_addsub/.lm32_addsub_v \
-work/lm32_dp_ram/.lm32_dp_ram_v \
 work/lm32_logic_op/.lm32_logic_op_v \
-work/lm32_ram/.lm32_ram_v \
 work/lm32_shifter/.lm32_shifter_v \
 work/lm32_multiplier/.lm32_multiplier_v \
 work/jtag_tap/.jtag_tap_v \
@@ -51,124 +47,147 @@ testbench/mem_model.vhd \
 testbench/cmd_router.vhd \
 testbench/tb_spec.vhd \
 testbench/cmd_router1.vhd \
-../ip_cores/adc_sync_fifo.vhd \
-../ip_cores/multishot_dpram.vhd \
-../ip_cores/wb_ddr_fifo.vhd \
-../ip_cores/adc_serdes.vhd \
-../ip_cores/monostable/monostable_rtl.vhd \
-../ip_cores/utils/utils_pkg.vhd \
-../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd \
-../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
+../../ip_cores/adc_sync_fifo.vhd \
+../../ip_cores/multishot_dpram.vhd \
+../../ip_cores/wb_ddr_fifo.vhd \
+../../ip_cores/adc_serdes.vhd \
+../../ip_cores/monostable/monostable_rtl.vhd \
+../../ip_cores/utils/utils_pkg.vhd \
+../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd \
+../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
 ../rtl/carrier_csr.vhd \
-../rtl/utc_core_regs.vhd \
-../rtl/utc_core.vhd \
-../rtl/irq_controller_regs.vhd \
-../rtl/irq_controller.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
+../../ip_cores/timetag_core/rtl/timetag_core_pkg.vhd \
 ../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd \
-testbench/gn412x_bfm.vhd \
-../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
-../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
+../../adc/rtl/fmc_adc_mezzanine_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
+../rtl/sdb_meta_pkg.vhd \
 ../../adc/rtl/fmc_adc_100Ms_csr.vhd \
+../../adc/rtl/fmc_adc_eic.vhd \
 ../../adc/rtl/offset_gain_s.vhd \
-../rtl/sdb_meta_pkg.vhd \
-../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
-../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
-../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
-../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
-../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
-../ip_cores/general-cores/modules/common/gc_reset.vhd \
-../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
-../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
-../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
-../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
-../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
-../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd \
-../ip_cores/general-cores/modules/common/gc_wfifo.vhd \
+../../ip_cores/timetag_core/rtl/timetag_core_regs.vhd \
+../../ip_cores/timetag_core/rtl/timetag_core.vhd \
+../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
+testbench/gn412x_bfm.vhd \
+../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
+../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
+../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
+../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
+../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
+../../ip_cores/general-cores/modules/common/gc_reset.vhd \
+../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
+../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
+../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
+../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
+../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
+../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
+../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
+../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
+../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
+../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
 ../../adc/rtl/fmc_adc_100Ms_core.vhd \
-../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
-../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
-../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd \
-../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
-../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
-../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
-../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
-../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd \
-../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd \
-../ip_cores/general-cores/modules/genrams/xilinx/sim_stub/dummy.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
-../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
-../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
-../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
-../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
-../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
-../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
-../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd \
-../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd \
-../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd \
-../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
-../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd \
-../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd \
-../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd \
-../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd \
-../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd \
-../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd \
-../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd \
-../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
+../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
+../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
+../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
+../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
+../../adc/rtl/fmc_adc_mezzanine.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
+../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
+../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
+../rtl/dma_eic.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
+../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd \
+../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd \
+../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd \
+../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
+../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd \
+../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd \
+../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd \
+../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd \
+../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd \
+../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd \
+../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd \
+../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
 ../rtl/spec_top_fmc_adc_100Ms.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
-../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \

 VHDL_OBJ := work/util/.util_vhd \
 work/textutil/.textutil_vhd \
@@ -185,17 +204,20 @@ work/utils_pkg/.utils_pkg_vhd \
 work/ext_pulse_sync_rtl/.ext_pulse_sync_rtl_vhd \
 work/genram_pkg/.genram_pkg_vhd \
 work/carrier_csr/.carrier_csr_vhd \
-work/utc_core_regs/.utc_core_regs_vhd \
-work/utc_core/.utc_core_vhd \
-work/irq_controller_regs/.irq_controller_regs_vhd \
-work/irq_controller/.irq_controller_vhd \
+work/wbgen2_pkg/.wbgen2_pkg_vhd \
+work/timetag_core_pkg/.timetag_core_pkg_vhd \
 work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg_vhd \
-work/gn412x_bfm/.gn412x_bfm_vhd \
+work/fmc_adc_mezzanine_pkg/.fmc_adc_mezzanine_pkg_vhd \
 work/wishbone_pkg/.wishbone_pkg_vhd \
-work/gencores_pkg/.gencores_pkg_vhd \
+work/sdb_meta_pkg/.sdb_meta_pkg_vhd \
 work/fmc_adc_100Ms_csr/.fmc_adc_100Ms_csr_vhd \
+work/fmc_adc_eic/.fmc_adc_eic_vhd \
 work/offset_gain_s/.offset_gain_s_vhd \
-work/sdb_meta_pkg/.sdb_meta_pkg_vhd \
+work/timetag_core_regs/.timetag_core_regs_vhd \
+work/timetag_core/.timetag_core_vhd \
+work/gencores_pkg/.gencores_pkg_vhd \
+work/gn412x_bfm/.gn412x_bfm_vhd \
+work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg_vhd \
 work/gc_crc_gen/.gc_crc_gen_vhd \
 work/gc_moving_average/.gc_moving_average_vhd \
 work/gc_extend_pulse/.gc_extend_pulse_vhd \
@@ -206,20 +228,26 @@ work/gc_serial_dac/.gc_serial_dac_vhd \
 work/gc_sync_ffs/.gc_sync_ffs_vhd \
 work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd \
 work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd \
+work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2_vhd \
 work/gc_frequency_meter/.gc_frequency_meter_vhd \
-work/gc_dual_clock_ram/.gc_dual_clock_ram_vhd \
-work/gc_wfifo/.gc_wfifo_vhd \
+work/gc_rr_arbiter/.gc_rr_arbiter_vhd \
+work/gc_prio_encoder/.gc_prio_encoder_vhd \
+work/gc_word_packer/.gc_word_packer_vhd \
+work/gc_big_adder/.gc_big_adder_vhd \
 work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core_vhd \
 work/memory_loader_pkg/.memory_loader_pkg_vhd \
 work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd \
-work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg_vhd \
+work/inferred_sync_fifo/.inferred_sync_fifo_vhd \
+work/inferred_async_fifo/.inferred_async_fifo_vhd \
+work/fmc_adc_mezzanine/.fmc_adc_mezzanine_vhd \
 work/generic_dpram/.generic_dpram_vhd \
 work/generic_dpram_sameclock/.generic_dpram_sameclock_vhd \
 work/generic_dpram_dualclock/.generic_dpram_dualclock_vhd \
+work/generic_simple_dpram/.generic_simple_dpram_vhd \
 work/generic_spram/.generic_spram_vhd \
+work/gc_shiftreg/.gc_shiftreg_vhd \
 work/generic_async_fifo/.generic_async_fifo_vhd \
 work/generic_sync_fifo/.generic_sync_fifo_vhd \
-fifo_generator_v6_1/dummy/.dummy_vhd \
 work/wb_async_bridge/.wb_async_bridge_vhd \
 work/xwb_async_bridge/.xwb_async_bridge_vhd \
 work/wb_onewire_master/.wb_onewire_master_vhd \
@@ -243,7 +271,7 @@ work/simple_uart_wb/.simple_uart_wb_vhd \
 work/wb_simple_uart/.wb_simple_uart_vhd \
 work/xwb_simple_uart/.xwb_simple_uart_vhd \
 work/vic_prio_enc/.vic_prio_enc_vhd \
-work/wbgen2_pkg/.wbgen2_pkg_vhd \
+work/wb_slave_vic/.wb_slave_vic_vhd \
 work/wb_vic/.wb_vic_vhd \
 work/xwb_vic/.xwb_vic_vhd \
 work/wb_spi/.wb_spi_vhd \
@@ -251,20 +279,34 @@ work/xwb_spi/.xwb_spi_vhd \
 work/sdb_rom/.sdb_rom_vhd \
 work/xwb_crossbar/.xwb_crossbar_vhd \
 work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd \
+work/wb_irq_pkg/.wb_irq_pkg_vhd \
+work/irqm_core/.irqm_core_vhd \
+work/wb_irq_lm32/.wb_irq_lm32_vhd \
+work/wb_irq_slave/.wb_irq_slave_vhd \
+work/wb_irq_master/.wb_irq_master_vhd \
+work/wb_irq_timer/.wb_irq_timer_vhd \
 work/xwb_lm32/.xwb_lm32_vhd \
+work/lm32_dp_ram/.lm32_dp_ram_vhd \
+work/lm32_ram/.lm32_ram_vhd \
 work/wb_slave_adapter/.wb_slave_adapter_vhd \
-work/xloader_registers_pkg/.xloader_registers_pkg_vhd \
-work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd \
-work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd \
-work/xloader_wb/.xloader_wb_vhd \
 work/xwb_clock_crossing/.xwb_clock_crossing_vhd \
 work/xwb_dma/.xwb_dma_vhd \
+work/xwb_streamer/.xwb_streamer_vhd \
 work/wb_serial_lcd/.wb_serial_lcd_vhd \
+work/wb_spi_flash/.wb_spi_flash_vhd \
+work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg_vhd \
+work/simple_pwm_wb/.simple_pwm_wb_vhd \
+work/wb_simple_pwm/.wb_simple_pwm_vhd \
+work/xwb_simple_pwm/.xwb_simple_pwm_vhd \
 work/wbgen2_dpssram/.wbgen2_dpssram_vhd \
 work/wbgen2_eic/.wbgen2_eic_vhd \
 work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd \
 work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd \
-work/wb_slave_vic/.wb_slave_vic_vhd \
+work/dma_eic/.dma_eic_vhd \
+work/xloader_registers_pkg/.xloader_registers_pkg_vhd \
+work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd \
+work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd \
+work/xloader_wb/.xloader_wb_vhd \
 work/ddr3_ctrl/.ddr3_ctrl_vhd \
 work/ddr3_ctrl_wb/.ddr3_ctrl_wb_vhd \
 work/ddr3_ctrl_wrapper_pkg/.ddr3_ctrl_wrapper_pkg_vhd \
@@ -295,8 +337,8 @@ work/serdes_n_to_1_s2_diff/.serdes_n_to_1_s2_diff_vhd \
 work/serdes_n_to_1_s2_se/.serdes_n_to_1_s2_se_vhd \
 work/pulse_sync_rtl/.pulse_sync_rtl_vhd \

-LIBS := work fifo_generator_v6_1
-LIB_IND := work/.work fifo_generator_v6_1/.fifo_generator_v6_1
+LIBS := work
+LIB_IND := work/.work
 ## rules #################################
 sim: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
 $(VERILOG_OBJ): $(VHDL_OBJ) 
@@ -311,86 +353,73 @@ clean:
 work/.work:
 	(vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work 

-fifo_generator_v6_1/.fifo_generator_v6_1:
-	(vlib fifo_generator_v6_1 && vmap -modelsimini modelsim.ini fifo_generator_v6_1 && touch fifo_generator_v6_1/.fifo_generator_v6_1 )|| rm -rf fifo_generator_v6_1 
-
 work/ddr3/.ddr3_v: sim_models/2048Mb_ddr3/ddr3.v sim_models/2048Mb_ddr3/ddr3_parameters.vh
 		vlog -work work $(VLOG_FLAGS) +incdir+sim_models/2048Mb_ddr3 +incdir+sim_models/2048Mb_ddr3 +define+sg15E +define+x16 $<
 		@mkdir -p $(dir $@) && touch $@ 


-work/sockit_owm/.sockit_owm_v: ../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v 
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_onewire_master  $<
+work/sockit_owm/.sockit_owm_v: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v 
+		vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master  $<
 		@mkdir -p $(dir $@) && touch $@ 


-work/spi_clgen/.spi_clgen_v: ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v ../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_spi  $<
+work/spi_clgen/.spi_clgen_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
+		vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi  $<
 		@mkdir -p $(dir $@) && touch $@ 


-work/spi_shift/.spi_shift_v: ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v ../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_spi  $<
+work/spi_shift/.spi_shift_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
+		vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi  $<
 		@mkdir -p $(dir $@) && touch $@ 


-work/spi_top/.spi_top_v: ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v ../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_spi  $<
+work/spi_top/.spi_top_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
+		vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi  $<
 		@mkdir -p $(dir $@) && touch $@ 


-work/lm32_allprofiles/.lm32_allprofiles_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v 
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/generated  $<
+work/lm32_allprofiles/.lm32_allprofiles_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v 
+		vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated  $<
 		@mkdir -p $(dir $@) && touch $@ 


-work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
+work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
+		vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
 		@mkdir -p $(dir $@) && touch $@ 


-work/jtag_cores/.jtag_cores_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v 
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
+work/jtag_cores/.jtag_cores_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v 
+		vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
 		@mkdir -p $(dir $@) && touch $@ 


-work/lm32_adder/.lm32_adder_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
+work/lm32_adder/.lm32_adder_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
+		vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
 		@mkdir -p $(dir $@) && touch $@ 


-work/lm32_addsub/.lm32_addsub_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
+work/lm32_addsub/.lm32_addsub_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
+		vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
 		@mkdir -p $(dir $@) && touch $@ 


-work/lm32_dp_ram/.lm32_dp_ram_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v 
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
+work/lm32_logic_op/.lm32_logic_op_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
+		vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
 		@mkdir -p $(dir $@) && touch $@ 


-work/lm32_logic_op/.lm32_logic_op_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
+work/lm32_shifter/.lm32_shifter_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
+		vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
 		@mkdir -p $(dir $@) && touch $@ 


-work/lm32_ram/.lm32_ram_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
+work/lm32_multiplier/.lm32_multiplier_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v
+		vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic  $<
 		@mkdir -p $(dir $@) && touch $@ 


-work/lm32_shifter/.lm32_shifter_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
-		@mkdir -p $(dir $@) && touch $@ 
-
-
-work/lm32_multiplier/.lm32_multiplier_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v ../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic  $<
-		@mkdir -p $(dir $@) && touch $@ 
-
-
-work/jtag_tap/.jtag_tap_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v 
-		vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic  $<
+work/jtag_tap/.jtag_tap_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v 
+		vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic  $<
 		@mkdir -p $(dir $@) && touch $@ 


@@ -440,37 +469,37 @@ work/cmd_router1/.cmd_router1: \
 work/util/.util \
 work/textutil/.textutil

-work/adc_sync_fifo/.adc_sync_fifo_vhd: ../ip_cores/adc_sync_fifo.vhd
+work/adc_sync_fifo/.adc_sync_fifo_vhd: ../../ip_cores/adc_sync_fifo.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/multishot_dpram/.multishot_dpram_vhd: ../ip_cores/multishot_dpram.vhd
+work/multishot_dpram/.multishot_dpram_vhd: ../../ip_cores/multishot_dpram.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/wb_ddr_fifo/.wb_ddr_fifo_vhd: ../ip_cores/wb_ddr_fifo.vhd
+work/wb_ddr_fifo/.wb_ddr_fifo_vhd: ../../ip_cores/wb_ddr_fifo.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/adc_serdes/.adc_serdes_vhd: ../ip_cores/adc_serdes.vhd
+work/adc_serdes/.adc_serdes_vhd: ../../ip_cores/adc_serdes.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/monostable_rtl/.monostable_rtl_vhd: ../ip_cores/monostable/monostable_rtl.vhd
+work/monostable_rtl/.monostable_rtl_vhd: ../../ip_cores/monostable/monostable_rtl.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/utils_pkg/.utils_pkg_vhd: ../ip_cores/utils/utils_pkg.vhd
+work/utils_pkg/.utils_pkg_vhd: ../../ip_cores/utils/utils_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/ext_pulse_sync_rtl/.ext_pulse_sync_rtl_vhd: ../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd
+work/ext_pulse_sync_rtl/.ext_pulse_sync_rtl_vhd: ../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -478,7 +507,7 @@ work/ext_pulse_sync_rtl/.ext_pulse_sync_rtl_vhd: ../ip_cores/ext_pulse_sync/ext_
 work/ext_pulse_sync_rtl/.ext_pulse_sync_rtl: \
 work/utils_pkg/.utils_pkg

-work/genram_pkg/.genram_pkg_vhd: ../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
+work/genram_pkg/.genram_pkg_vhd: ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -488,76 +517,103 @@ work/carrier_csr/.carrier_csr_vhd: ../rtl/carrier_csr.vhd
 		@mkdir -p $(dir $@) && touch $@


-work/utc_core_regs/.utc_core_regs_vhd: ../rtl/utc_core_regs.vhd
+work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/utc_core/.utc_core_vhd: ../rtl/utc_core.vhd
+work/timetag_core_pkg/.timetag_core_pkg_vhd: ../../ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/irq_controller_regs/.irq_controller_regs_vhd: ../rtl/irq_controller_regs.vhd
+work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg_vhd: ../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/irq_controller/.irq_controller_vhd: ../rtl/irq_controller.vhd
+work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg: \
+work/timetag_core_pkg/.timetag_core_pkg
+
+work/fmc_adc_mezzanine_pkg/.fmc_adc_mezzanine_pkg_vhd: ../../adc/rtl/fmc_adc_mezzanine_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg_vhd: ../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd
+work/fmc_adc_mezzanine_pkg/.fmc_adc_mezzanine_pkg: \
+work/timetag_core_pkg/.timetag_core_pkg
+
+work/wishbone_pkg/.wishbone_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/gn412x_bfm/.gn412x_bfm_vhd: testbench/gn412x_bfm.vhd
+work/wishbone_pkg/.wishbone_pkg: \
+work/genram_pkg/.genram_pkg
+
+work/sdb_meta_pkg/.sdb_meta_pkg_vhd: ../rtl/sdb_meta_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/gn412x_bfm/.gn412x_bfm: \
-work/util/.util \
-work/mem_model/.mem_model \
-work/textutil/.textutil
+work/sdb_meta_pkg/.sdb_meta_pkg: \
+work/wishbone_pkg/.wishbone_pkg

-work/wishbone_pkg/.wishbone_pkg_vhd: ../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
+work/fmc_adc_100Ms_csr/.fmc_adc_100Ms_csr_vhd: ../../adc/rtl/fmc_adc_100Ms_csr.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/wishbone_pkg/.wishbone_pkg: \
-work/genram_pkg/.genram_pkg
+work/fmc_adc_eic/.fmc_adc_eic_vhd: ../../adc/rtl/fmc_adc_eic.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/fmc_adc_eic/.fmc_adc_eic: \
+work/wbgen2_pkg/.wbgen2_pkg

-work/gencores_pkg/.gencores_pkg_vhd: ../ip_cores/general-cores/modules/common/gencores_pkg.vhd
+work/offset_gain_s/.offset_gain_s_vhd: ../../adc/rtl/offset_gain_s.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/gencores_pkg/.gencores_pkg: \
-work/genram_pkg/.genram_pkg
+work/timetag_core_regs/.timetag_core_regs_vhd: ../../ip_cores/timetag_core/rtl/timetag_core_regs.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@

-work/fmc_adc_100Ms_csr/.fmc_adc_100Ms_csr_vhd: ../../adc/rtl/fmc_adc_100Ms_csr.vhd
+
+work/timetag_core/.timetag_core_vhd: ../../ip_cores/timetag_core/rtl/timetag_core.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/offset_gain_s/.offset_gain_s_vhd: ../../adc/rtl/offset_gain_s.vhd
+work/timetag_core/.timetag_core: \
+work/timetag_core_pkg/.timetag_core_pkg
+
+work/gencores_pkg/.gencores_pkg_vhd: ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/sdb_meta_pkg/.sdb_meta_pkg_vhd: ../rtl/sdb_meta_pkg.vhd
+work/gencores_pkg/.gencores_pkg: \
+work/genram_pkg/.genram_pkg
+
+work/gn412x_bfm/.gn412x_bfm_vhd: testbench/gn412x_bfm.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/sdb_meta_pkg/.sdb_meta_pkg: \
-work/wishbone_pkg/.wishbone_pkg
+work/gn412x_bfm/.gn412x_bfm: \
+work/util/.util \
+work/mem_model/.mem_model \
+work/textutil/.textutil

-work/gc_crc_gen/.gc_crc_gen_vhd: ../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
+work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg_vhd: ../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/gc_crc_gen/.gc_crc_gen_vhd: ../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -565,7 +621,7 @@ work/gc_crc_gen/.gc_crc_gen_vhd: ../ip_cores/general-cores/modules/common/gc_crc
 work/gc_crc_gen/.gc_crc_gen: \
 work/gencores_pkg/.gencores_pkg

-work/gc_moving_average/.gc_moving_average_vhd: ../ip_cores/general-cores/modules/common/gc_moving_average.vhd
+work/gc_moving_average/.gc_moving_average_vhd: ../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -573,15 +629,16 @@ work/gc_moving_average/.gc_moving_average_vhd: ../ip_cores/general-cores/modules
 work/gc_moving_average/.gc_moving_average: \
 work/gencores_pkg/.gencores_pkg

-work/gc_extend_pulse/.gc_extend_pulse_vhd: ../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
+work/gc_extend_pulse/.gc_extend_pulse_vhd: ../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


 work/gc_extend_pulse/.gc_extend_pulse: \
+work/genram_pkg/.genram_pkg \
 work/gencores_pkg/.gencores_pkg

-work/gc_delay_gen/.gc_delay_gen_vhd: ../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
+work/gc_delay_gen/.gc_delay_gen_vhd: ../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -589,7 +646,7 @@ work/gc_delay_gen/.gc_delay_gen_vhd: ../ip_cores/general-cores/modules/common/gc
 work/gc_delay_gen/.gc_delay_gen: \
 work/gencores_pkg/.gencores_pkg

-work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd: ../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
+work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd: ../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -597,22 +654,22 @@ work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd: ../ip_cores/general-cores
 work/gc_dual_pi_controller/.gc_dual_pi_controller: \
 work/gencores_pkg/.gencores_pkg

-work/gc_reset/.gc_reset_vhd: ../ip_cores/general-cores/modules/common/gc_reset.vhd
+work/gc_reset/.gc_reset_vhd: ../../ip_cores/general-cores/modules/common/gc_reset.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/gc_serial_dac/.gc_serial_dac_vhd: ../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
+work/gc_serial_dac/.gc_serial_dac_vhd: ../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/gc_sync_ffs/.gc_sync_ffs_vhd: ../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
+work/gc_sync_ffs/.gc_sync_ffs_vhd: ../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd: ../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
+work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd: ../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -621,7 +678,7 @@ work/gc_arbitrated_mux/.gc_arbitrated_mux: \
 work/genram_pkg/.genram_pkg \
 work/gencores_pkg/.gencores_pkg

-work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd: ../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
+work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd: ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -629,7 +686,15 @@ work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd: ../ip_cores/general-cores
 work/gc_pulse_synchronizer/.gc_pulse_synchronizer: \
 work/gencores_pkg/.gencores_pkg

-work/gc_frequency_meter/.gc_frequency_meter_vhd: ../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
+work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2_vhd: ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2: \
+work/gencores_pkg/.gencores_pkg
+
+work/gc_frequency_meter/.gc_frequency_meter_vhd: ../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -637,17 +702,31 @@ work/gc_frequency_meter/.gc_frequency_meter_vhd: ../ip_cores/general-cores/modul
 work/gc_frequency_meter/.gc_frequency_meter: \
 work/gencores_pkg/.gencores_pkg

-work/gc_dual_clock_ram/.gc_dual_clock_ram_vhd: ../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd
+work/gc_rr_arbiter/.gc_rr_arbiter_vhd: ../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/gc_prio_encoder/.gc_prio_encoder_vhd: ../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/gc_word_packer/.gc_word_packer_vhd: ../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/gc_wfifo/.gc_wfifo_vhd: ../ip_cores/general-cores/modules/common/gc_wfifo.vhd
+work/gc_word_packer/.gc_word_packer: \
+work/genram_pkg/.genram_pkg
+
+work/gc_big_adder/.gc_big_adder_vhd: ../../ip_cores/general-cores/modules/common/gc_big_adder.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/gc_wfifo/.gc_wfifo: \
+work/gc_big_adder/.gc_big_adder: \
+work/wishbone_pkg/.wishbone_pkg \
 work/gencores_pkg/.gencores_pkg

 work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core_vhd: ../../adc/rtl/fmc_adc_100Ms_core.vhd
@@ -656,9 +735,10 @@ work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core_vhd: ../../adc/rtl/fmc_adc_100Ms_cor


 work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core: \
-work/genram_pkg/.genram_pkg
+work/genram_pkg/.genram_pkg \
+work/timetag_core_pkg/.timetag_core_pkg

-work/memory_loader_pkg/.memory_loader_pkg_vhd: ../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
+work/memory_loader_pkg/.memory_loader_pkg_vhd: ../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -666,7 +746,7 @@ work/memory_loader_pkg/.memory_loader_pkg_vhd: ../ip_cores/general-cores/modules
 work/memory_loader_pkg/.memory_loader_pkg: \
 work/genram_pkg/.genram_pkg

-work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd: ../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
+work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -674,39 +754,69 @@ work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd: ../ip_cores/general-cores
 work/generic_shiftreg_fifo/.generic_shiftreg_fifo: \
 work/genram_pkg/.genram_pkg

-work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg_vhd: ../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd
+work/inferred_sync_fifo/.inferred_sync_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/generic_dpram/.generic_dpram_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
+work/inferred_sync_fifo/.inferred_sync_fifo: \
+work/genram_pkg/.genram_pkg
+
+work/inferred_async_fifo/.inferred_async_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/generic_dpram/.generic_dpram: \
-work/memory_loader_pkg/.memory_loader_pkg \
+work/inferred_async_fifo/.inferred_async_fifo: \
 work/genram_pkg/.genram_pkg

-work/generic_dpram_sameclock/.generic_dpram_sameclock_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
+work/fmc_adc_mezzanine/.fmc_adc_mezzanine_vhd: ../../adc/rtl/fmc_adc_mezzanine.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/fmc_adc_mezzanine/.fmc_adc_mezzanine: \
+work/wishbone_pkg/.wishbone_pkg \
+work/timetag_core_pkg/.timetag_core_pkg \
+work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg
+
+work/generic_dpram/.generic_dpram_vhd: ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/generic_dpram/.generic_dpram: \
+work/genram_pkg/.genram_pkg \
+work/memory_loader_pkg/.memory_loader_pkg
+
+work/generic_dpram_sameclock/.generic_dpram_sameclock_vhd: ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


 work/generic_dpram_sameclock/.generic_dpram_sameclock: \
-work/memory_loader_pkg/.memory_loader_pkg \
-work/genram_pkg/.genram_pkg
+work/genram_pkg/.genram_pkg \
+work/memory_loader_pkg/.memory_loader_pkg

-work/generic_dpram_dualclock/.generic_dpram_dualclock_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
+work/generic_dpram_dualclock/.generic_dpram_dualclock_vhd: ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


 work/generic_dpram_dualclock/.generic_dpram_dualclock: \
-work/memory_loader_pkg/.memory_loader_pkg \
-work/genram_pkg/.genram_pkg
+work/genram_pkg/.genram_pkg \
+work/memory_loader_pkg/.memory_loader_pkg
+
+work/generic_simple_dpram/.generic_simple_dpram_vhd: ../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+

-work/generic_spram/.generic_spram_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
+work/generic_simple_dpram/.generic_simple_dpram: \
+work/genram_pkg/.genram_pkg \
+work/memory_loader_pkg/.memory_loader_pkg
+
+work/generic_spram/.generic_spram_vhd: ../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -714,28 +824,31 @@ work/generic_spram/.generic_spram_vhd: ../ip_cores/general-cores/modules/genrams
 work/generic_spram/.generic_spram: \
 work/genram_pkg/.genram_pkg

-work/generic_async_fifo/.generic_async_fifo_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd
+work/gc_shiftreg/.gc_shiftreg_vhd: ../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/generic_async_fifo/.generic_async_fifo: \
+work/gc_shiftreg/.gc_shiftreg: \
 work/genram_pkg/.genram_pkg

-work/generic_sync_fifo/.generic_sync_fifo_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd
+work/generic_async_fifo/.generic_async_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/generic_sync_fifo/.generic_sync_fifo: \
+work/generic_async_fifo/.generic_async_fifo: \
 work/genram_pkg/.genram_pkg

-fifo_generator_v6_1/dummy/.dummy_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/sim_stub/dummy.vhd
-		vcom $(VCOM_FLAGS)  -work fifo_generator_v6_1 $< 
+work/generic_sync_fifo/.generic_sync_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/wb_async_bridge/.wb_async_bridge_vhd: ../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
+work/generic_sync_fifo/.generic_sync_fifo: \
+work/genram_pkg/.genram_pkg
+
+work/wb_async_bridge/.wb_async_bridge_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -744,7 +857,7 @@ work/wb_async_bridge/.wb_async_bridge: \
 work/wishbone_pkg/.wishbone_pkg \
 work/gencores_pkg/.gencores_pkg

-work/xwb_async_bridge/.xwb_async_bridge_vhd: ../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
+work/xwb_async_bridge/.xwb_async_bridge_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -752,7 +865,7 @@ work/xwb_async_bridge/.xwb_async_bridge_vhd: ../ip_cores/general-cores/modules/w
 work/xwb_async_bridge/.xwb_async_bridge: \
 work/wishbone_pkg/.wishbone_pkg

-work/wb_onewire_master/.wb_onewire_master_vhd: ../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
+work/wb_onewire_master/.wb_onewire_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -761,7 +874,7 @@ work/wb_onewire_master/.wb_onewire_master: \
 work/wishbone_pkg/.wishbone_pkg \
 work/gencores_pkg/.gencores_pkg

-work/xwb_onewire_master/.xwb_onewire_master_vhd: ../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
+work/xwb_onewire_master/.xwb_onewire_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -769,22 +882,22 @@ work/xwb_onewire_master/.xwb_onewire_master_vhd: ../ip_cores/general-cores/modul
 work/xwb_onewire_master/.xwb_onewire_master: \
 work/wishbone_pkg/.wishbone_pkg

-work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd: ../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
+work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd: ../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
+work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/i2c_master_top/.i2c_master_top_vhd: ../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
+work/i2c_master_top/.i2c_master_top_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/wb_i2c_master/.wb_i2c_master_vhd: ../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
+work/wb_i2c_master/.wb_i2c_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -792,7 +905,7 @@ work/wb_i2c_master/.wb_i2c_master_vhd: ../ip_cores/general-cores/modules/wishbon
 work/wb_i2c_master/.wb_i2c_master: \
 work/wishbone_pkg/.wishbone_pkg

-work/xwb_i2c_master/.xwb_i2c_master_vhd: ../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
+work/xwb_i2c_master/.xwb_i2c_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -800,7 +913,7 @@ work/xwb_i2c_master/.xwb_i2c_master_vhd: ../ip_cores/general-cores/modules/wishb
 work/xwb_i2c_master/.xwb_i2c_master: \
 work/wishbone_pkg/.wishbone_pkg

-work/xwb_bus_fanout/.xwb_bus_fanout_vhd: ../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
+work/xwb_bus_fanout/.xwb_bus_fanout_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -808,16 +921,16 @@ work/xwb_bus_fanout/.xwb_bus_fanout_vhd: ../ip_cores/general-cores/modules/wishb
 work/xwb_bus_fanout/.xwb_bus_fanout: \
 work/wishbone_pkg/.wishbone_pkg

-work/xwb_dpram/.xwb_dpram_vhd: ../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
+work/xwb_dpram/.xwb_dpram_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


 work/xwb_dpram/.xwb_dpram: \
-work/wishbone_pkg/.wishbone_pkg \
-work/genram_pkg/.genram_pkg
+work/genram_pkg/.genram_pkg \
+work/wishbone_pkg/.wishbone_pkg

-work/wb_gpio_port/.wb_gpio_port_vhd: ../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
+work/wb_gpio_port/.wb_gpio_port_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -826,7 +939,7 @@ work/wb_gpio_port/.wb_gpio_port: \
 work/wishbone_pkg/.wishbone_pkg \
 work/gencores_pkg/.gencores_pkg

-work/xwb_gpio_port/.xwb_gpio_port_vhd: ../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
+work/xwb_gpio_port/.xwb_gpio_port_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -834,7 +947,7 @@ work/xwb_gpio_port/.xwb_gpio_port_vhd: ../ip_cores/general-cores/modules/wishbon
 work/xwb_gpio_port/.xwb_gpio_port: \
 work/wishbone_pkg/.wishbone_pkg

-work/wb_tics/.wb_tics_vhd: ../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
+work/wb_tics/.wb_tics_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -842,7 +955,7 @@ work/wb_tics/.wb_tics_vhd: ../ip_cores/general-cores/modules/wishbone/wb_simple_
 work/wb_tics/.wb_tics: \
 work/wishbone_pkg/.wishbone_pkg

-work/xwb_tics/.xwb_tics_vhd: ../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
+work/xwb_tics/.xwb_tics_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -850,27 +963,27 @@ work/xwb_tics/.xwb_tics_vhd: ../ip_cores/general-cores/modules/wishbone/wb_simpl
 work/xwb_tics/.xwb_tics: \
 work/wishbone_pkg/.wishbone_pkg

-work/uart_async_rx/.uart_async_rx_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
+work/uart_async_rx/.uart_async_rx_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/uart_async_tx/.uart_async_tx_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
+work/uart_async_tx/.uart_async_tx_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/uart_baud_gen/.uart_baud_gen_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
+work/uart_baud_gen/.uart_baud_gen_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/simple_uart_pkg/.simple_uart_pkg_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
+work/simple_uart_pkg/.simple_uart_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/simple_uart_wb/.simple_uart_wb_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
+work/simple_uart_wb/.simple_uart_wb_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -878,17 +991,17 @@ work/simple_uart_wb/.simple_uart_wb_vhd: ../ip_cores/general-cores/modules/wishb
 work/simple_uart_wb/.simple_uart_wb: \
 work/simple_uart_pkg/.simple_uart_pkg

-work/wb_simple_uart/.wb_simple_uart_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
+work/wb_simple_uart/.wb_simple_uart_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


 work/wb_simple_uart/.wb_simple_uart: \
-work/simple_uart_pkg/.simple_uart_pkg \
+work/genram_pkg/.genram_pkg \
 work/wishbone_pkg/.wishbone_pkg \
-work/genram_pkg/.genram_pkg
+work/simple_uart_pkg/.simple_uart_pkg

-work/xwb_simple_uart/.xwb_simple_uart_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
+work/xwb_simple_uart/.xwb_simple_uart_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -896,25 +1009,29 @@ work/xwb_simple_uart/.xwb_simple_uart_vhd: ../ip_cores/general-cores/modules/wis
 work/xwb_simple_uart/.xwb_simple_uart: \
 work/wishbone_pkg/.wishbone_pkg

-work/vic_prio_enc/.vic_prio_enc_vhd: ../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
+work/vic_prio_enc/.vic_prio_enc_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/wbgen2_pkg/.wbgen2_pkg_vhd: ../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
+work/wb_slave_vic/.wb_slave_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/wb_vic/.wb_vic_vhd: ../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
+work/wb_slave_vic/.wb_slave_vic: \
+work/wbgen2_pkg/.wbgen2_pkg
+
+work/wb_vic/.wb_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


 work/wb_vic/.wb_vic: \
+work/genram_pkg/.genram_pkg \
 work/wishbone_pkg/.wishbone_pkg

-work/xwb_vic/.xwb_vic_vhd: ../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
+work/xwb_vic/.xwb_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -922,7 +1039,7 @@ work/xwb_vic/.xwb_vic_vhd: ../ip_cores/general-cores/modules/wishbone/wb_vic/xwb
 work/xwb_vic/.xwb_vic: \
 work/wishbone_pkg/.wishbone_pkg

-work/wb_spi/.wb_spi_vhd: ../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
+work/wb_spi/.wb_spi_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -930,7 +1047,7 @@ work/wb_spi/.wb_spi_vhd: ../ip_cores/general-cores/modules/wishbone/wb_spi/wb_sp
 work/wb_spi/.wb_spi: \
 work/wishbone_pkg/.wishbone_pkg

-work/xwb_spi/.xwb_spi_vhd: ../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
+work/xwb_spi/.xwb_spi_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -938,7 +1055,7 @@ work/xwb_spi/.xwb_spi_vhd: ../ip_cores/general-cores/modules/wishbone/wb_spi/xwb
 work/xwb_spi/.xwb_spi: \
 work/wishbone_pkg/.wishbone_pkg

-work/sdb_rom/.sdb_rom_vhd: ../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
+work/sdb_rom/.sdb_rom_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -946,7 +1063,7 @@ work/sdb_rom/.sdb_rom_vhd: ../ip_cores/general-cores/modules/wishbone/wb_crossba
 work/sdb_rom/.sdb_rom: \
 work/wishbone_pkg/.wishbone_pkg

-work/xwb_crossbar/.xwb_crossbar_vhd: ../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
+work/xwb_crossbar/.xwb_crossbar_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -954,7 +1071,7 @@ work/xwb_crossbar/.xwb_crossbar_vhd: ../ip_cores/general-cores/modules/wishbone/
 work/xwb_crossbar/.xwb_crossbar: \
 work/wishbone_pkg/.wishbone_pkg

-work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd: ../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
+work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -962,84 +1079,172 @@ work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd: ../ip_cores/general-cores/modules/w
 work/xwb_sdb_crossbar/.xwb_sdb_crossbar: \
 work/wishbone_pkg/.wishbone_pkg

-work/xwb_lm32/.xwb_lm32_vhd: ../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
+work/wb_irq_pkg/.wb_irq_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/xwb_lm32/.xwb_lm32: \
+work/wb_irq_pkg/.wb_irq_pkg: \
 work/wishbone_pkg/.wishbone_pkg

-work/wb_slave_adapter/.wb_slave_adapter_vhd: ../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
+work/irqm_core/.irqm_core_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/wb_slave_adapter/.wb_slave_adapter: \
+work/irqm_core/.irqm_core: \
+work/wb_irq_pkg/.wb_irq_pkg \
+work/genram_pkg/.genram_pkg \
 work/wishbone_pkg/.wishbone_pkg

-work/xloader_registers_pkg/.xloader_registers_pkg_vhd: ../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
+work/wb_irq_lm32/.wb_irq_lm32_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/xloader_registers_pkg/.xloader_registers_pkg: \
-work/wbgen2_pkg/.wbgen2_pkg
+work/wb_irq_lm32/.wb_irq_lm32: \
+work/wb_irq_pkg/.wb_irq_pkg \
+work/wishbone_pkg/.wishbone_pkg

-work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd: ../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
+work/wb_irq_slave/.wb_irq_slave_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader: \
+work/wb_irq_slave/.wb_irq_slave: \
+work/wb_irq_pkg/.wb_irq_pkg \
+work/genram_pkg/.genram_pkg \
 work/wishbone_pkg/.wishbone_pkg

-work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd: ../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
+work/wb_irq_master/.wb_irq_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader: \
+work/wb_irq_master/.wb_irq_master: \
+work/wb_irq_pkg/.wb_irq_pkg \
+work/genram_pkg/.genram_pkg \
+work/wishbone_pkg/.wishbone_pkg
+
+work/wb_irq_timer/.wb_irq_timer_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/wb_irq_timer/.wb_irq_timer: \
+work/wb_irq_pkg/.wb_irq_pkg \
+work/genram_pkg/.genram_pkg \
 work/wishbone_pkg/.wishbone_pkg \
-work/xloader_registers_pkg/.xloader_registers_pkg \
 work/gencores_pkg/.gencores_pkg

-work/xloader_wb/.xloader_wb_vhd: ../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd
+work/xwb_lm32/.xwb_lm32_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/xloader_wb/.xloader_wb: \
-work/xloader_registers_pkg/.xloader_registers_pkg \
-work/wbgen2_pkg/.wbgen2_pkg
+work/xwb_lm32/.xwb_lm32: \
+work/wishbone_pkg/.wishbone_pkg

-work/xwb_clock_crossing/.xwb_clock_crossing_vhd: ../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
+work/lm32_dp_ram/.lm32_dp_ram_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/lm32_dp_ram/.lm32_dp_ram: \
+work/genram_pkg/.genram_pkg
+
+work/lm32_ram/.lm32_ram_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/lm32_ram/.lm32_ram: \
+work/genram_pkg/.genram_pkg
+
+work/wb_slave_adapter/.wb_slave_adapter_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/wb_slave_adapter/.wb_slave_adapter: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/xwb_clock_crossing/.xwb_clock_crossing_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


 work/xwb_clock_crossing/.xwb_clock_crossing: \
-work/wishbone_pkg/.wishbone_pkg \
-work/gencores_pkg/.gencores_pkg
+work/genram_pkg/.genram_pkg \
+work/wishbone_pkg/.wishbone_pkg

-work/xwb_dma/.xwb_dma_vhd: ../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
+work/xwb_dma/.xwb_dma_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


 work/xwb_dma/.xwb_dma: \
+work/genram_pkg/.genram_pkg \
 work/wishbone_pkg/.wishbone_pkg

-work/wb_serial_lcd/.wb_serial_lcd_vhd: ../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
+work/xwb_streamer/.xwb_streamer_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_streamer/.xwb_streamer: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/wb_serial_lcd/.wb_serial_lcd_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


 work/wb_serial_lcd/.wb_serial_lcd: \
+work/genram_pkg/.genram_pkg \
+work/wishbone_pkg/.wishbone_pkg
+
+work/wb_spi_flash/.wb_spi_flash_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/wb_spi_flash/.wb_spi_flash: \
+work/genram_pkg/.genram_pkg \
 work/wishbone_pkg/.wishbone_pkg \
-work/genram_pkg/.genram_pkg
+work/gencores_pkg/.gencores_pkg
+
+work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/simple_pwm_wb/.simple_pwm_wb_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+

-work/wbgen2_dpssram/.wbgen2_dpssram_vhd: ../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
+work/simple_pwm_wb/.simple_pwm_wb: \
+work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg
+
+work/wb_simple_pwm/.wb_simple_pwm_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/wb_simple_pwm/.wb_simple_pwm: \
+work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg \
+work/wishbone_pkg/.wishbone_pkg
+
+work/xwb_simple_pwm/.xwb_simple_pwm_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_simple_pwm/.xwb_simple_pwm: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/wbgen2_dpssram/.wbgen2_dpssram_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -1047,7 +1252,7 @@ work/wbgen2_dpssram/.wbgen2_dpssram_vhd: ../ip_cores/general-cores/modules/wishb
 work/wbgen2_dpssram/.wbgen2_dpssram: \
 work/wbgen2_pkg/.wbgen2_pkg

-work/wbgen2_eic/.wbgen2_eic_vhd: ../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
+work/wbgen2_eic/.wbgen2_eic_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -1055,16 +1260,16 @@ work/wbgen2_eic/.wbgen2_eic_vhd: ../ip_cores/general-cores/modules/wishbone/wbge
 work/wbgen2_eic/.wbgen2_eic: \
 work/wbgen2_pkg/.wbgen2_pkg

-work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd: ../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
+work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


 work/wbgen2_fifo_async/.wbgen2_fifo_async: \
-work/genram_pkg/.genram_pkg \
-work/wbgen2_pkg/.wbgen2_pkg
+work/wbgen2_pkg/.wbgen2_pkg \
+work/genram_pkg/.genram_pkg

-work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd: ../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
+work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -1072,20 +1277,55 @@ work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd: ../ip_cores/general-cores/modules/w
 work/wbgen2_fifo_sync/.wbgen2_fifo_sync: \
 work/wbgen2_pkg/.wbgen2_pkg

-work/wb_slave_vic/.wb_slave_vic_vhd: ../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
+work/dma_eic/.dma_eic_vhd: ../rtl/dma_eic.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/wb_slave_vic/.wb_slave_vic: \
+work/dma_eic/.dma_eic: \
+work/wbgen2_pkg/.wbgen2_pkg
+
+work/xloader_registers_pkg/.xloader_registers_pkg_vhd: ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/xloader_registers_pkg/.xloader_registers_pkg: \
 work/wbgen2_pkg/.wbgen2_pkg

-work/ddr3_ctrl/.ddr3_ctrl_vhd: ../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd
+work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd: ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd: ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader: \
+work/wishbone_pkg/.wishbone_pkg \
+work/gencores_pkg/.gencores_pkg \
+work/xloader_registers_pkg/.xloader_registers_pkg
+
+work/xloader_wb/.xloader_wb_vhd: ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/xloader_wb/.xloader_wb: \
+work/wbgen2_pkg/.wbgen2_pkg \
+work/xloader_registers_pkg/.xloader_registers_pkg
+
+work/ddr3_ctrl/.ddr3_ctrl_vhd: ../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/ddr3_ctrl_wb/.ddr3_ctrl_wb_vhd: ../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd
+work/ddr3_ctrl_wb/.ddr3_ctrl_wb_vhd: ../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -1093,12 +1333,12 @@ work/ddr3_ctrl_wb/.ddr3_ctrl_wb_vhd: ../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl
 work/ddr3_ctrl_wb/.ddr3_ctrl_wb: \
 work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg

-work/ddr3_ctrl_wrapper_pkg/.ddr3_ctrl_wrapper_pkg_vhd: ../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd
+work/ddr3_ctrl_wrapper_pkg/.ddr3_ctrl_wrapper_pkg_vhd: ../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/ddr3_ctrl_wrapper/.ddr3_ctrl_wrapper_vhd: ../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd
+work/ddr3_ctrl_wrapper/.ddr3_ctrl_wrapper_vhd: ../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -1106,52 +1346,52 @@ work/ddr3_ctrl_wrapper/.ddr3_ctrl_wrapper_vhd: ../ip_cores/ddr3-sp6-core/hdl/rtl
 work/ddr3_ctrl_wrapper/.ddr3_ctrl_wrapper: \
 work/ddr3_ctrl_wrapper_pkg/.ddr3_ctrl_wrapper_pkg

-work/gn4124_core_pkg/.gn4124_core_pkg_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
+work/gn4124_core_pkg/.gn4124_core_pkg_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/ddr3_ctrl_spec_bank3_64b_32b/.ddr3_ctrl_spec_bank3_64b_32b_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd
+work/ddr3_ctrl_spec_bank3_64b_32b/.ddr3_ctrl_spec_bank3_64b_32b_vhd: ../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/memc3_infrastructure/.memc3_infrastructure_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd
+work/memc3_infrastructure/.memc3_infrastructure_vhd: ../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/memc3_wrapper/.memc3_wrapper_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd
+work/memc3_wrapper/.memc3_wrapper_vhd: ../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/iodrp_controller/.iodrp_controller_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd
+work/iodrp_controller/.iodrp_controller_vhd: ../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/iodrp_mcb_controller/.iodrp_mcb_controller_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd
+work/iodrp_mcb_controller/.iodrp_mcb_controller_vhd: ../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/mcb_raw_wrapper/.mcb_raw_wrapper_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd
+work/mcb_raw_wrapper/.mcb_raw_wrapper_vhd: ../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/mcb_soft_calibration_top/.mcb_soft_calibration_top_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd
+work/mcb_soft_calibration_top/.mcb_soft_calibration_top_vhd: ../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/mcb_soft_calibration/.mcb_soft_calibration_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd
+work/mcb_soft_calibration/.mcb_soft_calibration_vhd: ../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/dma_controller/.dma_controller_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd
+work/dma_controller/.dma_controller_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -1159,12 +1399,12 @@ work/dma_controller/.dma_controller_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/
 work/dma_controller/.dma_controller: \
 work/gn4124_core_pkg/.gn4124_core_pkg

-work/dma_controller_wb_slave/.dma_controller_wb_slave_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd
+work/dma_controller_wb_slave/.dma_controller_wb_slave_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/l2p_arbiter/.l2p_arbiter_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd
+work/l2p_arbiter/.l2p_arbiter_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -1172,7 +1412,7 @@ work/l2p_arbiter/.l2p_arbiter_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2
 work/l2p_arbiter/.l2p_arbiter: \
 work/gn4124_core_pkg/.gn4124_core_pkg

-work/l2p_dma_master/.l2p_dma_master_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd
+work/l2p_dma_master/.l2p_dma_master_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -1181,7 +1421,7 @@ work/l2p_dma_master/.l2p_dma_master: \
 work/gn4124_core_pkg/.gn4124_core_pkg \
 work/genram_pkg/.genram_pkg

-work/p2l_decode32/.p2l_decode32_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd
+work/p2l_decode32/.p2l_decode32_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -1189,7 +1429,7 @@ work/p2l_decode32/.p2l_decode32_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/
 work/p2l_decode32/.p2l_decode32: \
 work/gn4124_core_pkg/.gn4124_core_pkg

-work/p2l_dma_master/.p2l_dma_master_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd
+work/p2l_dma_master/.p2l_dma_master_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -1198,7 +1438,7 @@ work/p2l_dma_master/.p2l_dma_master: \
 work/gn4124_core_pkg/.gn4124_core_pkg \
 work/genram_pkg/.genram_pkg

-work/wbmaster32/.wbmaster32_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd
+work/wbmaster32/.wbmaster32_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -1207,7 +1447,7 @@ work/wbmaster32/.wbmaster32: \
 work/gn4124_core_pkg/.gn4124_core_pkg \
 work/genram_pkg/.genram_pkg

-work/gn4124_core/.gn4124_core_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
+work/gn4124_core/.gn4124_core_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -1221,14 +1461,15 @@ work/spec_top_fmc_adc_100Ms/.spec_top_fmc_adc_100Ms_vhd: ../rtl/spec_top_fmc_adc


 work/spec_top_fmc_adc_100Ms/.spec_top_fmc_adc_100Ms: \
-work/wishbone_pkg/.wishbone_pkg \
-work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg \
 work/gn4124_core_pkg/.gn4124_core_pkg \
-work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg \
+work/wishbone_pkg/.wishbone_pkg \
+work/timetag_core_pkg/.timetag_core_pkg \
+work/fmc_adc_mezzanine_pkg/.fmc_adc_mezzanine_pkg \
 work/sdb_meta_pkg/.sdb_meta_pkg \
+work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg \
 work/gencores_pkg/.gencores_pkg

-work/l2p_ser/.l2p_ser_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd
+work/l2p_ser/.l2p_ser_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -1236,7 +1477,7 @@ work/l2p_ser/.l2p_ser_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l
 work/l2p_ser/.l2p_ser: \
 work/gn4124_core_pkg/.gn4124_core_pkg

-work/p2l_des/.p2l_des_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd
+work/p2l_des/.p2l_des_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -1244,27 +1485,27 @@ work/p2l_des/.p2l_des_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p
 work/p2l_des/.p2l_des: \
 work/gn4124_core_pkg/.gn4124_core_pkg

-work/serdes_1_to_n_clk_pll_s2_diff/.serdes_1_to_n_clk_pll_s2_diff_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
+work/serdes_1_to_n_clk_pll_s2_diff/.serdes_1_to_n_clk_pll_s2_diff_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/serdes_1_to_n_data_s2_se/.serdes_1_to_n_data_s2_se_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd
+work/serdes_1_to_n_data_s2_se/.serdes_1_to_n_data_s2_se_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/serdes_n_to_1_s2_diff/.serdes_n_to_1_s2_diff_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd
+work/serdes_n_to_1_s2_diff/.serdes_n_to_1_s2_diff_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/serdes_n_to_1_s2_se/.serdes_n_to_1_s2_se_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd
+work/serdes_n_to_1_s2_se/.serdes_n_to_1_s2_se_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/pulse_sync_rtl/.pulse_sync_rtl_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd
+work/pulse_sync_rtl/.pulse_sync_rtl_vhd: ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


--- a/hdl/spec/sim/Manifest.py
+++ b/hdl/spec/sim/Manifest.py
@@ -7,14 +7,21 @@ files = ["testbench/gn412x_bfm.vhd",
         "testbench/util.vhd",
         "testbench/tb_spec.vhd",
         "testbench/cmd_router1.vhd",
-         "../ip_cores/adc_sync_fifo.vhd",
-         "../ip_cores/multishot_dpram.vhd",
-         "../ip_cores/wb_ddr_fifo.vhd",
-         "../ip_cores/adc_serdes.vhd",
-         "../ip_cores/monostable/monostable_rtl.vhd",
-         "../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd",
-         "../ip_cores/utils/utils_pkg.vhd"]
+         "../../ip_cores/adc_sync_fifo.vhd",
+         "../../ip_cores/multishot_dpram.vhd",
+         "../../ip_cores/wb_ddr_fifo.vhd",
+         "../../ip_cores/adc_serdes.vhd",
+         "../../ip_cores/monostable/monostable_rtl.vhd",
+         "../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd",
+         "../../ip_cores/utils/utils_pkg.vhd"]

 modules = { "local" : ["../rtl",
+                       "../../adc/rtl",
+                       "../../ip_cores/timetag_core/rtl",
                       "testbench",
-                       "sim_models/2048Mb_ddr3"]}
+                       "sim_models/2048Mb_ddr3"],
+            "git" : ["git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master",
+                     "git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::spec_bank3_64b_32b",
+                     "git://ohwr.org/hdl-core-lib/gn4124-core.git::master"]}
+
+fetchto="../../ip_cores"
--- a/hdl/spec/sim/cmd0.vec
+++ b/hdl/spec/sim/cmd0.vec
@@ -209,86 +209,106 @@ wait %d2000


 -- onewire config
-wr FF00000000001A04 F 007C0270
+wr FF00000000001104 F 007C0270
 wait %d100
-wr FF00000000001A00 F 0000000A
+wr FF00000000001100 F 0000000A
 wait %d100

-- irq mask
-wr FF00000000001508 F 0000000F
+-- fmc eic set irq enable mask
+wr FF00000000002004 F 00000003
+
+-- dma eic set irq enable mask
+wr FF00000000001404 F 00000003
+
+-- vic set irq enable mask
+wr FF00000000001308 F 00000003
+
+-- vic config
+wr FF00000000001300 F 00001777
+
+-- release fmc reset
+wr FF0000000000120C F 00000003
+
+-- Set time-tag core seconds
+wr FF00000000002100 F 00001234
+
+-- Set time-tag core coarse time
+wr FF00000000002104 F 00000000
+

 -- trigger config (sw trig enable)
-wr FF00000000001908 F 00000008
+wr FF00000000005308 F 00000008
 -- trigger config (hw int trig enable)
--wr FF00000000001908 F 00000004
-
+--wr FF00000000005308 F 00000004
 -- trigger config (int trig)
--wr FF00000000001908 F 02600004
+--wr FF00000000005308 F 02600004

 -- decimation factor = 1
-wr FF0000000000191C F 00000001
+wr FF0000000000531C F 00000001

 -- pre-trig samples
-wr FF00000000001920 F 00000100
+wr FF00000000005320 F 00000000

 -- post-trig samples
-wr FF00000000001924 F 00001000
+wr FF00000000005324 F 00000001

 -- number of shots
-wr FF00000000001914 F 00000001
+wr FF00000000005314 F 00000003

 -- Channel 1 gain
-wr FF00000000001934 F 00008000
+wr FF00000000005334 F 00008000
 -- Channel 1 offset
-wr FF00000000001938 F 00000000
+wr FF00000000005338 F 00000000

 -- Channel 2 gain
-wr FF00000000001944 F 00008000
+wr FF00000000005344 F 00008000
 -- Channel 2 offset
-wr FF00000000001948 F 00000000
+wr FF00000000005348 F 00000000

 -- Channel 3 gain
-wr FF00000000001954 F 00008000
+wr FF00000000005354 F 00008000
 -- Channel 3 offset
-wr FF00000000001958 F 00000000
+wr FF00000000005358 F 00000000

 -- Channel 4 gain
-wr FF00000000001964 F 00008000
+wr FF00000000005364 F 00008000
 -- Channel 4 offset
-wr FF00000000001968 F 00000000
+wr FF00000000005368 F 00000000

 -- Enable test data and sampling clock
--wr FF00000000001900 F 00000024
+--wr FF00000000005300 F 00000024
 -- Enable sampling clock
-wr FF00000000001900 F 00000004
+wr FF00000000005300 F 00000004
+
+wait   %d2000

 -- start acquisition
--wr FF00000000001900 F 00000025
-wr FF00000000001900 F 00000005
+--wr FF00000000005300 F 00000025
+wr FF00000000005300 F 00000005

 wait   %d800
 -- sw trigger
-wr FF00000000001910 F FFFFFFFF
+wr FF00000000005310 F FFFFFFFF

 wait   %d800
 -- stop acquisition
-wr FF00000000001900 F 00000006
+--wr FF00000000005300 F 00000006

 wait   %d800
 -- sw trigger
--wr FF00000000001910 F FFFFFFFF
+wr FF00000000005310 F FFFFFFFF

 wait   %d800
 -- sw trigger
--wr FF00000000001910 F FFFFFFFF
+wr FF00000000005310 F FFFFFFFF

 wait   %d800
 -- sw trigger
--wr FF00000000001910 F FFFFFFFF
+--wr FF00000000005310 F FFFFFFFF

 wait   %d800
 -- sw trigger
--wr FF00000000001910 F FFFFFFFF
+--wr FF00000000005310 F FFFFFFFF

 wait %d1000

@@ -316,11 +336,11 @@ wait %d3000
 ---------------------------------------------

 -- start acquisition
--wr FF00000000001900 F 00000001
+--wr FF00000000005300 F 00000001

 wait   %d500
 -- sw trigger
--wr FF00000000001910 F FFFFFFFF
+--wr FF00000000005310 F FFFFFFFF

 wait %d400


--- a/hdl/spec/sim/spec.do
+++ b/hdl/spec/sim/spec.do
@@ -7,8 +7,9 @@ log -r /*
 ##do wave_onewire.do
 ##do wave_adc_core.do
 ##do wave_gnum.do
-do wave_end_acq_irq.do
+##do wave_end_acq_irq.do
 ##do wave_ddr_wb.do
+do wave_trig_tag.do

 view wave
 view transcript

--- a/hdl/spec/sim/testbench/tb_spec.vhd
+++ b/hdl/spec/sim/testbench/tb_spec.vhd
@@ -227,45 +227,45 @@ architecture TEST of TB_SPEC is
        DDR3_RZQ     : inout std_logic;

        -- FMC slot
-        ext_trigger_p_i : in std_logic;  -- External trigger
-        ext_trigger_n_i : in std_logic;
-
-        adc_dco_p_i  : in std_logic;                     -- ADC data clock
-        adc_dco_n_i  : in std_logic;
-        adc_fr_p_i   : in std_logic;                     -- ADC frame start
-        adc_fr_n_i   : in std_logic;
-        adc_outa_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (odd bits)
-        adc_outa_n_i : in std_logic_vector(3 downto 0);
-        adc_outb_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (even bits)
-        adc_outb_n_i : in std_logic_vector(3 downto 0);
-
-        spi_din_i       : in  std_logic;  -- SPI data from FMC
-        spi_dout_o      : out std_logic;  -- SPI data to FMC
-        spi_sck_o       : out std_logic;  -- SPI clock
-        spi_cs_adc_n_o  : out std_logic;  -- SPI ADC chip select (active low)
-        spi_cs_dac1_n_o : out std_logic;  -- SPI channel 1 offset DAC chip select (active low)
-        spi_cs_dac2_n_o : out std_logic;  -- SPI channel 2 offset DAC chip select (active low)
-        spi_cs_dac3_n_o : out std_logic;  -- SPI channel 3 offset DAC chip select (active low)
-        spi_cs_dac4_n_o : out std_logic;  -- SPI channel 4 offset DAC chip select (active low)
-
-        gpio_dac_clr_n_o : out std_logic;                     -- offset DACs clear (active low)
-        gpio_led_acq_o   : out std_logic;                     -- Mezzanine front panel power LED (PWR)
-        gpio_led_trig_o  : out std_logic;                     -- Mezzanine front panel trigger LED (TRIG)
-        gpio_ssr_ch1_o   : out std_logic_vector(6 downto 0);  -- Channel 1 solid state relays control
-        gpio_ssr_ch2_o   : out std_logic_vector(6 downto 0);  -- Channel 2 solid state relays control
-        gpio_ssr_ch3_o   : out std_logic_vector(6 downto 0);  -- Channel 3 solid state relays control
-        gpio_ssr_ch4_o   : out std_logic_vector(6 downto 0);  -- Channel 4 solid state relays control
-        gpio_si570_oe_o  : out std_logic;                     -- Si570 (programmable oscillator) output enable
-
-        si570_scl_b : inout std_logic;  -- I2C bus clock (Si570)
-        si570_sda_b : inout std_logic;  -- I2C bus data (Si570)
-
-        mezz_one_wire_b : inout std_logic;  -- 1-wire interface (DS18B20 thermometer + unique ID)
-
-        prsnt_m2c_n_i : in std_logic;   -- Mezzanine present (active low)
-
-        sys_scl_b : inout std_logic;    -- Mezzanine system I2C clock (EEPROM)
-        sys_sda_b : inout std_logic     -- Mezzanine system I2C data (EEPROM)
+        adc0_ext_trigger_p_i : in std_logic;  -- External trigger
+        adc0_ext_trigger_n_i : in std_logic;
+
+        adc0_dco_p_i  : in std_logic;                     -- ADC data clock
+        adc0_dco_n_i  : in std_logic;
+        adc0_fr_p_i   : in std_logic;                     -- ADC frame start
+        adc0_fr_n_i   : in std_logic;
+        adc0_outa_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (odd bits)
+        adc0_outa_n_i : in std_logic_vector(3 downto 0);
+        adc0_outb_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (even bits)
+        adc0_outb_n_i : in std_logic_vector(3 downto 0);
+
+        adc0_spi_din_i       : in  std_logic;  -- SPI data from FMC
+        adc0_spi_dout_o      : out std_logic;  -- SPI data to FMC
+        adc0_spi_sck_o       : out std_logic;  -- SPI clock
+        adc0_spi_cs_adc_n_o  : out std_logic;  -- SPI ADC chip select (active low)
+        adc0_spi_cs_dac1_n_o : out std_logic;  -- SPI channel 1 offset DAC chip select (active low)
+        adc0_spi_cs_dac2_n_o : out std_logic;  -- SPI channel 2 offset DAC chip select (active low)
+        adc0_spi_cs_dac3_n_o : out std_logic;  -- SPI channel 3 offset DAC chip select (active low)
+        adc0_spi_cs_dac4_n_o : out std_logic;  -- SPI channel 4 offset DAC chip select (active low)
+
+        adc0_gpio_dac_clr_n_o : out std_logic;                     -- offset DACs clear (active low)
+        adc0_gpio_led_acq_o   : out std_logic;                     -- Mezzanine front panel power LED (PWR)
+        adc0_gpio_led_trig_o  : out std_logic;                     -- Mezzanine front panel trigger LED (TRIG)
+        adc0_gpio_ssr_ch1_o   : out std_logic_vector(6 downto 0);  -- Channel 1 solid state relays control
+        adc0_gpio_ssr_ch2_o   : out std_logic_vector(6 downto 0);  -- Channel 2 solid state relays control
+        adc0_gpio_ssr_ch3_o   : out std_logic_vector(6 downto 0);  -- Channel 3 solid state relays control
+        adc0_gpio_ssr_ch4_o   : out std_logic_vector(6 downto 0);  -- Channel 4 solid state relays control
+        adc0_gpio_si570_oe_o  : out std_logic;                     -- Si570 (programmable oscillator) output enable
+
+        adc0_si570_scl_b : inout std_logic;  -- I2C bus clock (Si570)
+        adc0_si570_sda_b : inout std_logic;  -- I2C bus data (Si570)
+
+        adc0_one_wire_b : inout std_logic;  -- 1-wire interface (DS18B20 thermometer + unique ID)
+
+        fmc0_prsnt_m2c_n_i : in std_logic;   -- Mezzanine present (active low)
+
+        fmc0_sys_scl_b : inout std_logic;    -- Mezzanine system I2C clock (EEPROM)
+        fmc0_sys_sda_b : inout std_logic     -- Mezzanine system I2C data (EEPROM)
        );
  end component spec_top_fmc_adc_100Ms;

@@ -615,45 +615,45 @@ begin
      gpio       => GPIO(9 downto 8),   -- General Purpose Input/Output

      -- FMC slot
-      ext_trigger_p_i => ext_trigger_p_i,
-      ext_trigger_n_i => ext_trigger_n_i,
-
-      adc_dco_p_i  => adc_dco_p_i,
-      adc_dco_n_i  => adc_dco_n_i,
-      adc_fr_p_i   => adc_fr_p_i,
-      adc_fr_n_i   => adc_fr_n_i,
-      adc_outa_p_i => adc_outa_p_i,
-      adc_outa_n_i => adc_outa_n_i,
-      adc_outb_p_i => adc_outb_p_i,
-      adc_outb_n_i => adc_outb_n_i,
-
-      spi_din_i       => spi_din_i,
-      spi_dout_o      => spi_dout_o,
-      spi_sck_o       => spi_sck_o,
-      spi_cs_adc_n_o  => spi_cs_adc_n_o ,
-      spi_cs_dac1_n_o => spi_cs_dac1_n_o,
-      spi_cs_dac2_n_o => spi_cs_dac2_n_o,
-      spi_cs_dac3_n_o => spi_cs_dac3_n_o,
-      spi_cs_dac4_n_o => spi_cs_dac4_n_o,
-
-      gpio_dac_clr_n_o => gpio_dac_clr_n_o,
-      gpio_led_acq_o   => gpio_led_acq_o,
-      gpio_led_trig_o  => gpio_led_trig_o,
-      gpio_ssr_ch1_o   => gpio_ssr_ch1_o,
-      gpio_ssr_ch2_o   => gpio_ssr_ch2_o,
-      gpio_ssr_ch3_o   => gpio_ssr_ch3_o,
-      gpio_ssr_ch4_o   => gpio_ssr_ch4_o,
-      gpio_si570_oe_o  => gpio_si570_oe_o,
-
-      si570_scl_b => si570_scl_b,
-      si570_sda_b => si570_sda_b,
-
-      mezz_one_wire_b => mezz_one_wire_b,
-
-      prsnt_m2c_n_i => prsnt_m2c_n_i,
-
-      sys_scl_b => sys_scl_b,
-      sys_sda_b => sys_sda_b,
+      adc0_ext_trigger_p_i => ext_trigger_p_i,
+      adc0_ext_trigger_n_i => ext_trigger_n_i,
+
+      adc0_dco_p_i  => adc_dco_p_i,
+      adc0_dco_n_i  => adc_dco_n_i,
+      adc0_fr_p_i   => adc_fr_p_i,
+      adc0_fr_n_i   => adc_fr_n_i,
+      adc0_outa_p_i => adc_outa_p_i,
+      adc0_outa_n_i => adc_outa_n_i,
+      adc0_outb_p_i => adc_outb_p_i,
+      adc0_outb_n_i => adc_outb_n_i,
+
+      adc0_spi_din_i       => spi_din_i,
+      adc0_spi_dout_o      => spi_dout_o,
+      adc0_spi_sck_o       => spi_sck_o,
+      adc0_spi_cs_adc_n_o  => spi_cs_adc_n_o ,
+      adc0_spi_cs_dac1_n_o => spi_cs_dac1_n_o,
+      adc0_spi_cs_dac2_n_o => spi_cs_dac2_n_o,
+      adc0_spi_cs_dac3_n_o => spi_cs_dac3_n_o,
+      adc0_spi_cs_dac4_n_o => spi_cs_dac4_n_o,
+
+      adc0_gpio_dac_clr_n_o => gpio_dac_clr_n_o,
+      adc0_gpio_led_acq_o   => gpio_led_acq_o,
+      adc0_gpio_led_trig_o  => gpio_led_trig_o,
+      adc0_gpio_ssr_ch1_o   => gpio_ssr_ch1_o,
+      adc0_gpio_ssr_ch2_o   => gpio_ssr_ch2_o,
+      adc0_gpio_ssr_ch3_o   => gpio_ssr_ch3_o,
+      adc0_gpio_ssr_ch4_o   => gpio_ssr_ch4_o,
+      adc0_gpio_si570_oe_o  => gpio_si570_oe_o,
+
+      adc0_si570_scl_b => si570_scl_b,
+      adc0_si570_sda_b => si570_sda_b,
+
+      adc0_one_wire_b => mezz_one_wire_b,
+
+      fmc0_prsnt_m2c_n_i => prsnt_m2c_n_i,
+
+      fmc0_sys_scl_b => sys_scl_b,
+      fmc0_sys_sda_b => sys_sda_b,

      -- DDR3 interface
      ddr3_a       => ddr3_a_o,

--- a/hdl/spec/wb_gen/carrier_csr.h
+++ b/hdl/spec/wb_gen/carrier_csr.h
@@ -3,7 +3,7 @@

  * File           : carrier_csr.h
  * Author         : auto-generated by wbgen2 from carrier_csr.wb
-  * Created        : Thu Aug  8 14:54:22 2013
+  * Created        : Wed Dec 11 11:55:04 2013
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb

--- a/hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
+++ b/hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
@@ -321,13 +321,13 @@ architecture rtl of svec_top_fmc_adc_100Ms is
  constant c_WB_SLAVE_VIC          : integer := 3;   -- Vectored interrupt controller
  constant c_WB_SLAVE_FMC0_EIC     : integer := 4;   -- FMC slot 1 interrupt controller
  constant c_WB_SLAVE_FMC0_TIMETAG : integer := 5;   -- FMC slot 1 timetag core
-  constant c_WB_SLAVE_FMC0_DDR_DAT : integer := 6;   -- FMC slot 1 DDR data
-  constant c_WB_SLAVE_FMC0_DDR_ADR : integer := 7;   -- FMC slot 1 DDR address
+  constant c_WB_SLAVE_FMC0_DDR_ADR : integer := 6;   -- FMC slot 1 DDR address
+  constant c_WB_SLAVE_FMC0_DDR_DAT : integer := 7;   -- FMC slot 1 DDR data
  constant c_WB_SLAVE_FMC0_ADC     : integer := 8;   -- FMC slot 1 ADC mezzanine
  constant c_WB_SLAVE_FMC1_EIC     : integer := 9;   -- FMC slot 2 interrupt controller
  constant c_WB_SLAVE_FMC1_TIMETAG : integer := 10;  -- FMC slot 2 timetag core
-  constant c_WB_SLAVE_FMC1_DDR_DAT : integer := 11;  -- FMC slot 2 DDR data
-  constant c_WB_SLAVE_FMC1_DDR_ADR : integer := 12;  -- FMC slot 2 DDR address
+  constant c_WB_SLAVE_FMC1_DDR_ADR : integer := 11;  -- FMC slot 2 DDR address
+  constant c_WB_SLAVE_FMC1_DDR_DAT : integer := 12;  -- FMC slot 2 DDR data
  constant c_WB_SLAVE_FMC1_ADC     : integer := 13;  -- FMC slot 2 ADC mezzanine


@@ -413,9 +413,9 @@ architecture rtl of svec_top_fmc_adc_100Ms is
        name      => "WB-DDR-Addr-Access ")));

  -- f_xwb_bridge_manual_sdb(size, sdb_addr)
-  -- Note: sdb_addr is the sdb records address relative to the parent interconnect
-  constant c_fmc0_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00004000");
-  constant c_fmc1_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00008000");
+  -- Note: sdb_addr is the sdb records address relative to the bridge base address
+  constant c_fmc0_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
+  constant c_fmc1_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");

  -- sdb header address
  constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
@@ -552,18 +552,18 @@ architecture rtl of svec_top_fmc_adc_100Ms is
  signal led_state_man : std_logic_vector(15 downto 0);

  -- DDR0 (bank 4)
-  signal ddr0_status     : std_logic_vector(31 downto 0);
-  signal ddr0_calib_done : std_logic;
-  signal ddr0_addr_cnt   : unsigned(31 downto 0);
-  signal ddr0_wb_cyc_d   : std_logic;
-  signal ddr0_wb_cyc_fe  : std_logic;
+  signal ddr0_status      : std_logic_vector(31 downto 0);
+  signal ddr0_calib_done  : std_logic;
+  signal ddr0_addr_cnt    : unsigned(31 downto 0);
+  signal ddr0_dat_cyc_d   : std_logic;
+  signal ddr0_addr_cnt_en : std_logic;

  -- DDR1 (bank 5)
  signal ddr1_status     : std_logic_vector(31 downto 0);
  signal ddr1_calib_done : std_logic;
  signal ddr1_addr_cnt   : unsigned(31 downto 0);
-  signal ddr1_wb_cyc_d   : std_logic;
-  signal ddr1_wb_cyc_fe  : std_logic;
+  signal ddr1_dat_cyc_d   : std_logic;
+  signal ddr1_addr_cnt_en   : std_logic;

  -- Carrier 1-wire
  signal carrier_owr_en : std_logic_vector(0 downto 0);
@@ -582,6 +582,8 @@ architecture rtl of svec_top_fmc_adc_100Ms is
  signal acq_start_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
  signal acq_stop_p  : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
  signal acq_end_p   : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
+  signal fmc0_trigger_tag : t_timetag;
+  signal fmc1_trigger_tag : t_timetag;

  -- led pwm
  signal led_pwm_update_cnt : unsigned(9 downto 0);
@@ -936,7 +938,7 @@ begin
  ------------------------------------------------------------------------------
  cmp_fmc0_eic : fmc_adc_eic
    port map(
-      rst_n_i       => sys_rst_n,
+      rst_n_i       => fmc0_rst_n,
      clk_sys_i     => sys_clk_125,
      wb_adr_i      => cnx_master_out(c_WB_SLAVE_FMC0_EIC).adr(3 downto 2),  -- cnx_master_out.adr is byte address
      wb_dat_i      => cnx_master_out(c_WB_SLAVE_FMC0_EIC).dat,
@@ -962,7 +964,7 @@ begin
  ------------------------------------------------------------------------------
  cmp_fmc1_eic : fmc_adc_eic
    port map(
-      rst_n_i       => sys_rst_n,
+      rst_n_i       => fmc1_rst_n,
      clk_sys_i     => sys_clk_125,
      wb_adr_i      => cnx_master_out(c_WB_SLAVE_FMC1_EIC).adr(3 downto 2),  -- cnx_master_out.adr is byte address
      wb_dat_i      => cnx_master_out(c_WB_SLAVE_FMC1_EIC).dat,
@@ -992,7 +994,7 @@ begin
    p_ddr_wr_fifo_empty : process (sys_clk_125)
    begin
      if rising_edge(sys_clk_125) then
-        if sys_rst_n = '0' then
+        if fmc0_rst_n = '0' or fmc1_rst_n = '0' then
          ddr_wr_fifo_empty_d(I)  <= '0';
          ddr_wr_fifo_empty_d1(I) <= '0';
        else
@@ -1009,7 +1011,7 @@ begin
    p_acq_end_extend : process (sys_clk_125)
    begin
      if rising_edge(sys_clk_125) then
-        if sys_rst_n = '0' then
+        if fmc0_rst_n = '0' or fmc1_rst_n = '0' then
          acq_end_extend(I) <= '0';
        elsif acq_end_p(I) = '1' then
          acq_end_extend(I) <= '1';
@@ -1063,6 +1065,8 @@ begin
      acq_stop_p_o  => acq_stop_p(0),
      acq_end_p_o   => acq_end_p(0),

+      trigger_tag_i => fmc0_trigger_tag,
+
      ext_trigger_p_i => adc0_ext_trigger_p_i,
      ext_trigger_n_i => adc0_ext_trigger_n_i,

@@ -1149,6 +1153,8 @@ begin
      acq_stop_p_o  => acq_stop_p(1),
      acq_end_p_o   => acq_end_p(1),

+      trigger_tag_i => fmc1_trigger_tag,
+
      ext_trigger_p_i => adc1_ext_trigger_p_i,
      ext_trigger_n_i => adc1_ext_trigger_n_i,

@@ -1292,19 +1298,18 @@ begin
  --  The counter is incremented on the falling edge of cyc. This is because the ddr controller
  --  samples the address on (cyc_re and stb)+1

-  -- cyc falling edge detection
-  p_ddr0_wb_cyc : process (sys_clk_125)
+  p_ddr0_dat_cyc: process (sys_clk_125)
  begin
    if rising_edge(sys_clk_125) then
-      if (fmc0_rst_n = '0') then
-        ddr0_wb_cyc_d <= '0';
+      if fmc0_rst_n = '0' then
+        ddr0_dat_cyc_d <= '0';
      else
-        ddr0_wb_cyc_d <= cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc;
+        ddr0_dat_cyc_d <= cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc;
      end if;
    end if;
-  end process p_ddr0_wb_cyc;
+  end process p_ddr0_dat_cyc;

-  ddr0_wb_cyc_fe <= not(cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc) and ddr0_wb_cyc_d;
+  ddr0_addr_cnt_en <= not(cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc) and ddr0_dat_cyc_d;

  -- address counter
  p_ddr0_addr_cnt : process (sys_clk_125)
@@ -1316,7 +1321,7 @@ begin
             cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).stb = '1' and
             cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).cyc = '1') then
        ddr0_addr_cnt <= unsigned(cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).dat);
-      elsif (ddr0_wb_cyc_fe = '1') then
+      elsif (ddr0_addr_cnt_en = '1') then
        ddr0_addr_cnt <= ddr0_addr_cnt + 1;
      end if;
    end if;
@@ -1445,19 +1450,18 @@ begin
  --  The counter is incremented on the falling edge of cyc. This is because the ddr controller
  --  samples the address on (cyc_re and stb)+1

-  -- cyc falling edge detection
-  p_ddr1_wb_cyc : process (sys_clk_125)
+  p_ddr1_dat_cyc: process (sys_clk_125)
  begin
    if rising_edge(sys_clk_125) then
-      if (fmc1_rst_n = '0') then
-        ddr1_wb_cyc_d <= '0';
+      if fmc1_rst_n = '0' then
+        ddr1_dat_cyc_d <= '0';
      else
-        ddr1_wb_cyc_d <= cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc;
+        ddr1_dat_cyc_d <= cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc;
      end if;
    end if;
-  end process p_ddr1_wb_cyc;
+  end process p_ddr1_dat_cyc;

-  ddr1_wb_cyc_fe <= not(cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc) and ddr1_wb_cyc_d;
+  ddr1_addr_cnt_en <= not(cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc) and ddr1_dat_cyc_d;

  -- address counter
  p_ddr1_addr_cnt : process (sys_clk_125)
@@ -1469,7 +1473,7 @@ begin
             cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).stb = '1' and
             cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).cyc = '1') then
        ddr1_addr_cnt <= unsigned(cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).dat);
-      elsif (ddr1_wb_cyc_fe = '1') then
+      elsif (ddr1_addr_cnt_en = '1') then
        ddr1_addr_cnt <= ddr1_addr_cnt + 1;
      end if;
    end if;
@@ -1512,6 +1516,8 @@ begin
      acq_stop_p_i  => acq_stop_p(0),
      acq_end_p_i   => acq_end_p(0),

+      trig_tag_o => fmc0_trigger_tag,
+
      wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).adr(6 downto 2),  -- cnx_master_out.adr is byte address
      wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).dat,
      wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).dat,
@@ -1541,6 +1547,8 @@ begin
      acq_stop_p_i  => acq_stop_p(1),
      acq_end_p_i   => acq_end_p(1),

+      trig_tag_o => fmc1_trigger_tag,
+
      wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).adr(6 downto 2),  -- cnx_master_out.adr is byte address
      wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).dat,
      wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).dat,

--- a/hdl/svec/sim/testbench/Makefile
+++ b/hdl/svec/sim/testbench/Makefile
@@ -22,9 +22,7 @@ VERILOG_SRC := main.sv \
 ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
 ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
 ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
-../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v \
 ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
-../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v \
 ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
 ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v \
 ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v \
@@ -40,9 +38,7 @@ work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v \
 work/jtag_cores/.jtag_cores_v \
 work/lm32_adder/.lm32_adder_v \
 work/lm32_addsub/.lm32_addsub_v \
-work/lm32_dp_ram/.lm32_dp_ram_v \
 work/lm32_logic_op/.lm32_logic_op_v \
-work/lm32_ram/.lm32_ram_v \
 work/lm32_shifter/.lm32_shifter_v \
 work/lm32_multiplier/.lm32_multiplier_v \
 work/jtag_tap/.jtag_tap_v \
@@ -56,15 +52,15 @@ VHDL_SRC := ../../../ip_cores/adc_sync_fifo.vhd \
 ../../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd \
 ../../rtl/bicolor_led_ctrl_pkg.vhd \
 ../../rtl/carrier_csr.vhd \
-../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
 ../../rtl/bicolor_led_ctrl.vhd \
 ../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
-../../../adc/rtl/fmc_adc_mezzanine_pkg.vhd \
-../../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd \
 ../../../ip_cores/timetag_core/rtl/timetag_core_pkg.vhd \
+../../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd \
+../../../adc/rtl/fmc_adc_mezzanine_pkg.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
 ../../rtl/sdb_meta_pkg.vhd \
 ../../../adc/rtl/fmc_adc_100Ms_csr.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
 ../../../adc/rtl/offset_gain_s.vhd \
 ../../../ip_cores/timetag_core/rtl/timetag_core_regs.vhd \
 ../../../ip_cores/timetag_core/rtl/timetag_core.vhd \
@@ -80,20 +76,26 @@ VHDL_SRC := ../../../ip_cores/adc_sync_fifo.vhd \
 ../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
 ../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
 ../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
+../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
 ../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
-../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd \
-../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd \
+../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
+../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
+../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
+../../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
 ../../../adc/rtl/fmc_adc_100Ms_core.vhd \
 ../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
 ../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
+../../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
+../../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
 ../../../adc/rtl/fmc_adc_mezzanine.vhd \
 ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
 ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
 ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
+../../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
 ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
-../../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd \
-../../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd \
-../../../ip_cores/general-cores/modules/genrams/xilinx/sim_stub/dummy.vhd \
+../../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
+../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
+../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
@@ -125,20 +127,34 @@ VHDL_SRC := ../../../ip_cores/adc_sync_fifo.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
-../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
-../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
-../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
-../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
+../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
 ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
-../../rtl/irq_controller.vhd \
+../../../adc/rtl/fmc_adc_eic.vhd \
+../../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
+../../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
+../../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
+../../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
 ../../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd \
 ../../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd \
 ../../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd \
@@ -187,15 +203,15 @@ work/utils_pkg/.utils_pkg_vhd \
 work/ext_pulse_sync_rtl/.ext_pulse_sync_rtl_vhd \
 work/bicolor_led_ctrl_pkg/.bicolor_led_ctrl_pkg_vhd \
 work/carrier_csr/.carrier_csr_vhd \
-work/wbgen2_pkg/.wbgen2_pkg_vhd \
 work/bicolor_led_ctrl/.bicolor_led_ctrl_vhd \
 work/genram_pkg/.genram_pkg_vhd \
-work/fmc_adc_mezzanine_pkg/.fmc_adc_mezzanine_pkg_vhd \
-work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg_vhd \
 work/timetag_core_pkg/.timetag_core_pkg_vhd \
+work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg_vhd \
+work/fmc_adc_mezzanine_pkg/.fmc_adc_mezzanine_pkg_vhd \
 work/wishbone_pkg/.wishbone_pkg_vhd \
 work/sdb_meta_pkg/.sdb_meta_pkg_vhd \
 work/fmc_adc_100Ms_csr/.fmc_adc_100Ms_csr_vhd \
+work/wbgen2_pkg/.wbgen2_pkg_vhd \
 work/offset_gain_s/.offset_gain_s_vhd \
 work/timetag_core_regs/.timetag_core_regs_vhd \
 work/timetag_core/.timetag_core_vhd \
@@ -211,20 +227,26 @@ work/gc_serial_dac/.gc_serial_dac_vhd \
 work/gc_sync_ffs/.gc_sync_ffs_vhd \
 work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd \
 work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd \
+work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2_vhd \
 work/gc_frequency_meter/.gc_frequency_meter_vhd \
-work/gc_dual_clock_ram/.gc_dual_clock_ram_vhd \
-work/gc_wfifo/.gc_wfifo_vhd \
+work/gc_rr_arbiter/.gc_rr_arbiter_vhd \
+work/gc_prio_encoder/.gc_prio_encoder_vhd \
+work/gc_word_packer/.gc_word_packer_vhd \
+work/gc_big_adder/.gc_big_adder_vhd \
 work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core_vhd \
 work/memory_loader_pkg/.memory_loader_pkg_vhd \
 work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd \
+work/inferred_sync_fifo/.inferred_sync_fifo_vhd \
+work/inferred_async_fifo/.inferred_async_fifo_vhd \
 work/fmc_adc_mezzanine/.fmc_adc_mezzanine_vhd \
 work/generic_dpram/.generic_dpram_vhd \
 work/generic_dpram_sameclock/.generic_dpram_sameclock_vhd \
 work/generic_dpram_dualclock/.generic_dpram_dualclock_vhd \
+work/generic_simple_dpram/.generic_simple_dpram_vhd \
 work/generic_spram/.generic_spram_vhd \
+work/gc_shiftreg/.gc_shiftreg_vhd \
 work/generic_async_fifo/.generic_async_fifo_vhd \
 work/generic_sync_fifo/.generic_sync_fifo_vhd \
-fifo_generator_v6_1/dummy/.dummy_vhd \
 work/wb_async_bridge/.wb_async_bridge_vhd \
 work/xwb_async_bridge/.xwb_async_bridge_vhd \
 work/wb_onewire_master/.wb_onewire_master_vhd \
@@ -256,20 +278,34 @@ work/xwb_spi/.xwb_spi_vhd \
 work/sdb_rom/.sdb_rom_vhd \
 work/xwb_crossbar/.xwb_crossbar_vhd \
 work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd \
+work/wb_irq_pkg/.wb_irq_pkg_vhd \
+work/irqm_core/.irqm_core_vhd \
+work/wb_irq_lm32/.wb_irq_lm32_vhd \
+work/wb_irq_slave/.wb_irq_slave_vhd \
+work/wb_irq_master/.wb_irq_master_vhd \
+work/wb_irq_timer/.wb_irq_timer_vhd \
 work/xwb_lm32/.xwb_lm32_vhd \
+work/lm32_dp_ram/.lm32_dp_ram_vhd \
+work/lm32_ram/.lm32_ram_vhd \
 work/wb_slave_adapter/.wb_slave_adapter_vhd \
-work/xloader_registers_pkg/.xloader_registers_pkg_vhd \
-work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd \
-work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd \
-work/xloader_wb/.xloader_wb_vhd \
 work/xwb_clock_crossing/.xwb_clock_crossing_vhd \
 work/xwb_dma/.xwb_dma_vhd \
+work/xwb_streamer/.xwb_streamer_vhd \
 work/wb_serial_lcd/.wb_serial_lcd_vhd \
+work/wb_spi_flash/.wb_spi_flash_vhd \
+work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg_vhd \
+work/simple_pwm_wb/.simple_pwm_wb_vhd \
+work/wb_simple_pwm/.wb_simple_pwm_vhd \
+work/xwb_simple_pwm/.xwb_simple_pwm_vhd \
 work/wbgen2_dpssram/.wbgen2_dpssram_vhd \
 work/wbgen2_eic/.wbgen2_eic_vhd \
 work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd \
 work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd \
-work/irq_controller/.irq_controller_vhd \
+work/fmc_adc_eic/.fmc_adc_eic_vhd \
+work/xloader_registers_pkg/.xloader_registers_pkg_vhd \
+work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd \
+work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd \
+work/xloader_wb/.xloader_wb_vhd \
 work/ddr3_ctrl/.ddr3_ctrl_vhd \
 work/ddr3_ctrl_wb/.ddr3_ctrl_wb_vhd \
 work/ddr3_ctrl_wrapper_pkg/.ddr3_ctrl_wrapper_pkg_vhd \
@@ -309,8 +345,8 @@ work/VME_SharedComps/.VME_SharedComps_vhd \
 work/VME_swapper/.VME_swapper_vhd \
 work/VME_Wb_master/.VME_Wb_master_vhd \

-LIBS := work fifo_generator_v6_1
-LIB_IND := work/.work fifo_generator_v6_1/.fifo_generator_v6_1
+LIBS := work
+LIB_IND := work/.work
 ## rules #################################
 sim: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
 $(VERILOG_OBJ): $(VHDL_OBJ) 
@@ -325,9 +361,6 @@ clean:
 work/.work:
 	(vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work 

-fifo_generator_v6_1/.fifo_generator_v6_1:
-	(vlib fifo_generator_v6_1 && vmap -modelsimini modelsim.ini fifo_generator_v6_1 && touch fifo_generator_v6_1/.fifo_generator_v6_1 )|| rm -rf fifo_generator_v6_1 
-
 work/main/.main_sv: main.sv 
 		vlog -work work $(VLOG_FLAGS)  -sv +incdir+. +incdir+../vme64x_bfm +incdir+../2048Mb_ddr3 $<
 		@mkdir -p $(dir $@) && touch $@ 
@@ -383,21 +416,11 @@ work/lm32_addsub/.lm32_addsub_v: ../../../ip_cores/general-cores/modules/wishbon
 		@mkdir -p $(dir $@) && touch $@ 


-work/lm32_dp_ram/.lm32_dp_ram_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v 
-		vlog -work work $(VLOG_FLAGS) +incdir+../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
-		@mkdir -p $(dir $@) && touch $@ 
-
-
 work/lm32_logic_op/.lm32_logic_op_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
 		vlog -work work $(VLOG_FLAGS) +incdir+../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
 		@mkdir -p $(dir $@) && touch $@ 


-work/lm32_ram/.lm32_ram_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
-		vlog -work work $(VLOG_FLAGS) +incdir+../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
-		@mkdir -p $(dir $@) && touch $@ 
-
-
 work/lm32_shifter/.lm32_shifter_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
 		vlog -work work $(VLOG_FLAGS) +incdir+../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src  $<
 		@mkdir -p $(dir $@) && touch $@ 
@@ -462,11 +485,6 @@ work/carrier_csr/.carrier_csr_vhd: ../../rtl/carrier_csr.vhd
 		@mkdir -p $(dir $@) && touch $@


-work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
-		vcom $(VCOM_FLAGS)  -work work $< 
-		@mkdir -p $(dir $@) && touch $@
-
-
 work/bicolor_led_ctrl/.bicolor_led_ctrl_vhd: ../../rtl/bicolor_led_ctrl.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@
@@ -480,7 +498,7 @@ work/genram_pkg/.genram_pkg_vhd: ../../../ip_cores/general-cores/modules/genrams
 		@mkdir -p $(dir $@) && touch $@


-work/fmc_adc_mezzanine_pkg/.fmc_adc_mezzanine_pkg_vhd: ../../../adc/rtl/fmc_adc_mezzanine_pkg.vhd
+work/timetag_core_pkg/.timetag_core_pkg_vhd: ../../../ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

@@ -490,11 +508,17 @@ work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg_vhd: ../../../adc/rtl/fmc_ad
 		@mkdir -p $(dir $@) && touch $@


-work/timetag_core_pkg/.timetag_core_pkg_vhd: ../../../ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
+work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg: \
+work/timetag_core_pkg/.timetag_core_pkg
+
+work/fmc_adc_mezzanine_pkg/.fmc_adc_mezzanine_pkg_vhd: ../../../adc/rtl/fmc_adc_mezzanine_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


+work/fmc_adc_mezzanine_pkg/.fmc_adc_mezzanine_pkg: \
+work/timetag_core_pkg/.timetag_core_pkg
+
 work/wishbone_pkg/.wishbone_pkg_vhd: ../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@
@@ -516,6 +540,11 @@ work/fmc_adc_100Ms_csr/.fmc_adc_100Ms_csr_vhd: ../../../adc/rtl/fmc_adc_100Ms_cs
 		@mkdir -p $(dir $@) && touch $@


+work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
 work/offset_gain_s/.offset_gain_s_vhd: ../../../adc/rtl/offset_gain_s.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@
@@ -531,6 +560,9 @@ work/timetag_core/.timetag_core_vhd: ../../../ip_cores/timetag_core/rtl/timetag_
 		@mkdir -p $(dir $@) && touch $@


+work/timetag_core/.timetag_core: \
+work/timetag_core_pkg/.timetag_core_pkg
+
 work/gencores_pkg/.gencores_pkg_vhd: ../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@
@@ -566,6 +598,7 @@ work/gc_extend_pulse/.gc_extend_pulse_vhd: ../../../ip_cores/general-cores/modul


 work/gc_extend_pulse/.gc_extend_pulse: \
+work/genram_pkg/.genram_pkg \
 work/gencores_pkg/.gencores_pkg

 work/gc_delay_gen/.gc_delay_gen_vhd: ../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
@@ -616,6 +649,14 @@ work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd: ../../../ip_cores/general
 work/gc_pulse_synchronizer/.gc_pulse_synchronizer: \
 work/gencores_pkg/.gencores_pkg

+work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2_vhd: ../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2: \
+work/gencores_pkg/.gencores_pkg
+
 work/gc_frequency_meter/.gc_frequency_meter_vhd: ../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@
@@ -624,17 +665,31 @@ work/gc_frequency_meter/.gc_frequency_meter_vhd: ../../../ip_cores/general-cores
 work/gc_frequency_meter/.gc_frequency_meter: \
 work/gencores_pkg/.gencores_pkg

-work/gc_dual_clock_ram/.gc_dual_clock_ram_vhd: ../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd
+work/gc_rr_arbiter/.gc_rr_arbiter_vhd: ../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/gc_wfifo/.gc_wfifo_vhd: ../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd
+work/gc_prio_encoder/.gc_prio_encoder_vhd: ../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/gc_wfifo/.gc_wfifo: \
+work/gc_word_packer/.gc_word_packer_vhd: ../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/gc_word_packer/.gc_word_packer: \
+work/genram_pkg/.genram_pkg
+
+work/gc_big_adder/.gc_big_adder_vhd: ../../../ip_cores/general-cores/modules/common/gc_big_adder.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/gc_big_adder/.gc_big_adder: \
+work/wishbone_pkg/.wishbone_pkg \
 work/gencores_pkg/.gencores_pkg

 work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core_vhd: ../../../adc/rtl/fmc_adc_100Ms_core.vhd
@@ -643,7 +698,8 @@ work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core_vhd: ../../../adc/rtl/fmc_adc_100Ms_


 work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core: \
-work/genram_pkg/.genram_pkg
+work/genram_pkg/.genram_pkg \
+work/timetag_core_pkg/.timetag_core_pkg

 work/memory_loader_pkg/.memory_loader_pkg_vhd: ../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
@@ -661,6 +717,22 @@ work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd: ../../../ip_cores/general
 work/generic_shiftreg_fifo/.generic_shiftreg_fifo: \
 work/genram_pkg/.genram_pkg

+work/inferred_sync_fifo/.inferred_sync_fifo_vhd: ../../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/inferred_sync_fifo/.inferred_sync_fifo: \
+work/genram_pkg/.genram_pkg
+
+work/inferred_async_fifo/.inferred_async_fifo_vhd: ../../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/inferred_async_fifo/.inferred_async_fifo: \
+work/genram_pkg/.genram_pkg
+
 work/fmc_adc_mezzanine/.fmc_adc_mezzanine_vhd: ../../../adc/rtl/fmc_adc_mezzanine.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@
@@ -668,6 +740,7 @@ work/fmc_adc_mezzanine/.fmc_adc_mezzanine_vhd: ../../../adc/rtl/fmc_adc_mezzanin

 work/fmc_adc_mezzanine/.fmc_adc_mezzanine: \
 work/wishbone_pkg/.wishbone_pkg \
+work/timetag_core_pkg/.timetag_core_pkg \
 work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg

 work/generic_dpram/.generic_dpram_vhd: ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
@@ -697,6 +770,15 @@ work/generic_dpram_dualclock/.generic_dpram_dualclock: \
 work/genram_pkg/.genram_pkg \
 work/memory_loader_pkg/.memory_loader_pkg

+work/generic_simple_dpram/.generic_simple_dpram_vhd: ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/generic_simple_dpram/.generic_simple_dpram: \
+work/genram_pkg/.genram_pkg \
+work/memory_loader_pkg/.memory_loader_pkg
+
 work/generic_spram/.generic_spram_vhd: ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@
@@ -705,27 +787,30 @@ work/generic_spram/.generic_spram_vhd: ../../../ip_cores/general-cores/modules/g
 work/generic_spram/.generic_spram: \
 work/genram_pkg/.genram_pkg

-work/generic_async_fifo/.generic_async_fifo_vhd: ../../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd
+work/gc_shiftreg/.gc_shiftreg_vhd: ../../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/generic_async_fifo/.generic_async_fifo: \
+work/gc_shiftreg/.gc_shiftreg: \
 work/genram_pkg/.genram_pkg

-work/generic_sync_fifo/.generic_sync_fifo_vhd: ../../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd
+work/generic_async_fifo/.generic_async_fifo_vhd: ../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/generic_sync_fifo/.generic_sync_fifo: \
+work/generic_async_fifo/.generic_async_fifo: \
 work/genram_pkg/.genram_pkg

-fifo_generator_v6_1/dummy/.dummy_vhd: ../../../ip_cores/general-cores/modules/genrams/xilinx/sim_stub/dummy.vhd
-		vcom $(VCOM_FLAGS)  -work fifo_generator_v6_1 $< 
+work/generic_sync_fifo/.generic_sync_fifo_vhd: ../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


+work/generic_sync_fifo/.generic_sync_fifo: \
+work/genram_pkg/.genram_pkg
+
 work/wb_async_bridge/.wb_async_bridge_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@
@@ -906,6 +991,7 @@ work/wb_vic/.wb_vic_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_vic


 work/wb_vic/.wb_vic: \
+work/genram_pkg/.genram_pkg \
 work/wishbone_pkg/.wishbone_pkg

 work/xwb_vic/.xwb_vic_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
@@ -956,56 +1042,95 @@ work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd: ../../../ip_cores/general-cores/mod
 work/xwb_sdb_crossbar/.xwb_sdb_crossbar: \
 work/wishbone_pkg/.wishbone_pkg

-work/xwb_lm32/.xwb_lm32_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
+work/wb_irq_pkg/.wb_irq_pkg_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/xwb_lm32/.xwb_lm32: \
+work/wb_irq_pkg/.wb_irq_pkg: \
 work/wishbone_pkg/.wishbone_pkg

-work/wb_slave_adapter/.wb_slave_adapter_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
+work/irqm_core/.irqm_core_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/wb_slave_adapter/.wb_slave_adapter: \
+work/irqm_core/.irqm_core: \
+work/wb_irq_pkg/.wb_irq_pkg \
+work/genram_pkg/.genram_pkg \
 work/wishbone_pkg/.wishbone_pkg

-work/xloader_registers_pkg/.xloader_registers_pkg_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
+work/wb_irq_lm32/.wb_irq_lm32_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/xloader_registers_pkg/.xloader_registers_pkg: \
-work/wbgen2_pkg/.wbgen2_pkg
+work/wb_irq_lm32/.wb_irq_lm32: \
+work/wb_irq_pkg/.wb_irq_pkg \
+work/wishbone_pkg/.wishbone_pkg

-work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
+work/wb_irq_slave/.wb_irq_slave_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader: \
+work/wb_irq_slave/.wb_irq_slave: \
+work/wb_irq_pkg/.wb_irq_pkg \
+work/genram_pkg/.genram_pkg \
 work/wishbone_pkg/.wishbone_pkg

-work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
+work/wb_irq_master/.wb_irq_master_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader: \
+work/wb_irq_master/.wb_irq_master: \
+work/wb_irq_pkg/.wb_irq_pkg \
+work/genram_pkg/.genram_pkg \
+work/wishbone_pkg/.wishbone_pkg
+
+work/wb_irq_timer/.wb_irq_timer_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/wb_irq_timer/.wb_irq_timer: \
+work/wb_irq_pkg/.wb_irq_pkg \
+work/genram_pkg/.genram_pkg \
 work/wishbone_pkg/.wishbone_pkg \
-work/gencores_pkg/.gencores_pkg \
-work/xloader_registers_pkg/.xloader_registers_pkg
+work/gencores_pkg/.gencores_pkg

-work/xloader_wb/.xloader_wb_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd
+work/xwb_lm32/.xwb_lm32_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/xloader_wb/.xloader_wb: \
-work/wbgen2_pkg/.wbgen2_pkg \
-work/xloader_registers_pkg/.xloader_registers_pkg
+work/xwb_lm32/.xwb_lm32: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/lm32_dp_ram/.lm32_dp_ram_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/lm32_dp_ram/.lm32_dp_ram: \
+work/genram_pkg/.genram_pkg
+
+work/lm32_ram/.lm32_ram_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/lm32_ram/.lm32_ram: \
+work/genram_pkg/.genram_pkg
+
+work/wb_slave_adapter/.wb_slave_adapter_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/wb_slave_adapter/.wb_slave_adapter: \
+work/wishbone_pkg/.wishbone_pkg

 work/xwb_clock_crossing/.xwb_clock_crossing_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
@@ -1013,8 +1138,8 @@ work/xwb_clock_crossing/.xwb_clock_crossing_vhd: ../../../ip_cores/general-cores


 work/xwb_clock_crossing/.xwb_clock_crossing: \
-work/wishbone_pkg/.wishbone_pkg \
-work/gencores_pkg/.gencores_pkg
+work/genram_pkg/.genram_pkg \
+work/wishbone_pkg/.wishbone_pkg

 work/xwb_dma/.xwb_dma_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
@@ -1022,6 +1147,15 @@ work/xwb_dma/.xwb_dma_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_d


 work/xwb_dma/.xwb_dma: \
+work/genram_pkg/.genram_pkg \
+work/wishbone_pkg/.wishbone_pkg
+
+work/xwb_streamer/.xwb_streamer_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_streamer/.xwb_streamer: \
 work/wishbone_pkg/.wishbone_pkg

 work/wb_serial_lcd/.wb_serial_lcd_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
@@ -1033,6 +1167,46 @@ work/wb_serial_lcd/.wb_serial_lcd: \
 work/genram_pkg/.genram_pkg \
 work/wishbone_pkg/.wishbone_pkg

+work/wb_spi_flash/.wb_spi_flash_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/wb_spi_flash/.wb_spi_flash: \
+work/genram_pkg/.genram_pkg \
+work/wishbone_pkg/.wishbone_pkg \
+work/gencores_pkg/.gencores_pkg
+
+work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/simple_pwm_wb/.simple_pwm_wb_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/simple_pwm_wb/.simple_pwm_wb: \
+work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg
+
+work/wb_simple_pwm/.wb_simple_pwm_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/wb_simple_pwm/.wb_simple_pwm: \
+work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg \
+work/wishbone_pkg/.wishbone_pkg
+
+work/xwb_simple_pwm/.xwb_simple_pwm_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_simple_pwm/.xwb_simple_pwm: \
+work/wishbone_pkg/.wishbone_pkg
+
 work/wbgen2_dpssram/.wbgen2_dpssram_vhd: ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@
@@ -1066,14 +1240,49 @@ work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd: ../../../ip_cores/general-cores/mod
 work/wbgen2_fifo_sync/.wbgen2_fifo_sync: \
 work/wbgen2_pkg/.wbgen2_pkg

-work/irq_controller/.irq_controller_vhd: ../../rtl/irq_controller.vhd
+work/fmc_adc_eic/.fmc_adc_eic_vhd: ../../../adc/rtl/fmc_adc_eic.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@


-work/irq_controller/.irq_controller: \
+work/fmc_adc_eic/.fmc_adc_eic: \
 work/wbgen2_pkg/.wbgen2_pkg

+work/xloader_registers_pkg/.xloader_registers_pkg_vhd: ../../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/xloader_registers_pkg/.xloader_registers_pkg: \
+work/wbgen2_pkg/.wbgen2_pkg
+
+work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd: ../../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd: ../../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader: \
+work/wishbone_pkg/.wishbone_pkg \
+work/gencores_pkg/.gencores_pkg \
+work/xloader_registers_pkg/.xloader_registers_pkg
+
+work/xloader_wb/.xloader_wb_vhd: ../../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
+		vcom $(VCOM_FLAGS)  -work work $< 
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/xloader_wb/.xloader_wb: \
+work/wbgen2_pkg/.wbgen2_pkg \
+work/xloader_registers_pkg/.xloader_registers_pkg
+
 work/ddr3_ctrl/.ddr3_ctrl_vhd: ../../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd
 		vcom $(VCOM_FLAGS)  -work work $< 
 		@mkdir -p $(dir $@) && touch $@

--- a/hdl/svec/sim/testbench/main.sv
+++ b/hdl/svec/sim/testbench/main.sv
@@ -112,6 +112,8 @@ module main;
   initial begin
      uint64_t d;
      uint32_t wr_data;
+      uint64_t blt_addr[];
+      uint64_t blt_data[];

      int i, result;

@@ -121,12 +123,20 @@ module main;
      #20us;
      init_vme64x_core(acc);

+      $display("Release FMC0/1 reset\n");
+      acc.write('h120C, 'h3, A32|SINGLE|D32);
+

      // Enable all interrupts
-      $display("Enable all interrupts\n");
-      acc.write('h1304, 'hF, A32|SINGLE|D32);
-      acc.read('h1308, d, A32|SINGLE|D32);
-      $display("Interrupt mask = 0x%x\n",d);
+      $display("Enable FMC0 and FMC1 interrupt vectors\n");
+      acc.write('h1308, 'h3, A32|SINGLE|D32);
+      acc.read('h1310, d, A32|SINGLE|D32);
+      $display("VIC interrupt mask = 0x%x\n",d);
+      acc.write('h1300, 'h3, A32|SINGLE|D32);
+
+      $display("Enable TRIGGER and END_ACQ in FMC0/1 EIC\n");
+      acc.write('h2000, 'h3, A32|SINGLE|D32);
+      acc.write('h6000, 'h3, A32|SINGLE|D32);

      // Trigger setup (sw trigger)
      $display("Trigger setup\n");
@@ -150,12 +160,35 @@ module main;
      $display("Software trigger\n");
      acc.write('h5310, 'hFF, A32|SINGLE|D32);

-
      /*
+      // Data "FIFO" test
+      acc.write('h2200, 'h0, A32|SINGLE|D32);
+      acc.read('h2200, d, A32|SINGLE|D32);
+      $display("Read DDR_ADR: 0x%x\n", d);
+
+      $display("Write data to DDR in BLT\n");
+      blt_addr = {'h3000};
+      blt_data = {'h1, 'h2, 'h3, 'h4, 'h5, 'h6, 'h7, 'h8 ,'h9, 'hA};
+      acc.writem(blt_addr, blt_data, A32|BLT|D32, result);
+
+      acc.write('h2200, 'h0, A32|SINGLE|D32);
+      acc.read('h2200, d, A32|SINGLE|D32);
+      $display("Read DDR_ADR: 0x%x\n", d);
+
+      $display("Read data from DDR in BLT");
+      blt_data = {};
+      acc.readm(blt_addr, blt_data, A32|BLT|D32, result);
+
+      for(i=0; i<10; i++)
+        begin
+           $display("Data %d: 0x%x\n", i, blt_data[i]);
+        end
+      */
+
      acc.write('h2200, 'h0, A32|SINGLE|D32);
      for(i=0; i<5; i++)
        begin
-           acc.read('h2100, d, A32|SINGLE|D32);
+           acc.read('h3000, d, A32|SINGLE|D32);
           $display("Read %d: 0x%x\n", i, d);
        end

@@ -163,17 +196,17 @@ module main;
      for(i=0; i<2; i++)
        begin
           wr_data = i;
-           acc.write('h2100, wr_data, A32|SINGLE|D32);
+           acc.write('h3000, wr_data, A32|SINGLE|D32);
           $display("Write %d: 0x%x\n", i, wr_data);
        end

      acc.write('h2200, 'h0, A32|SINGLE|D32);
      for(i=0; i<5; i++)
        begin
-           acc.read('h2100, d, A32|SINGLE|D32);
+           acc.read('h3000, d, A32|SINGLE|D32);
           $display("Read %d: 0x%x\n", i, d);
        end
-       */
+

   end


--- a/hdl/svec/sim/testbench/svec.do
+++ b/hdl/svec/sim/testbench/svec.do
@@ -5,7 +5,8 @@ set NumericStdNoWarnings 1

 #view wave
 #view transcript
-do wave_interrupt.do
+#do wave_interrupt.do
+do wave_ddr.do
 radix -hexadecimal

 run 50 us