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Commit 14262933 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: adjusted timetag core to WR time interface format (40bit TAI + 28bit clock ticks)

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doc/manual/timetag_core_regs.tex
View file @ 14262933
......@@ -3,134 +3,125 @@
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{seconds} @tab
Timetag seconds register
@code{seconds_upper} @tab
Timetag seconds register (upper)
@item @code{0x4} @tab
REG @tab
@code{coarse} @tab
Timetag coarse time register, system clock ticks (125MHz)
@code{seconds_lower} @tab
Timetag seconds register (lower)
@item @code{0x8} @tab
REG @tab
@code{trig_tag_meta} @tab
Trigger time-tag metadata register
@code{coarse} @tab
Timetag coarse time register, system clock ticks (125MHz)
@item @code{0xc} @tab
REG @tab
@code{trig_tag_seconds} @tab
Trigger time-tag seconds register
@code{trig_tag_seconds_upper} @tab
Trigger time-tag seconds register (upper)
@item @code{0x10} @tab
REG @tab
@code{trig_tag_coarse} @tab
Trigger time-tag coarse time (system clock ticks 125MHz) register
@code{trig_tag_seconds_lower} @tab
Trigger time-tag seconds register (lower)
@item @code{0x14} @tab
REG @tab
@code{trig_tag_fine} @tab
Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)
@code{trig_tag_coarse} @tab
Trigger time-tag coarse time (system clock ticks 125MHz) register
@item @code{0x18} @tab
REG @tab
@code{acq_start_tag_meta} @tab
Acquisition start time-tag metadata register
@code{acq_start_tag_seconds_upper} @tab
Acquisition start time-tag seconds register (upper)
@item @code{0x1c} @tab
REG @tab
@code{acq_start_tag_seconds} @tab
Acquisition start time-tag seconds register
@code{acq_start_tag_seconds_lower} @tab
Acquisition start time-tag seconds register (lower)
@item @code{0x20} @tab
REG @tab
@code{acq_start_tag_coarse} @tab
Acquisition start time-tag coarse time (system clock ticks 125MHz) register
@item @code{0x24} @tab
REG @tab
@code{acq_start_tag_fine} @tab
Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)
@code{acq_stop_tag_seconds_upper} @tab
Acquisition stop time-tag seconds register (upper)
@item @code{0x28} @tab
REG @tab
@code{acq_stop_tag_meta} @tab
Acquisition stop time-tag metadata register
@code{acq_stop_tag_seconds_lower} @tab
Acquisition stop time-tag seconds register (lower)
@item @code{0x2c} @tab
REG @tab
@code{acq_stop_tag_seconds} @tab
Acquisition stop time-tag seconds register
@item @code{0x30} @tab
REG @tab
@code{acq_stop_tag_coarse} @tab
Acquisition stop time-tag coarse time (system clock ticks 125MHz) register
@item @code{0x30} @tab
REG @tab
@code{acq_end_tag_seconds_upper} @tab
Acquisition end time-tag seconds register (upper)
@item @code{0x34} @tab
REG @tab
@code{acq_stop_tag_fine} @tab
Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)
@code{acq_end_tag_seconds_lower} @tab
Acquisition end time-tag seconds register (lower)
@item @code{0x38} @tab
REG @tab
@code{acq_end_tag_meta} @tab
Acquisition end time-tag metadata register
@item @code{0x3c} @tab
REG @tab
@code{acq_end_tag_seconds} @tab
Acquisition end time-tag seconds register
@item @code{0x40} @tab
REG @tab
@code{acq_end_tag_coarse} @tab
Acquisition end time-tag coarse time (system clock ticks 125MHz) register
@item @code{0x44} @tab
REG @tab
@code{acq_end_tag_fine} @tab
Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility)
@end multitable
@regsection @code{seconds} - Timetag seconds register
Seconds counter. Incremented everytime the coarse counter overflows.
@regsection @code{seconds_upper} - Timetag seconds register (upper)
8 upper bits of seconds counter. Incremented everytime the coarse counter overflows.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@item @code{7...0}
@tab R/W @tab
@code{SECONDS}
@code{SECONDS_UPPER}
@tab @code{X} @tab
Timetag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@regsection @code{seconds_lower} - Timetag seconds register (lower)
32 lower bits of seconds counter. Incremented everytime the coarse counter overflows.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{SECONDS_LOWER}
@tab @code{X} @tab
Timetag seconds
@end multitable
@regsection @code{coarse} - Timetag coarse time register, system clock ticks (125MHz)
Coarse time counter clocked by 125MHz system clock.
Counts from 0 to 125000000.
Coarse time counter clocked by 125MHz system clock.@*Counts from 0 to 125000000.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@item @code{27...0}
@tab R/W @tab
@code{COARSE}
@tab @code{X} @tab
Timetag coarse time
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{trig_tag_meta} - Trigger time-tag metadata register
@regsection @code{trig_tag_seconds_upper} - Trigger time-tag seconds register (upper)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@item @code{7...0}
@tab R/O @tab
@code{TRIG_TAG_META}
@code{TRIG_TAG_SECONDS_UPPER}
@tab @code{X} @tab
Trigger time-tag metadata
Trigger time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_tag_meta} @tab Holds time-tag metadata of the last trigger event
@item @code{trig_tag_seconds_upper} @tab Holds time-tag seconds of the last trigger event
@end multitable
@regsection @code{trig_tag_seconds} - Trigger time-tag seconds register
@regsection @code{trig_tag_seconds_lower} - Trigger time-tag seconds register (lower)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{TRIG_TAG_SECONDS}
@code{TRIG_TAG_SECONDS_LOWER}
@tab @code{X} @tab
Trigger time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_tag_seconds} @tab Holds time-tag seconds of the last trigger event
@item @code{trig_tag_seconds_lower} @tab Holds time-tag seconds of the last trigger event
@end multitable
@regsection @code{trig_tag_coarse} - Trigger time-tag coarse time (system clock ticks 125MHz) register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@item @code{27...0}
@tab R/O @tab
@code{TRIG_TAG_COARSE}
@tab @code{X} @tab
......@@ -140,49 +131,36 @@ Trigger time-tag coarse time
@headitem Field @tab Description
@item @code{trig_tag_coarse} @tab Holds time-tag coarse time of the last trigger event
@end multitable
@regsection @code{trig_tag_fine} - Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{TRIG_TAG_FINE}
@tab @code{X} @tab
Trigger time-tag fine time
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_tag_fine} @tab Holds time-tag fine time of the last trigger event
@end multitable
@regsection @code{acq_start_tag_meta} - Acquisition start time-tag metadata register
@regsection @code{acq_start_tag_seconds_upper} - Acquisition start time-tag seconds register (upper)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@item @code{7...0}
@tab R/O @tab
@code{ACQ_START_TAG_META}
@code{ACQ_START_TAG_SECONDS_UPPER}
@tab @code{X} @tab
Acquisition start time-tag metadata
Acquisition start time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_start_tag_meta} @tab Holds time-tag metadata of the last acquisition start event
@item @code{acq_start_tag_seconds_upper} @tab Holds time-tag seconds of the last acquisition start event
@end multitable
@regsection @code{acq_start_tag_seconds} - Acquisition start time-tag seconds register
@regsection @code{acq_start_tag_seconds_lower} - Acquisition start time-tag seconds register (lower)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{ACQ_START_TAG_SECONDS}
@code{ACQ_START_TAG_SECONDS_LOWER}
@tab @code{X} @tab
Acquisition start time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_start_tag_seconds} @tab Holds time-tag seconds of the last acquisition start event
@item @code{acq_start_tag_seconds_lower} @tab Holds time-tag seconds of the last acquisition start event
@end multitable
@regsection @code{acq_start_tag_coarse} - Acquisition start time-tag coarse time (system clock ticks 125MHz) register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@item @code{27...0}
@tab R/O @tab
@code{ACQ_START_TAG_COARSE}
@tab @code{X} @tab
......@@ -192,49 +170,36 @@ Acquisition start time-tag coarse time
@headitem Field @tab Description
@item @code{acq_start_tag_coarse} @tab Holds time-tag coarse time of the last acquisition start event
@end multitable
@regsection @code{acq_start_tag_fine} - Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)
@regsection @code{acq_stop_tag_seconds_upper} - Acquisition stop time-tag seconds register (upper)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@item @code{7...0}
@tab R/O @tab
@code{ACQ_START_TAG_FINE}
@code{ACQ_STOP_TAG_SECONDS_UPPER}
@tab @code{X} @tab
Acquisition start time-tag fine time
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_start_tag_fine} @tab Holds time-tag fine time of the last acquisition start event
@end multitable
@regsection @code{acq_stop_tag_meta} - Acquisition stop time-tag metadata register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{ACQ_STOP_TAG_META}
@tab @code{X} @tab
Acquisition stop time-tag metadata
Acquisition stop time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_stop_tag_meta} @tab Holds time-tag metadata of the last acquisition stop event
@item @code{acq_stop_tag_seconds_upper} @tab Holds time-tag seconds of the last acquisition stop event
@end multitable
@regsection @code{acq_stop_tag_seconds} - Acquisition stop time-tag seconds register
@regsection @code{acq_stop_tag_seconds_lower} - Acquisition stop time-tag seconds register (lower)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{ACQ_STOP_TAG_SECONDS}
@code{ACQ_STOP_TAG_SECONDS_LOWER}
@tab @code{X} @tab
Acquisition stop time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_stop_tag_seconds} @tab Holds time-tag seconds of the last acquisition stop event
@item @code{acq_stop_tag_seconds_lower} @tab Holds time-tag seconds of the last acquisition stop event
@end multitable
@regsection @code{acq_stop_tag_coarse} - Acquisition stop time-tag coarse time (system clock ticks 125MHz) register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@item @code{27...0}
@tab R/O @tab
@code{ACQ_STOP_TAG_COARSE}
@tab @code{X} @tab
......@@ -244,49 +209,36 @@ Acquisition stop time-tag coarse time
@headitem Field @tab Description
@item @code{acq_stop_tag_coarse} @tab Holds time-tag coarse time of the last acquisition stop event
@end multitable
@regsection @code{acq_stop_tag_fine} - Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{ACQ_STOP_TAG_FINE}
@tab @code{X} @tab
Acquisition stop time-tag fine time
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_stop_tag_fine} @tab Holds time-tag fine time of the last acquisition stop event
@end multitable
@regsection @code{acq_end_tag_meta} - Acquisition end time-tag metadata register
@regsection @code{acq_end_tag_seconds_upper} - Acquisition end time-tag seconds register (upper)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@item @code{7...0}
@tab R/O @tab
@code{ACQ_END_TAG_META}
@code{ACQ_END_TAG_SECONDS_UPPER}
@tab @code{X} @tab
Acquisition end time-tag metadata
Acquisition end time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_end_tag_meta} @tab Holds time-tag metadata of the last acquisition end event
@item @code{acq_end_tag_seconds_upper} @tab Holds time-tag seconds of the last acquisition end event
@end multitable
@regsection @code{acq_end_tag_seconds} - Acquisition end time-tag seconds register
@regsection @code{acq_end_tag_seconds_lower} - Acquisition end time-tag seconds register (lower)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{ACQ_END_TAG_SECONDS}
@code{ACQ_END_TAG_SECONDS_LOWER}
@tab @code{X} @tab
Acquisition end time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_end_tag_seconds} @tab Holds time-tag seconds of the last acquisition end event
@item @code{acq_end_tag_seconds_lower} @tab Holds time-tag seconds of the last acquisition end event
@end multitable
@regsection @code{acq_end_tag_coarse} - Acquisition end time-tag coarse time (system clock ticks 125MHz) register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@item @code{27...0}
@tab R/O @tab
@code{ACQ_END_TAG_COARSE}
@tab @code{X} @tab
......@@ -296,16 +248,3 @@ Acquisition end time-tag coarse time
@headitem Field @tab Description
@item @code{acq_end_tag_coarse} @tab Holds time-tag coarse time of the last acquisition end event
@end multitable
@regsection @code{acq_end_tag_fine} - Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{ACQ_END_TAG_FINE}
@tab @code{X} @tab
Acquisition end time-tag fine time
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_end_tag_fine} @tab Holds time-tag fine time of the last acquisition end event
@end multitable
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ 14262933
......@@ -9,7 +9,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-24
-- Last update: 2016-04-19
-- Last update: 2016-06-08
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: FMC ADC 100Ms/s core.
......@@ -1357,8 +1357,9 @@ begin
trig_tag_done <= acq_in_trig_tag and acq_in_trig_tag_d;
trig_tag_data <= trigger_tag_i.fine & trigger_tag_i.coarse when trig_tag_done = '1' else
trigger_tag_i.seconds & trigger_tag_i.meta;
-- keep compatibility with trig_tag_data order prior to 5.0 release
trig_tag_data <= X"000000000" & trigger_tag_i.coarse when trig_tag_done = '1' else
trigger_tag_i.seconds(31 downto 0) & X"000000" & trigger_tag_i.seconds(39 downto 32);
------------------------------------------------------------------------------
-- Dual DPRAM buffers for multi-shots acquisition
......
hdl/adc/rtl/fmc_adc_mezzanine.vhd
View file @ 14262933
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- FMC ADC mezzanine
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: fmc_adc_mezzanine (fmc_adc_mezzanine.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 07-05-2013
--
-- description: The FMC ADC mezzanine is wrapper around the fmc-adc-100ms core and
-- the other wishbone slaves connected to a FMC ADC mezzanine.
--
-- dependencies:
--
-- references:
--
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title : FMC ADC mezzanine
-- Project : FMC ADC 100M 14B 4CHA gateware
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : fmc_adc_mezzanine.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-05-07
-- Last update: 2016-06-08
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: The FMC ADC mezzanine is wrapper around the fmc-adc-100ms core
-- and the other wishbone slaves connected to a FMC ADC mezzanine.
-------------------------------------------------------------------------------
-- Copyright (c) 2013-2016 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
......@@ -29,11 +27,11 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see git log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2013-05-07 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......@@ -612,9 +610,11 @@ begin
acq_stop_p_i => acq_stop_p,
acq_end_p_i => acq_end_p,
wr_enabled_i => '0',
trig_tag_o => trigger_tag,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_adr_i => cnx_master_out(c_WB_SLAVE_TIMETAG).adr(5 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_TIMETAG).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TIMETAG).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_TIMETAG).cyc,
......
hdl/ip_cores/timetag_core/rtl/timetag_core.vhd
View file @ 14262933
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Time-tagging core
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: timetag_core (timetag_core.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 18-11-2011
--
-- version: 1.0
--
-- description: Implements a UTC seconds counter and a 125MHz system clock ticks
-- counter to time-tag trigger, acquisition start and stop events.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title : Time-tagging core
-- Project : FMC ADC 100M 14B 4CHA gateware
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : timetag_core.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-11-18
-- Last update: 2016-06-08
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Implements a UTC seconds counter and a 125MHz system clock
-- ticks counter to time-tag trigger, acquisition start and stop events.
-------------------------------------------------------------------------------
-- Copyright (c) 2011-2016 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
......@@ -29,25 +27,21 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2011-11-18 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity timetag_core is
port (
-- Clock, reset
clk_i : in std_logic; -- Must be 125MHz
clk_i : in std_logic; -- Must be 125MHz
rst_n_i : in std_logic;
-- Input pulses to time-tag
......@@ -56,11 +50,14 @@ entity timetag_core is
acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic;
-- White Rabbit enabled flag
wr_enabled_i : in std_logic;
-- Trigger time-tag output
trig_tag_o : out t_timetag;
-- Wishbone interface
wb_adr_i : in std_logic_vector(4 downto 0);
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -78,62 +75,52 @@ architecture rtl of timetag_core is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component timetag_core_regs
component timetag_core_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
timetag_core_seconds_o : out std_logic_vector(31 downto 0);
timetag_core_seconds_i : in std_logic_vector(31 downto 0);
timetag_core_seconds_load_o : out std_logic;
timetag_core_coarse_o : out std_logic_vector(31 downto 0);
timetag_core_coarse_i : in std_logic_vector(31 downto 0);
timetag_core_coarse_load_o : out std_logic;
timetag_core_trig_tag_meta_i : in std_logic_vector(31 downto 0);
timetag_core_trig_tag_seconds_i : in std_logic_vector(31 downto 0);
timetag_core_trig_tag_coarse_i : in std_logic_vector(31 downto 0);
timetag_core_trig_tag_fine_i : in std_logic_vector(31 downto 0);
timetag_core_acq_start_tag_meta_i : in std_logic_vector(31 downto 0);
timetag_core_acq_start_tag_seconds_i : in std_logic_vector(31 downto 0);
timetag_core_acq_start_tag_coarse_i : in std_logic_vector(31 downto 0);
timetag_core_acq_start_tag_fine_i : in std_logic_vector(31 downto 0);
timetag_core_acq_stop_tag_meta_i : in std_logic_vector(31 downto 0);
timetag_core_acq_stop_tag_seconds_i : in std_logic_vector(31 downto 0);
timetag_core_acq_stop_tag_coarse_i : in std_logic_vector(31 downto 0);
timetag_core_acq_stop_tag_fine_i : in std_logic_vector(31 downto 0);
timetag_core_acq_end_tag_meta_i : in std_logic_vector(31 downto 0);
timetag_core_acq_end_tag_seconds_i : in std_logic_vector(31 downto 0);
timetag_core_acq_end_tag_coarse_i : in std_logic_vector(31 downto 0);
timetag_core_acq_end_tag_fine_i : in std_logic_vector(31 downto 0)
);
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
timetag_core_seconds_upper_o : out std_logic_vector(7 downto 0);
timetag_core_seconds_upper_i : in std_logic_vector(7 downto 0);
timetag_core_seconds_upper_load_o : out std_logic;
timetag_core_seconds_lower_o : out std_logic_vector(31 downto 0);
timetag_core_seconds_lower_i : in std_logic_vector(31 downto 0);
timetag_core_seconds_lower_load_o : out std_logic;
timetag_core_coarse_o : out std_logic_vector(27 downto 0);
timetag_core_coarse_i : in std_logic_vector(27 downto 0);
timetag_core_coarse_load_o : out std_logic;
timetag_core_trig_tag_seconds_upper_i : in std_logic_vector(7 downto 0);
timetag_core_trig_tag_seconds_lower_i : in std_logic_vector(31 downto 0);
timetag_core_trig_tag_coarse_i : in std_logic_vector(27 downto 0);
timetag_core_acq_start_tag_seconds_upper_i : in std_logic_vector(7 downto 0);
timetag_core_acq_start_tag_seconds_lower_i : in std_logic_vector(31 downto 0);
timetag_core_acq_start_tag_coarse_i : in std_logic_vector(27 downto 0);
timetag_core_acq_stop_tag_seconds_upper_i : in std_logic_vector(7 downto 0);
timetag_core_acq_stop_tag_seconds_lower_i : in std_logic_vector(31 downto 0);
timetag_core_acq_stop_tag_coarse_i : in std_logic_vector(27 downto 0);
timetag_core_acq_end_tag_seconds_upper_i : in std_logic_vector(7 downto 0);
timetag_core_acq_end_tag_seconds_lower_i : in std_logic_vector(31 downto 0);
timetag_core_acq_end_tag_coarse_i : in std_logic_vector(27 downto 0));
end component timetag_core_regs;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_TRIG_TAG_META : std_logic_vector(31 downto 0) := x"6fc8ad2d";
constant c_ACQ_START_TAG_META : std_logic_vector(31 downto 0) := x"0d7c7c76";
constant c_ACQ_STOP_TAG_META : std_logic_vector(31 downto 0) := x"2b4e09ff";
constant c_ACQ_END_TAG_META : std_logic_vector(31 downto 0) := x"7f644cd2";
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal timetag_seconds : std_logic_vector(31 downto 0);
signal timetag_seconds_cnt : unsigned(31 downto 0);
signal timetag_seconds_load_value : std_logic_vector(31 downto 0);
signal timetag_seconds_load_en : std_logic;
signal timetag_coarse : std_logic_vector(31 downto 0);
signal timetag_coarse_cnt : unsigned(31 downto 0);
signal timetag_coarse_load_value : std_logic_vector(31 downto 0);
signal timetag_seconds : std_logic_vector(39 downto 0);
signal timetag_seconds_cnt : unsigned(39 downto 0);
signal timetag_seconds_load_value : std_logic_vector(39 downto 0);
signal timetag_seconds_load_en : std_logic_vector(1 downto 0);
signal timetag_coarse : std_logic_vector(27 downto 0);
signal timetag_coarse_cnt : unsigned(27 downto 0);
signal timetag_coarse_load_value : std_logic_vector(27 downto 0);
signal timetag_coarse_load_en : std_logic;
signal trig_tag : t_timetag;
signal acq_start_tag : t_timetag;
......@@ -150,41 +137,39 @@ begin
-- Wishbone interface to UTC core registers
------------------------------------------------------------------------------
cmp_timetag_core_regs : timetag_core_regs
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => open,
timetag_core_seconds_o => timetag_seconds_load_value,
timetag_core_seconds_i => timetag_seconds,
timetag_core_seconds_load_o => timetag_seconds_load_en,
timetag_core_coarse_o => timetag_coarse_load_value,
timetag_core_coarse_i => timetag_coarse,
timetag_core_coarse_load_o => timetag_coarse_load_en,
timetag_core_trig_tag_meta_i => trig_tag.meta,
timetag_core_trig_tag_seconds_i => trig_tag.seconds,
timetag_core_trig_tag_coarse_i => trig_tag.coarse,
timetag_core_trig_tag_fine_i => trig_tag.fine,
timetag_core_acq_start_tag_meta_i => acq_start_tag.meta,
timetag_core_acq_start_tag_seconds_i => acq_start_tag.seconds,
timetag_core_acq_start_tag_coarse_i => acq_start_tag.coarse,
timetag_core_acq_start_tag_fine_i => acq_start_tag.fine,
timetag_core_acq_stop_tag_meta_i => acq_stop_tag.meta,
timetag_core_acq_stop_tag_seconds_i => acq_stop_tag.seconds,
timetag_core_acq_stop_tag_coarse_i => acq_stop_tag.coarse,
timetag_core_acq_stop_tag_fine_i => acq_stop_tag.fine,
timetag_core_acq_end_tag_meta_i => acq_end_tag.meta,
timetag_core_acq_end_tag_seconds_i => acq_end_tag.seconds,
timetag_core_acq_end_tag_coarse_i => acq_end_tag.coarse,
timetag_core_acq_end_tag_fine_i => acq_end_tag.fine
);
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => open,
timetag_core_seconds_upper_o => timetag_seconds_load_value(39 downto 32),
timetag_core_seconds_upper_i => timetag_seconds(39 downto 32),
timetag_core_seconds_upper_load_o => timetag_seconds_load_en(1),
timetag_core_seconds_lower_o => timetag_seconds_load_value(31 downto 0),
timetag_core_seconds_lower_i => timetag_seconds(31 downto 0),
timetag_core_seconds_lower_load_o => timetag_seconds_load_en(0),
timetag_core_coarse_o => timetag_coarse_load_value,
timetag_core_coarse_i => timetag_coarse,
timetag_core_coarse_load_o => timetag_coarse_load_en,
timetag_core_trig_tag_seconds_upper_i => trig_tag.seconds(39 downto 32),
timetag_core_trig_tag_seconds_lower_i => trig_tag.seconds(31 downto 0),
timetag_core_trig_tag_coarse_i => trig_tag.coarse,
timetag_core_acq_start_tag_seconds_upper_i => acq_start_tag.seconds(39 downto 32),
timetag_core_acq_start_tag_seconds_lower_i => acq_start_tag.seconds(31 downto 0),
timetag_core_acq_start_tag_coarse_i => acq_start_tag.coarse,
timetag_core_acq_stop_tag_seconds_upper_i => acq_stop_tag.seconds(39 downto 32),
timetag_core_acq_stop_tag_seconds_lower_i => acq_stop_tag.seconds(31 downto 0),
timetag_core_acq_stop_tag_coarse_i => acq_stop_tag.coarse,
timetag_core_acq_end_tag_seconds_upper_i => acq_end_tag.seconds(39 downto 32),
timetag_core_acq_end_tag_seconds_lower_i => acq_end_tag.seconds(31 downto 0),
timetag_core_acq_end_tag_coarse_i => acq_end_tag.coarse);
------------------------------------------------------------------------------
-- UTC seconds counter
......@@ -194,8 +179,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
timetag_seconds_cnt <= (others => '0');
elsif timetag_seconds_load_en = '1' then
timetag_seconds_cnt <= unsigned(timetag_seconds_load_value);
elsif timetag_seconds_load_en(1) = '1' then
timetag_seconds_cnt(39 downto 32) <= unsigned(timetag_seconds_load_value(39 downto 32));
elsif timetag_seconds_load_en(0) = '1' then
timetag_seconds_cnt(31 downto 0) <= unsigned(timetag_seconds_load_value(31 downto 0));
elsif local_pps = '1' then
timetag_seconds_cnt <= timetag_seconds_cnt + 1;
end if;
......@@ -237,7 +224,6 @@ begin
if rst_n_i = '0' then
trig_tag.seconds <= (others => '0');
trig_tag.coarse <= (others => '0');
trig_tag.fine <= (others => '0');
elsif trigger_p_i = '1' then
trig_tag.seconds <= timetag_seconds;
trig_tag.coarse <= timetag_coarse;
......@@ -245,8 +231,7 @@ begin
end if;
end process p_trig_tag;
trig_tag.meta <= c_TRIG_TAG_META;
trig_tag_o <= trig_tag;
trig_tag_o <= trig_tag;
------------------------------------------------------------------------------
-- Last acquisition start event time-tag
......@@ -257,7 +242,6 @@ begin
if rst_n_i = '0' then
acq_start_tag.seconds <= (others => '0');
acq_start_tag.coarse <= (others => '0');
acq_start_tag.fine <= (others => '0');
elsif acq_start_p_i = '1' then
acq_start_tag.seconds <= timetag_seconds;
acq_start_tag.coarse <= timetag_coarse;
......@@ -265,8 +249,6 @@ begin
end if;
end process p_acq_start_tag;
acq_start_tag.meta <= c_ACQ_START_TAG_META;
------------------------------------------------------------------------------
-- Last acquisition stop event time-tag
------------------------------------------------------------------------------
......@@ -276,7 +258,6 @@ begin
if rst_n_i = '0' then
acq_stop_tag.seconds <= (others => '0');
acq_stop_tag.coarse <= (others => '0');
acq_stop_tag.fine <= (others => '0');
elsif acq_stop_p_i = '1' then
acq_stop_tag.seconds <= timetag_seconds;
acq_stop_tag.coarse <= timetag_coarse;
......@@ -284,8 +265,6 @@ begin
end if;
end process p_acq_stop_tag;
acq_stop_tag.meta <= c_ACQ_STOP_TAG_META;
------------------------------------------------------------------------------
-- Last acquisition end event time-tag
------------------------------------------------------------------------------
......@@ -295,7 +274,6 @@ begin
if rst_n_i = '0' then
acq_end_tag.seconds <= (others => '0');
acq_end_tag.coarse <= (others => '0');
acq_end_tag.fine <= (others => '0');
elsif acq_end_p_i = '1' then
acq_end_tag.seconds <= timetag_seconds;
acq_end_tag.coarse <= timetag_coarse;
......@@ -303,7 +281,5 @@ begin
end if;
end process p_acq_end_tag;
acq_end_tag.meta <= c_ACQ_END_TAG_META;
end rtl;
hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
View file @ 14262933
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Timetag core package
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: timetag_core_pkg.vhd (timetag_core_pkg.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 05-07-2013
--
-- version: 1.0
--
-- description: Package for timetag core
--
-- dependencies:
--
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title : Timetag core package
-- Project : FMC ADC 100M 14B 4CHA gateware
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : timetag_core_pkg.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-05
-- Last update: 2016-06-08
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for timetag core
-------------------------------------------------------------------------------
-- Copyright (c) 2013-2016 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
......@@ -28,11 +26,11 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2013-07-05 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......@@ -48,47 +46,35 @@ package timetag_core_pkg is
-- Types declaration
------------------------------------------------------------------------------
type t_timetag is record
meta : std_logic_vector(31 downto 0);
seconds : std_logic_vector(31 downto 0);
coarse : std_logic_vector(31 downto 0);
fine : std_logic_vector(31 downto 0);
seconds : std_logic_vector(39 downto 0);
coarse : std_logic_vector(27 downto 0);
end record t_timetag;
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component timetag_core
port (
-- Clock, reset
clk_i : in std_logic; -- Must be 125MHz
rst_n_i : in std_logic;
-- Input pulses to time-tag
trigger_p_i : in std_logic;
acq_start_p_i : in std_logic;
acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic;
-- Trigger time-tag output
trig_tag_o : out t_timetag;
-- Wishbone interface
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end component timetag_core;
component timetag_core is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
trigger_p_i : in std_logic;
acq_start_p_i : in std_logic;
acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic;
wr_enabled_i : in std_logic;
trig_tag_o : out t_timetag;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
end component timetag_core;
end timetag_core_pkg;
package body timetag_core_pkg is
end timetag_core_pkg;
hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd
View file @ 14262933
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/timetag_core_regs.vhd
-- Author : auto-generated by wbgen2 from timetag_core_regs.wb
-- Created : Thu Jul 4 18:04:57 2013
-- Created : Wed Jun 8 10:54:43 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
......@@ -18,7 +18,7 @@ entity timetag_core_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -27,46 +27,42 @@ entity timetag_core_regs is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'Timetag seconds' in reg: 'Timetag seconds register'
timetag_core_seconds_o : out std_logic_vector(31 downto 0);
timetag_core_seconds_i : in std_logic_vector(31 downto 0);
timetag_core_seconds_load_o : out std_logic;
-- Port for std_logic_vector field: 'Timetag seconds' in reg: 'Timetag seconds register (upper)'
timetag_core_seconds_upper_o : out std_logic_vector(7 downto 0);
timetag_core_seconds_upper_i : in std_logic_vector(7 downto 0);
timetag_core_seconds_upper_load_o : out std_logic;
-- Port for std_logic_vector field: 'Timetag seconds' in reg: 'Timetag seconds register (lower)'
timetag_core_seconds_lower_o : out std_logic_vector(31 downto 0);
timetag_core_seconds_lower_i : in std_logic_vector(31 downto 0);
timetag_core_seconds_lower_load_o : out std_logic;
-- Port for std_logic_vector field: 'Timetag coarse time' in reg: 'Timetag coarse time register, system clock ticks (125MHz)'
timetag_core_coarse_o : out std_logic_vector(31 downto 0);
timetag_core_coarse_i : in std_logic_vector(31 downto 0);
timetag_core_coarse_o : out std_logic_vector(27 downto 0);
timetag_core_coarse_i : in std_logic_vector(27 downto 0);
timetag_core_coarse_load_o : out std_logic;
-- Port for std_logic_vector field: 'Trigger time-tag metadata' in reg: 'Trigger time-tag metadata register'
timetag_core_trig_tag_meta_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Trigger time-tag seconds' in reg: 'Trigger time-tag seconds register'
timetag_core_trig_tag_seconds_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Trigger time-tag seconds' in reg: 'Trigger time-tag seconds register (upper)'
timetag_core_trig_tag_seconds_upper_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Trigger time-tag seconds' in reg: 'Trigger time-tag seconds register (lower)'
timetag_core_trig_tag_seconds_lower_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Trigger time-tag coarse time' in reg: 'Trigger time-tag coarse time (system clock ticks 125MHz) register'
timetag_core_trig_tag_coarse_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Trigger time-tag fine time' in reg: 'Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)'
timetag_core_trig_tag_fine_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition start time-tag metadata' in reg: 'Acquisition start time-tag metadata register'
timetag_core_acq_start_tag_meta_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition start time-tag seconds' in reg: 'Acquisition start time-tag seconds register'
timetag_core_acq_start_tag_seconds_i : in std_logic_vector(31 downto 0);
timetag_core_trig_tag_coarse_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Acquisition start time-tag seconds' in reg: 'Acquisition start time-tag seconds register (upper)'
timetag_core_acq_start_tag_seconds_upper_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Acquisition start time-tag seconds' in reg: 'Acquisition start time-tag seconds register (lower)'
timetag_core_acq_start_tag_seconds_lower_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition start time-tag coarse time' in reg: 'Acquisition start time-tag coarse time (system clock ticks 125MHz) register'
timetag_core_acq_start_tag_coarse_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition start time-tag fine time' in reg: 'Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)'
timetag_core_acq_start_tag_fine_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag metadata' in reg: 'Acquisition stop time-tag metadata register'
timetag_core_acq_stop_tag_meta_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag seconds' in reg: 'Acquisition stop time-tag seconds register'
timetag_core_acq_stop_tag_seconds_i : in std_logic_vector(31 downto 0);
timetag_core_acq_start_tag_coarse_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag seconds' in reg: 'Acquisition stop time-tag seconds register (upper)'
timetag_core_acq_stop_tag_seconds_upper_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag seconds' in reg: 'Acquisition stop time-tag seconds register (lower)'
timetag_core_acq_stop_tag_seconds_lower_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag coarse time' in reg: 'Acquisition stop time-tag coarse time (system clock ticks 125MHz) register'
timetag_core_acq_stop_tag_coarse_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag fine time' in reg: 'Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)'
timetag_core_acq_stop_tag_fine_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition end time-tag metadata' in reg: 'Acquisition end time-tag metadata register'
timetag_core_acq_end_tag_meta_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition end time-tag seconds' in reg: 'Acquisition end time-tag seconds register'
timetag_core_acq_end_tag_seconds_i : in std_logic_vector(31 downto 0);
timetag_core_acq_stop_tag_coarse_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Acquisition end time-tag seconds' in reg: 'Acquisition end time-tag seconds register (upper)'
timetag_core_acq_end_tag_seconds_upper_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Acquisition end time-tag seconds' in reg: 'Acquisition end time-tag seconds register (lower)'
timetag_core_acq_end_tag_seconds_lower_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition end time-tag coarse time' in reg: 'Acquisition end time-tag coarse time (system clock ticks 125MHz) register'
timetag_core_acq_end_tag_coarse_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition end time-tag fine time' in reg: 'Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility)'
timetag_core_acq_end_tag_fine_i : in std_logic_vector(31 downto 0)
timetag_core_acq_end_tag_coarse_i : in std_logic_vector(27 downto 0)
);
end timetag_core_regs;
......@@ -76,7 +72,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -99,7 +95,8 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
timetag_core_seconds_load_o <= '0';
timetag_core_seconds_upper_load_o <= '0';
timetag_core_seconds_lower_load_o <= '0';
timetag_core_coarse_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
......@@ -107,124 +104,249 @@ begin
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
timetag_core_seconds_load_o <= '0';
timetag_core_seconds_upper_load_o <= '0';
timetag_core_seconds_lower_load_o <= '0';
timetag_core_coarse_load_o <= '0';
ack_in_progress <= '0';
else
timetag_core_seconds_load_o <= '0';
timetag_core_seconds_upper_load_o <= '0';
timetag_core_seconds_lower_load_o <= '0';
timetag_core_coarse_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
timetag_core_seconds_load_o <= '1';
timetag_core_seconds_upper_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= timetag_core_seconds_i;
rddata_reg(7 downto 0) <= timetag_core_seconds_upper_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
timetag_core_coarse_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= timetag_core_coarse_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
when "0001" =>
if (wb_we_i = '1') then
timetag_core_seconds_lower_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= timetag_core_trig_tag_meta_i;
rddata_reg(31 downto 0) <= timetag_core_seconds_lower_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_trig_tag_seconds_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_trig_tag_coarse_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
when "0010" =>
if (wb_we_i = '1') then
timetag_core_coarse_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= timetag_core_trig_tag_fine_i;
rddata_reg(27 downto 0) <= timetag_core_coarse_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
when "0011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_start_tag_meta_i;
rddata_reg(7 downto 0) <= timetag_core_trig_tag_seconds_upper_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
when "0100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_start_tag_seconds_i;
rddata_reg(31 downto 0) <= timetag_core_trig_tag_seconds_lower_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
when "0101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_start_tag_coarse_i;
rddata_reg(27 downto 0) <= timetag_core_trig_tag_coarse_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
when "0110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_start_tag_fine_i;
rddata_reg(7 downto 0) <= timetag_core_acq_start_tag_seconds_upper_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
when "0111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_stop_tag_meta_i;
rddata_reg(31 downto 0) <= timetag_core_acq_start_tag_seconds_lower_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
when "1000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_stop_tag_seconds_i;
rddata_reg(27 downto 0) <= timetag_core_acq_start_tag_coarse_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
when "1001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_stop_tag_coarse_i;
rddata_reg(7 downto 0) <= timetag_core_acq_stop_tag_seconds_upper_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
when "1010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_stop_tag_fine_i;
rddata_reg(31 downto 0) <= timetag_core_acq_stop_tag_seconds_lower_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
when "1011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_end_tag_meta_i;
rddata_reg(27 downto 0) <= timetag_core_acq_stop_tag_coarse_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
when "1100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_end_tag_seconds_i;
rddata_reg(7 downto 0) <= timetag_core_acq_end_tag_seconds_upper_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
when "1101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_end_tag_coarse_i;
rddata_reg(31 downto 0) <= timetag_core_acq_end_tag_seconds_lower_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
when "1110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_end_tag_fine_i;
rddata_reg(27 downto 0) <= timetag_core_acq_end_tag_coarse_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
......@@ -241,25 +363,23 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Timetag seconds
timetag_core_seconds_o <= wrdata_reg(31 downto 0);
timetag_core_seconds_upper_o <= wrdata_reg(7 downto 0);
-- Timetag seconds
timetag_core_seconds_lower_o <= wrdata_reg(31 downto 0);
-- Timetag coarse time
timetag_core_coarse_o <= wrdata_reg(31 downto 0);
-- Trigger time-tag metadata
timetag_core_coarse_o <= wrdata_reg(27 downto 0);
-- Trigger time-tag seconds
-- Trigger time-tag seconds
-- Trigger time-tag coarse time
-- Trigger time-tag fine time
-- Acquisition start time-tag metadata
-- Acquisition start time-tag seconds
-- Acquisition start time-tag seconds
-- Acquisition start time-tag coarse time
-- Acquisition start time-tag fine time
-- Acquisition stop time-tag metadata
-- Acquisition stop time-tag seconds
-- Acquisition stop time-tag seconds
-- Acquisition stop time-tag coarse time
-- Acquisition stop time-tag fine time
-- Acquisition end time-tag metadata
-- Acquisition end time-tag seconds
-- Acquisition end time-tag seconds
-- Acquisition end time-tag coarse time
-- Acquisition end time-tag fine time
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
hdl/ip_cores/timetag_core/wb_gen/Makefile
View file @ 14262933
WBGEN2=~/projects/wbgen2/wbgen2
WBGEN2=$(shell which wbgen2)
RTL=../rtl/
TEX=../../../../doc/manual/
......
hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.h
View file @ 14262933
......@@ -3,7 +3,7 @@
* File : timetag_core_regs.h
* Author : auto-generated by wbgen2 from timetag_core_regs.wb
* Created : Thu Jul 4 18:04:57 2013
* Created : Wed Jun 8 10:54:43 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
......@@ -31,79 +31,67 @@
#endif
/* definitions for register: Timetag seconds register */
/* definitions for register: Timetag seconds register (upper) */
/* definitions for register: Timetag seconds register (lower) */
/* definitions for register: Timetag coarse time register, system clock ticks (125MHz) */
/* definitions for register: Trigger time-tag metadata register */
/* definitions for register: Trigger time-tag seconds register (upper) */
/* definitions for register: Trigger time-tag seconds register */
/* definitions for register: Trigger time-tag seconds register (lower) */
/* definitions for register: Trigger time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Trigger time-tag fine time register, always 0 (used for time-tag format compatibility) */
/* definitions for register: Acquisition start time-tag metadata register */
/* definitions for register: Acquisition start time-tag seconds register (upper) */
/* definitions for register: Acquisition start time-tag seconds register */
/* definitions for register: Acquisition start time-tag seconds register (lower) */
/* definitions for register: Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility) */
/* definitions for register: Acquisition stop time-tag metadata register */
/* definitions for register: Acquisition stop time-tag seconds register (upper) */
/* definitions for register: Acquisition stop time-tag seconds register */
/* definitions for register: Acquisition stop time-tag seconds register (lower) */
/* definitions for register: Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility) */
/* definitions for register: Acquisition end time-tag seconds register (upper) */
/* definitions for register: Acquisition end time-tag metadata register */
/* definitions for register: Acquisition end time-tag seconds register */
/* definitions for register: Acquisition end time-tag seconds register (lower) */
/* definitions for register: Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility) */
PACKED struct TIMETAG_CORE_WB {
/* [0x0]: REG Timetag seconds register */
uint32_t SECONDS;
/* [0x4]: REG Timetag coarse time register, system clock ticks (125MHz) */
/* [0x0]: REG Timetag seconds register (upper) */
uint32_t SECONDS_UPPER;
/* [0x4]: REG Timetag seconds register (lower) */
uint32_t SECONDS_LOWER;
/* [0x8]: REG Timetag coarse time register, system clock ticks (125MHz) */
uint32_t COARSE;
/* [0x8]: REG Trigger time-tag metadata register */
uint32_t TRIG_TAG_META;
/* [0xc]: REG Trigger time-tag seconds register */
uint32_t TRIG_TAG_SECONDS;
/* [0x10]: REG Trigger time-tag coarse time (system clock ticks 125MHz) register */
/* [0xc]: REG Trigger time-tag seconds register (upper) */
uint32_t TRIG_TAG_SECONDS_UPPER;
/* [0x10]: REG Trigger time-tag seconds register (lower) */
uint32_t TRIG_TAG_SECONDS_LOWER;
/* [0x14]: REG Trigger time-tag coarse time (system clock ticks 125MHz) register */
uint32_t TRIG_TAG_COARSE;
/* [0x14]: REG Trigger time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t TRIG_TAG_FINE;
/* [0x18]: REG Acquisition start time-tag metadata register */
uint32_t ACQ_START_TAG_META;
/* [0x1c]: REG Acquisition start time-tag seconds register */
uint32_t ACQ_START_TAG_SECONDS;
/* [0x18]: REG Acquisition start time-tag seconds register (upper) */
uint32_t ACQ_START_TAG_SECONDS_UPPER;
/* [0x1c]: REG Acquisition start time-tag seconds register (lower) */
uint32_t ACQ_START_TAG_SECONDS_LOWER;
/* [0x20]: REG Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_START_TAG_COARSE;
/* [0x24]: REG Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t ACQ_START_TAG_FINE;
/* [0x28]: REG Acquisition stop time-tag metadata register */
uint32_t ACQ_STOP_TAG_META;
/* [0x2c]: REG Acquisition stop time-tag seconds register */
uint32_t ACQ_STOP_TAG_SECONDS;
/* [0x30]: REG Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
/* [0x24]: REG Acquisition stop time-tag seconds register (upper) */
uint32_t ACQ_STOP_TAG_SECONDS_UPPER;
/* [0x28]: REG Acquisition stop time-tag seconds register (lower) */
uint32_t ACQ_STOP_TAG_SECONDS_LOWER;
/* [0x2c]: REG Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_STOP_TAG_COARSE;
/* [0x34]: REG Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t ACQ_STOP_TAG_FINE;
/* [0x38]: REG Acquisition end time-tag metadata register */
uint32_t ACQ_END_TAG_META;
/* [0x3c]: REG Acquisition end time-tag seconds register */
uint32_t ACQ_END_TAG_SECONDS;
/* [0x40]: REG Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
/* [0x30]: REG Acquisition end time-tag seconds register (upper) */
uint32_t ACQ_END_TAG_SECONDS_UPPER;
/* [0x34]: REG Acquisition end time-tag seconds register (lower) */
uint32_t ACQ_END_TAG_SECONDS_LOWER;
/* [0x38]: REG Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_END_TAG_COARSE;
/* [0x44]: REG Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t ACQ_END_TAG_FINE;
};
#endif
hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.htm
View file @ 14262933
......@@ -34,24 +34,21 @@
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Timetag seconds register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Timetag coarse time register, system clock ticks (125MHz)</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Trigger time-tag metadata register</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Trigger time-tag seconds register</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Trigger time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Acquisition start time-tag metadata register</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Acquisition start time-tag seconds register</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Timetag seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Timetag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Timetag coarse time register, system clock ticks (125MHz)</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Trigger time-tag seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Trigger time-tag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Trigger time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Acquisition start time-tag seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Acquisition start time-tag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Acquisition start time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">Acquisition stop time-tag metadata register</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">Acquisition stop time-tag seconds register</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">Acquisition end time-tag metadata register</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">Acquisition end time-tag seconds register</a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">Acquisition end time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility)</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Acquisition stop time-tag seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">Acquisition stop time-tag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">Acquisition end time-tag seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">Acquisition end time-tag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">Acquisition end time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -79,13 +76,13 @@ C prefix
REG
</td>
<td >
<A href="#SECONDS">Timetag seconds register</a>
<A href="#SECONDS_UPPER">Timetag seconds register (upper)</a>
</td>
<td class="td_code">
timetag_core_seconds
timetag_core_seconds_upper
</td>
<td class="td_code">
SECONDS
SECONDS_UPPER
</td>
</tr>
<tr class="tr_even">
......@@ -96,13 +93,13 @@ SECONDS
REG
</td>
<td >
<A href="#COARSE">Timetag coarse time register, system clock ticks (125MHz)</a>
<A href="#SECONDS_LOWER">Timetag seconds register (lower)</a>
</td>
<td class="td_code">
timetag_core_coarse
timetag_core_seconds_lower
</td>
<td class="td_code">
COARSE
SECONDS_LOWER
</td>
</tr>
<tr class="tr_odd">
......@@ -113,13 +110,13 @@ COARSE
REG
</td>
<td >
<A href="#TRIG_TAG_META">Trigger time-tag metadata register</a>
<A href="#COARSE">Timetag coarse time register, system clock ticks (125MHz)</a>
</td>
<td class="td_code">
timetag_core_trig_tag_meta
timetag_core_coarse
</td>
<td class="td_code">
TRIG_TAG_META
COARSE
</td>
</tr>
<tr class="tr_even">
......@@ -130,13 +127,13 @@ TRIG_TAG_META
REG
</td>
<td >
<A href="#TRIG_TAG_SECONDS">Trigger time-tag seconds register</a>
<A href="#TRIG_TAG_SECONDS_UPPER">Trigger time-tag seconds register (upper)</a>
</td>
<td class="td_code">
timetag_core_trig_tag_seconds
timetag_core_trig_tag_seconds_upper
</td>
<td class="td_code">
TRIG_TAG_SECONDS
TRIG_TAG_SECONDS_UPPER
</td>
</tr>
<tr class="tr_odd">
......@@ -147,13 +144,13 @@ TRIG_TAG_SECONDS
REG
</td>
<td >
<A href="#TRIG_TAG_COARSE">Trigger time-tag coarse time (system clock ticks 125MHz) register</a>
<A href="#TRIG_TAG_SECONDS_LOWER">Trigger time-tag seconds register (lower)</a>
</td>
<td class="td_code">
timetag_core_trig_tag_coarse
timetag_core_trig_tag_seconds_lower
</td>
<td class="td_code">
TRIG_TAG_COARSE
TRIG_TAG_SECONDS_LOWER
</td>
</tr>
<tr class="tr_even">
......@@ -164,13 +161,13 @@ TRIG_TAG_COARSE
REG
</td>
<td >
<A href="#TRIG_TAG_FINE">Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)</a>
<A href="#TRIG_TAG_COARSE">Trigger time-tag coarse time (system clock ticks 125MHz) register</a>
</td>
<td class="td_code">
timetag_core_trig_tag_fine
timetag_core_trig_tag_coarse
</td>
<td class="td_code">
TRIG_TAG_FINE
TRIG_TAG_COARSE
</td>
</tr>
<tr class="tr_odd">
......@@ -181,13 +178,13 @@ TRIG_TAG_FINE
REG
</td>
<td >
<A href="#ACQ_START_TAG_META">Acquisition start time-tag metadata register</a>
<A href="#ACQ_START_TAG_SECONDS_UPPER">Acquisition start time-tag seconds register (upper)</a>
</td>
<td class="td_code">
timetag_core_acq_start_tag_meta
timetag_core_acq_start_tag_seconds_upper
</td>
<td class="td_code">
ACQ_START_TAG_META
ACQ_START_TAG_SECONDS_UPPER
</td>
</tr>
<tr class="tr_even">
......@@ -198,13 +195,13 @@ ACQ_START_TAG_META
REG
</td>
<td >
<A href="#ACQ_START_TAG_SECONDS">Acquisition start time-tag seconds register</a>
<A href="#ACQ_START_TAG_SECONDS_LOWER">Acquisition start time-tag seconds register (lower)</a>
</td>
<td class="td_code">
timetag_core_acq_start_tag_seconds
timetag_core_acq_start_tag_seconds_lower
</td>
<td class="td_code">
ACQ_START_TAG_SECONDS
ACQ_START_TAG_SECONDS_LOWER
</td>
</tr>
<tr class="tr_odd">
......@@ -232,13 +229,13 @@ ACQ_START_TAG_COARSE
REG
</td>
<td >
<A href="#ACQ_START_TAG_FINE">Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)</a>
<A href="#ACQ_STOP_TAG_SECONDS_UPPER">Acquisition stop time-tag seconds register (upper)</a>
</td>
<td class="td_code">
timetag_core_acq_start_tag_fine
timetag_core_acq_stop_tag_seconds_upper
</td>
<td class="td_code">
ACQ_START_TAG_FINE
ACQ_STOP_TAG_SECONDS_UPPER
</td>
</tr>
<tr class="tr_odd">
......@@ -249,13 +246,13 @@ ACQ_START_TAG_FINE
REG
</td>
<td >
<A href="#ACQ_STOP_TAG_META">Acquisition stop time-tag metadata register</a>
<A href="#ACQ_STOP_TAG_SECONDS_LOWER">Acquisition stop time-tag seconds register (lower)</a>
</td>
<td class="td_code">
timetag_core_acq_stop_tag_meta
timetag_core_acq_stop_tag_seconds_lower
</td>
<td class="td_code">
ACQ_STOP_TAG_META
ACQ_STOP_TAG_SECONDS_LOWER
</td>
</tr>
<tr class="tr_even">
......@@ -266,23 +263,6 @@ ACQ_STOP_TAG_META
REG
</td>
<td >
<A href="#ACQ_STOP_TAG_SECONDS">Acquisition stop time-tag seconds register</a>
</td>
<td class="td_code">
timetag_core_acq_stop_tag_seconds
</td>
<td class="td_code">
ACQ_STOP_TAG_SECONDS
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0xc
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_STOP_TAG_COARSE">Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a>
</td>
<td class="td_code">
......@@ -292,60 +272,43 @@ timetag_core_acq_stop_tag_coarse
ACQ_STOP_TAG_COARSE
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0xd
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_STOP_TAG_FINE">Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)</a>
</td>
<td class="td_code">
timetag_core_acq_stop_tag_fine
</td>
<td class="td_code">
ACQ_STOP_TAG_FINE
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0xe
0xc
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_END_TAG_META">Acquisition end time-tag metadata register</a>
<A href="#ACQ_END_TAG_SECONDS_UPPER">Acquisition end time-tag seconds register (upper)</a>
</td>
<td class="td_code">
timetag_core_acq_end_tag_meta
timetag_core_acq_end_tag_seconds_upper
</td>
<td class="td_code">
ACQ_END_TAG_META
ACQ_END_TAG_SECONDS_UPPER
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0xf
0xd
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_END_TAG_SECONDS">Acquisition end time-tag seconds register</a>
<A href="#ACQ_END_TAG_SECONDS_LOWER">Acquisition end time-tag seconds register (lower)</a>
</td>
<td class="td_code">
timetag_core_acq_end_tag_seconds
timetag_core_acq_end_tag_seconds_lower
</td>
<td class="td_code">
ACQ_END_TAG_SECONDS
ACQ_END_TAG_SECONDS_LOWER
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x10
0xe
</td>
<td >
REG
......@@ -360,23 +323,6 @@ timetag_core_acq_end_tag_coarse
ACQ_END_TAG_COARSE
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x11
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_END_TAG_FINE">Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility)</a>
</td>
<td class="td_code">
timetag_core_acq_end_tag_fine
</td>
<td class="td_code">
ACQ_END_TAG_FINE
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
......@@ -392,7 +338,7 @@ rst_n_i
</td>
<td class="td_pblock_right">
<b>Timetag seconds register:</b>
<b>Timetag seconds register (upper):</b>
</td>
<td class="td_arrow_right">
......@@ -409,7 +355,7 @@ clk_sys_i
</td>
<td class="td_pblock_right">
timetag_core_seconds_o[31:0]
timetag_core_seconds_upper_o[7:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -420,13 +366,13 @@ timetag_core_seconds_o[31:0]
&rArr;
</td>
<td class="td_pblock_left">
wb_adr_i[4:0]
wb_adr_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
timetag_core_seconds_i[31:0]
timetag_core_seconds_upper_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -443,7 +389,7 @@ wb_dat_i[31:0]
</td>
<td class="td_pblock_right">
timetag_core_seconds_load_o
timetag_core_seconds_upper_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -477,7 +423,7 @@ wb_cyc_i
</td>
<td class="td_pblock_right">
<b>Timetag coarse time register, system clock ticks (125MHz):</b>
<b>Timetag seconds register (lower):</b>
</td>
<td class="td_arrow_right">
......@@ -494,7 +440,7 @@ wb_sel_i[3:0]
</td>
<td class="td_pblock_right">
timetag_core_coarse_o[31:0]
timetag_core_seconds_lower_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -511,7 +457,7 @@ wb_stb_i
</td>
<td class="td_pblock_right">
timetag_core_coarse_i[31:0]
timetag_core_seconds_lower_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -528,7 +474,7 @@ wb_we_i
</td>
<td class="td_pblock_right">
timetag_core_coarse_load_o
timetag_core_seconds_lower_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -562,41 +508,7 @@ wb_stall_o
</td>
<td class="td_pblock_right">
<b>Trigger time-tag metadata register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
timetag_core_trig_tag_meta_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
<b>Timetag coarse time register, system clock ticks (125MHz):</b>
</td>
<td class="td_arrow_right">
......@@ -613,10 +525,10 @@ timetag_core_trig_tag_meta_i[31:0]
</td>
<td class="td_pblock_right">
<b>Trigger time-tag seconds register:</b>
timetag_core_coarse_o[27:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -630,7 +542,7 @@ timetag_core_trig_tag_meta_i[31:0]
</td>
<td class="td_pblock_right">
timetag_core_trig_tag_seconds_i[31:0]
timetag_core_coarse_i[27:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -642,49 +554,15 @@ timetag_core_trig_tag_seconds_i[31:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Trigger time-tag coarse time (system clock ticks 125MHz) register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
timetag_core_trig_tag_coarse_i[31:0]
timetag_core_coarse_load_o
</td>
<td class="td_arrow_right">
&lArr;
&rarr;
</td>
</tr>
<tr>
......@@ -715,7 +593,7 @@ timetag_core_trig_tag_coarse_i[31:0]
</td>
<td class="td_pblock_right">
<b>Trigger time-tag fine time register, always 0 (used for time-tag format compatibility):</b>
<b>Trigger time-tag seconds register (upper):</b>
</td>
<td class="td_arrow_right">
......@@ -732,7 +610,7 @@ timetag_core_trig_tag_coarse_i[31:0]
</td>
<td class="td_pblock_right">
timetag_core_trig_tag_fine_i[31:0]
timetag_core_trig_tag_seconds_upper_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -766,7 +644,7 @@ timetag_core_trig_tag_fine_i[31:0]
</td>
<td class="td_pblock_right">
<b>Acquisition start time-tag metadata register:</b>
<b>Trigger time-tag seconds register (lower):</b>
</td>
<td class="td_arrow_right">
......@@ -783,7 +661,7 @@ timetag_core_trig_tag_fine_i[31:0]
</td>
<td class="td_pblock_right">
timetag_core_acq_start_tag_meta_i[31:0]
timetag_core_trig_tag_seconds_lower_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -817,7 +695,7 @@ timetag_core_acq_start_tag_meta_i[31:0]
</td>
<td class="td_pblock_right">
<b>Acquisition start time-tag seconds register:</b>
<b>Trigger time-tag coarse time (system clock ticks 125MHz) register:</b>
</td>
<td class="td_arrow_right">
......@@ -834,7 +712,7 @@ timetag_core_acq_start_tag_meta_i[31:0]
</td>
<td class="td_pblock_right">
timetag_core_acq_start_tag_seconds_i[31:0]
timetag_core_trig_tag_coarse_i[27:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -868,7 +746,7 @@ timetag_core_acq_start_tag_seconds_i[31:0]
</td>
<td class="td_pblock_right">
<b>Acquisition start time-tag coarse time (system clock ticks 125MHz) register:</b>
<b>Acquisition start time-tag seconds register (upper):</b>
</td>
<td class="td_arrow_right">
......@@ -885,7 +763,7 @@ timetag_core_acq_start_tag_seconds_i[31:0]
</td>
<td class="td_pblock_right">
timetag_core_acq_start_tag_coarse_i[31:0]
timetag_core_acq_start_tag_seconds_upper_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -919,7 +797,7 @@ timetag_core_acq_start_tag_coarse_i[31:0]
</td>
<td class="td_pblock_right">
<b>Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility):</b>
<b>Acquisition start time-tag seconds register (lower):</b>
</td>
<td class="td_arrow_right">
......@@ -936,7 +814,7 @@ timetag_core_acq_start_tag_coarse_i[31:0]
</td>
<td class="td_pblock_right">
timetag_core_acq_start_tag_fine_i[31:0]
timetag_core_acq_start_tag_seconds_lower_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -970,7 +848,7 @@ timetag_core_acq_start_tag_fine_i[31:0]
</td>
<td class="td_pblock_right">
<b>Acquisition stop time-tag metadata register:</b>
<b>Acquisition start time-tag coarse time (system clock ticks 125MHz) register:</b>
</td>
<td class="td_arrow_right">
......@@ -987,7 +865,7 @@ timetag_core_acq_start_tag_fine_i[31:0]
</td>
<td class="td_pblock_right">
timetag_core_acq_stop_tag_meta_i[31:0]
timetag_core_acq_start_tag_coarse_i[27:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1021,7 +899,7 @@ timetag_core_acq_stop_tag_meta_i[31:0]
</td>
<td class="td_pblock_right">
<b>Acquisition stop time-tag seconds register:</b>
<b>Acquisition stop time-tag seconds register (upper):</b>
</td>
<td class="td_arrow_right">
......@@ -1038,7 +916,7 @@ timetag_core_acq_stop_tag_meta_i[31:0]
</td>
<td class="td_pblock_right">
timetag_core_acq_stop_tag_seconds_i[31:0]
timetag_core_acq_stop_tag_seconds_upper_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1072,7 +950,7 @@ timetag_core_acq_stop_tag_seconds_i[31:0]
</td>
<td class="td_pblock_right">
<b>Acquisition stop time-tag coarse time (system clock ticks 125MHz) register:</b>
<b>Acquisition stop time-tag seconds register (lower):</b>
</td>
<td class="td_arrow_right">
......@@ -1089,7 +967,7 @@ timetag_core_acq_stop_tag_seconds_i[31:0]
</td>
<td class="td_pblock_right">
timetag_core_acq_stop_tag_coarse_i[31:0]
timetag_core_acq_stop_tag_seconds_lower_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1123,7 +1001,7 @@ timetag_core_acq_stop_tag_coarse_i[31:0]
</td>
<td class="td_pblock_right">
<b>Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility):</b>
<b>Acquisition stop time-tag coarse time (system clock ticks 125MHz) register:</b>
</td>
<td class="td_arrow_right">
......@@ -1140,7 +1018,7 @@ timetag_core_acq_stop_tag_coarse_i[31:0]
</td>
<td class="td_pblock_right">
timetag_core_acq_stop_tag_fine_i[31:0]
timetag_core_acq_stop_tag_coarse_i[27:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1174,7 +1052,7 @@ timetag_core_acq_stop_tag_fine_i[31:0]
</td>
<td class="td_pblock_right">
<b>Acquisition end time-tag metadata register:</b>
<b>Acquisition end time-tag seconds register (upper):</b>
</td>
<td class="td_arrow_right">
......@@ -1191,7 +1069,7 @@ timetag_core_acq_stop_tag_fine_i[31:0]
</td>
<td class="td_pblock_right">
timetag_core_acq_end_tag_meta_i[31:0]
timetag_core_acq_end_tag_seconds_upper_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1225,7 +1103,7 @@ timetag_core_acq_end_tag_meta_i[31:0]
</td>
<td class="td_pblock_right">
<b>Acquisition end time-tag seconds register:</b>
<b>Acquisition end time-tag seconds register (lower):</b>
</td>
<td class="td_arrow_right">
......@@ -1242,7 +1120,7 @@ timetag_core_acq_end_tag_meta_i[31:0]
</td>
<td class="td_pblock_right">
timetag_core_acq_end_tag_seconds_i[31:0]
timetag_core_acq_end_tag_seconds_lower_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1293,58 +1171,7 @@ timetag_core_acq_end_tag_seconds_i[31:0]
</td>
<td class="td_pblock_right">
timetag_core_acq_end_tag_coarse_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
timetag_core_acq_end_tag_fine_i[31:0]
timetag_core_acq_end_tag_coarse_i[27:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1353,15 +1180,15 @@ timetag_core_acq_end_tag_fine_i[31:0]
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="SECONDS"></a>
<h3><a name="sect_3_1">3.1. Timetag seconds register</a></h3>
<a name="SECONDS_UPPER"></a>
<h3><a name="sect_3_1">3.1. Timetag seconds register (upper)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_seconds
timetag_core_seconds_upper
</td>
</tr>
<tr>
......@@ -1377,7 +1204,7 @@ timetag_core_seconds
<b>C prefix: </b>
</td>
<td class="td_code">
SECONDS
SECONDS_UPPER
</td>
</tr>
<tr>
......@@ -1390,7 +1217,7 @@ SECONDS
</tr>
</table>
<p>
Seconds counter. Incremented everytime the coarse counter overflows.
8 upper bits of seconds counter. Incremented everytime the coarse counter overflows.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -1420,29 +1247,29 @@ Seconds counter. Incremented everytime the coarse counter overflows.
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS[31:24]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -1474,29 +1301,29 @@ SECONDS[31:24]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS[23:16]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -1528,29 +1355,29 @@ SECONDS[23:16]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -1583,7 +1410,7 @@ SECONDS[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS[7:0]
SECONDS_UPPER[7:0]
</td>
<td >
......@@ -1610,18 +1437,18 @@ SECONDS[7:0]
</table>
<ul>
<li><b>
SECONDS
SECONDS_UPPER
</b>[<i>read/write</i>]: Timetag seconds
</ul>
<a name="COARSE"></a>
<h3><a name="sect_3_2">3.2. Timetag coarse time register, system clock ticks (125MHz)</a></h3>
<a name="SECONDS_LOWER"></a>
<h3><a name="sect_3_2">3.2. Timetag seconds register (lower)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_coarse
timetag_core_seconds_lower
</td>
</tr>
<tr>
......@@ -1637,7 +1464,7 @@ timetag_core_coarse
<b>C prefix: </b>
</td>
<td class="td_code">
COARSE
SECONDS_LOWER
</td>
</tr>
<tr>
......@@ -1650,7 +1477,7 @@ COARSE
</tr>
</table>
<p>
Coarse time counter clocked by 125MHz system clock.<br>Counts from 0 to 125000000.
32 lower bits of seconds counter. Incremented everytime the coarse counter overflows.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -1681,7 +1508,7 @@ Coarse time counter clocked by 125MHz system clock.<br>Counts from 0 to 12500000
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[31:24]
SECONDS_LOWER[31:24]
</td>
<td >
......@@ -1735,7 +1562,7 @@ COARSE[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[23:16]
SECONDS_LOWER[23:16]
</td>
<td >
......@@ -1789,7 +1616,7 @@ COARSE[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[15:8]
SECONDS_LOWER[15:8]
</td>
<td >
......@@ -1843,7 +1670,7 @@ COARSE[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[7:0]
SECONDS_LOWER[7:0]
</td>
<td >
......@@ -1870,18 +1697,18 @@ COARSE[7:0]
</table>
<ul>
<li><b>
COARSE
</b>[<i>read/write</i>]: Timetag coarse time
SECONDS_LOWER
</b>[<i>read/write</i>]: Timetag seconds
</ul>
<a name="TRIG_TAG_META"></a>
<h3><a name="sect_3_3">3.3. Trigger time-tag metadata register</a></h3>
<a name="COARSE"></a>
<h3><a name="sect_3_3">3.3. Timetag coarse time register, system clock ticks (125MHz)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_trig_tag_meta
timetag_core_coarse
</td>
</tr>
<tr>
......@@ -1897,7 +1724,7 @@ timetag_core_trig_tag_meta
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_TAG_META
COARSE
</td>
</tr>
<tr>
......@@ -1909,6 +1736,9 @@ TRIG_TAG_META
</td>
</tr>
</table>
<p>
Coarse time counter clocked by 125MHz system clock.<br>Counts from 0 to 125000000.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
......@@ -1937,20 +1767,20 @@ TRIG_TAG_META
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_META[31:24]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
</td>
<td >
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4 class="td_field">
COARSE[27:24]
</td>
<td >
......@@ -1992,7 +1822,7 @@ TRIG_TAG_META[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_META[23:16]
COARSE[23:16]
</td>
<td >
......@@ -2046,7 +1876,7 @@ TRIG_TAG_META[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_META[15:8]
COARSE[15:8]
</td>
<td >
......@@ -2100,7 +1930,7 @@ TRIG_TAG_META[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_META[7:0]
COARSE[7:0]
</td>
<td >
......@@ -2127,19 +1957,18 @@ TRIG_TAG_META[7:0]
</table>
<ul>
<li><b>
TRIG_TAG_META
</b>[<i>read-only</i>]: Trigger time-tag metadata
<br>Holds time-tag metadata of the last trigger event
COARSE
</b>[<i>read/write</i>]: Timetag coarse time
</ul>
<a name="TRIG_TAG_SECONDS"></a>
<h3><a name="sect_3_4">3.4. Trigger time-tag seconds register</a></h3>
<a name="TRIG_TAG_SECONDS_UPPER"></a>
<h3><a name="sect_3_4">3.4. Trigger time-tag seconds register (upper)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_trig_tag_seconds
timetag_core_trig_tag_seconds_upper
</td>
</tr>
<tr>
......@@ -2155,7 +1984,7 @@ timetag_core_trig_tag_seconds
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_TAG_SECONDS
TRIG_TAG_SECONDS_UPPER
</td>
</tr>
<tr>
......@@ -2195,29 +2024,29 @@ TRIG_TAG_SECONDS
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_SECONDS[31:24]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -2249,29 +2078,29 @@ TRIG_TAG_SECONDS[31:24]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_SECONDS[23:16]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -2303,29 +2132,29 @@ TRIG_TAG_SECONDS[23:16]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_SECONDS[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -2358,7 +2187,7 @@ TRIG_TAG_SECONDS[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_SECONDS[7:0]
TRIG_TAG_SECONDS_UPPER[7:0]
</td>
<td >
......@@ -2385,19 +2214,19 @@ TRIG_TAG_SECONDS[7:0]
</table>
<ul>
<li><b>
TRIG_TAG_SECONDS
TRIG_TAG_SECONDS_UPPER
</b>[<i>read-only</i>]: Trigger time-tag seconds
<br>Holds time-tag seconds of the last trigger event
</ul>
<a name="TRIG_TAG_COARSE"></a>
<h3><a name="sect_3_5">3.5. Trigger time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<a name="TRIG_TAG_SECONDS_LOWER"></a>
<h3><a name="sect_3_5">3.5. Trigger time-tag seconds register (lower)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_trig_tag_coarse
timetag_core_trig_tag_seconds_lower
</td>
</tr>
<tr>
......@@ -2413,7 +2242,7 @@ timetag_core_trig_tag_coarse
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_TAG_COARSE
TRIG_TAG_SECONDS_LOWER
</td>
</tr>
<tr>
......@@ -2454,7 +2283,7 @@ TRIG_TAG_COARSE
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_COARSE[31:24]
TRIG_TAG_SECONDS_LOWER[31:24]
</td>
<td >
......@@ -2508,7 +2337,7 @@ TRIG_TAG_COARSE[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_COARSE[23:16]
TRIG_TAG_SECONDS_LOWER[23:16]
</td>
<td >
......@@ -2562,7 +2391,7 @@ TRIG_TAG_COARSE[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_COARSE[15:8]
TRIG_TAG_SECONDS_LOWER[15:8]
</td>
<td >
......@@ -2616,7 +2445,7 @@ TRIG_TAG_COARSE[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_COARSE[7:0]
TRIG_TAG_SECONDS_LOWER[7:0]
</td>
<td >
......@@ -2643,19 +2472,19 @@ TRIG_TAG_COARSE[7:0]
</table>
<ul>
<li><b>
TRIG_TAG_COARSE
</b>[<i>read-only</i>]: Trigger time-tag coarse time
<br>Holds time-tag coarse time of the last trigger event
TRIG_TAG_SECONDS_LOWER
</b>[<i>read-only</i>]: Trigger time-tag seconds
<br>Holds time-tag seconds of the last trigger event
</ul>
<a name="TRIG_TAG_FINE"></a>
<h3><a name="sect_3_6">3.6. Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)</a></h3>
<a name="TRIG_TAG_COARSE"></a>
<h3><a name="sect_3_6">3.6. Trigger time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_trig_tag_fine
timetag_core_trig_tag_coarse
</td>
</tr>
<tr>
......@@ -2671,7 +2500,7 @@ timetag_core_trig_tag_fine
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_TAG_FINE
TRIG_TAG_COARSE
</td>
</tr>
<tr>
......@@ -2711,20 +2540,20 @@ TRIG_TAG_FINE
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_FINE[31:24]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td style="border: solid 1px black;" colspan=4 class="td_field">
TRIG_TAG_COARSE[27:24]
</td>
<td >
......@@ -2766,7 +2595,7 @@ TRIG_TAG_FINE[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_FINE[23:16]
TRIG_TAG_COARSE[23:16]
</td>
<td >
......@@ -2820,7 +2649,7 @@ TRIG_TAG_FINE[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_FINE[15:8]
TRIG_TAG_COARSE[15:8]
</td>
<td >
......@@ -2874,157 +2703,7 @@ TRIG_TAG_FINE[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_FINE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
TRIG_TAG_FINE
</b>[<i>read-only</i>]: Trigger time-tag fine time
<br>Holds time-tag fine time of the last trigger event
</ul>
<a name="ACQ_START_TAG_META"></a>
<h3><a name="sect_3_7">3.7. Acquisition start time-tag metadata register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_acq_start_tag_meta
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x6
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_START_TAG_META
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x18
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_META[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_META[23:16]
TRIG_TAG_COARSE[7:0]
</td>
<td >
......@@ -3049,645 +2728,21 @@ ACQ_START_TAG_META[23:16]
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_META[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_META[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_START_TAG_META
</b>[<i>read-only</i>]: Acquisition start time-tag metadata
<br>Holds time-tag metadata of the last acquisition start event
</ul>
<a name="ACQ_START_TAG_SECONDS"></a>
<h3><a name="sect_3_8">3.8. Acquisition start time-tag seconds register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_acq_start_tag_seconds
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x7
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_START_TAG_SECONDS
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x1c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_SECONDS[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_SECONDS[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_SECONDS[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_SECONDS[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_START_TAG_SECONDS
</b>[<i>read-only</i>]: Acquisition start time-tag seconds
<br>Holds time-tag seconds of the last acquisition start event
</ul>
<a name="ACQ_START_TAG_COARSE"></a>
<h3><a name="sect_3_9">3.9. Acquisition start time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_acq_start_tag_coarse
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_START_TAG_COARSE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x20
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_COARSE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_COARSE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_COARSE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_COARSE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_START_TAG_COARSE
</b>[<i>read-only</i>]: Acquisition start time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition start event
<ul>
<li><b>
TRIG_TAG_COARSE
</b>[<i>read-only</i>]: Trigger time-tag coarse time
<br>Holds time-tag coarse time of the last trigger event
</ul>
<a name="ACQ_START_TAG_FINE"></a>
<h3><a name="sect_3_10">3.10. Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)</a></h3>
<a name="ACQ_START_TAG_SECONDS_UPPER"></a>
<h3><a name="sect_3_7">3.7. Acquisition start time-tag seconds register (upper)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_acq_start_tag_fine
timetag_core_acq_start_tag_seconds_upper
</td>
</tr>
<tr>
......@@ -3695,7 +2750,7 @@ timetag_core_acq_start_tag_fine
<b>HW address: </b>
</td>
<td class="td_code">
0x9
0x6
</td>
</tr>
<tr>
......@@ -3703,7 +2758,7 @@ timetag_core_acq_start_tag_fine
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_START_TAG_FINE
ACQ_START_TAG_SECONDS_UPPER
</td>
</tr>
<tr>
......@@ -3711,7 +2766,7 @@ ACQ_START_TAG_FINE
<b>C offset: </b>
</td>
<td class="td_code">
0x24
0x18
</td>
</tr>
</table>
......@@ -3743,29 +2798,29 @@ ACQ_START_TAG_FINE
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_FINE[31:24]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -3797,29 +2852,29 @@ ACQ_START_TAG_FINE[31:24]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_FINE[23:16]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -3851,29 +2906,29 @@ ACQ_START_TAG_FINE[23:16]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_FINE[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -3906,7 +2961,7 @@ ACQ_START_TAG_FINE[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_FINE[7:0]
ACQ_START_TAG_SECONDS_UPPER[7:0]
</td>
<td >
......@@ -3933,19 +2988,19 @@ ACQ_START_TAG_FINE[7:0]
</table>
<ul>
<li><b>
ACQ_START_TAG_FINE
</b>[<i>read-only</i>]: Acquisition start time-tag fine time
<br>Holds time-tag fine time of the last acquisition start event
ACQ_START_TAG_SECONDS_UPPER
</b>[<i>read-only</i>]: Acquisition start time-tag seconds
<br>Holds time-tag seconds of the last acquisition start event
</ul>
<a name="ACQ_STOP_TAG_META"></a>
<h3><a name="sect_3_11">3.11. Acquisition stop time-tag metadata register</a></h3>
<a name="ACQ_START_TAG_SECONDS_LOWER"></a>
<h3><a name="sect_3_8">3.8. Acquisition start time-tag seconds register (lower)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_acq_stop_tag_meta
timetag_core_acq_start_tag_seconds_lower
</td>
</tr>
<tr>
......@@ -3953,7 +3008,7 @@ timetag_core_acq_stop_tag_meta
<b>HW address: </b>
</td>
<td class="td_code">
0xa
0x7
</td>
</tr>
<tr>
......@@ -3961,7 +3016,7 @@ timetag_core_acq_stop_tag_meta
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_STOP_TAG_META
ACQ_START_TAG_SECONDS_LOWER
</td>
</tr>
<tr>
......@@ -3969,7 +3024,7 @@ ACQ_STOP_TAG_META
<b>C offset: </b>
</td>
<td class="td_code">
0x28
0x1c
</td>
</tr>
</table>
......@@ -4002,7 +3057,7 @@ ACQ_STOP_TAG_META
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_META[31:24]
ACQ_START_TAG_SECONDS_LOWER[31:24]
</td>
<td >
......@@ -4056,7 +3111,7 @@ ACQ_STOP_TAG_META[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_META[23:16]
ACQ_START_TAG_SECONDS_LOWER[23:16]
</td>
<td >
......@@ -4110,7 +3165,7 @@ ACQ_STOP_TAG_META[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_META[15:8]
ACQ_START_TAG_SECONDS_LOWER[15:8]
</td>
<td >
......@@ -4164,7 +3219,7 @@ ACQ_STOP_TAG_META[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_META[7:0]
ACQ_START_TAG_SECONDS_LOWER[7:0]
</td>
<td >
......@@ -4191,19 +3246,19 @@ ACQ_STOP_TAG_META[7:0]
</table>
<ul>
<li><b>
ACQ_STOP_TAG_META
</b>[<i>read-only</i>]: Acquisition stop time-tag metadata
<br>Holds time-tag metadata of the last acquisition stop event
ACQ_START_TAG_SECONDS_LOWER
</b>[<i>read-only</i>]: Acquisition start time-tag seconds
<br>Holds time-tag seconds of the last acquisition start event
</ul>
<a name="ACQ_STOP_TAG_SECONDS"></a>
<h3><a name="sect_3_12">3.12. Acquisition stop time-tag seconds register</a></h3>
<a name="ACQ_START_TAG_COARSE"></a>
<h3><a name="sect_3_9">3.9. Acquisition start time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_acq_stop_tag_seconds
timetag_core_acq_start_tag_coarse
</td>
</tr>
<tr>
......@@ -4211,7 +3266,7 @@ timetag_core_acq_stop_tag_seconds
<b>HW address: </b>
</td>
<td class="td_code">
0xb
0x8
</td>
</tr>
<tr>
......@@ -4219,7 +3274,7 @@ timetag_core_acq_stop_tag_seconds
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_STOP_TAG_SECONDS
ACQ_START_TAG_COARSE
</td>
</tr>
<tr>
......@@ -4227,7 +3282,7 @@ ACQ_STOP_TAG_SECONDS
<b>C offset: </b>
</td>
<td class="td_code">
0x2c
0x20
</td>
</tr>
</table>
......@@ -4259,20 +3314,20 @@ ACQ_STOP_TAG_SECONDS
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_SECONDS[31:24]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td style="border: solid 1px black;" colspan=4 class="td_field">
ACQ_START_TAG_COARSE[27:24]
</td>
<td >
......@@ -4314,7 +3369,7 @@ ACQ_STOP_TAG_SECONDS[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_SECONDS[23:16]
ACQ_START_TAG_COARSE[23:16]
</td>
<td >
......@@ -4368,7 +3423,7 @@ ACQ_STOP_TAG_SECONDS[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_SECONDS[15:8]
ACQ_START_TAG_COARSE[15:8]
</td>
<td >
......@@ -4422,7 +3477,7 @@ ACQ_STOP_TAG_SECONDS[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_SECONDS[7:0]
ACQ_START_TAG_COARSE[7:0]
</td>
<td >
......@@ -4449,19 +3504,19 @@ ACQ_STOP_TAG_SECONDS[7:0]
</table>
<ul>
<li><b>
ACQ_STOP_TAG_SECONDS
</b>[<i>read-only</i>]: Acquisition stop time-tag seconds
<br>Holds time-tag seconds of the last acquisition stop event
ACQ_START_TAG_COARSE
</b>[<i>read-only</i>]: Acquisition start time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition start event
</ul>
<a name="ACQ_STOP_TAG_COARSE"></a>
<h3><a name="sect_3_13">3.13. Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<a name="ACQ_STOP_TAG_SECONDS_UPPER"></a>
<h3><a name="sect_3_10">3.10. Acquisition stop time-tag seconds register (upper)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_acq_stop_tag_coarse
timetag_core_acq_stop_tag_seconds_upper
</td>
</tr>
<tr>
......@@ -4469,7 +3524,7 @@ timetag_core_acq_stop_tag_coarse
<b>HW address: </b>
</td>
<td class="td_code">
0xc
0x9
</td>
</tr>
<tr>
......@@ -4477,7 +3532,7 @@ timetag_core_acq_stop_tag_coarse
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_STOP_TAG_COARSE
ACQ_STOP_TAG_SECONDS_UPPER
</td>
</tr>
<tr>
......@@ -4485,7 +3540,7 @@ ACQ_STOP_TAG_COARSE
<b>C offset: </b>
</td>
<td class="td_code">
0x30
0x24
</td>
</tr>
</table>
......@@ -4517,29 +3572,29 @@ ACQ_STOP_TAG_COARSE
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_COARSE[31:24]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -4571,29 +3626,29 @@ ACQ_STOP_TAG_COARSE[31:24]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_COARSE[23:16]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -4625,29 +3680,29 @@ ACQ_STOP_TAG_COARSE[23:16]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_COARSE[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -4680,7 +3735,7 @@ ACQ_STOP_TAG_COARSE[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_COARSE[7:0]
ACQ_STOP_TAG_SECONDS_UPPER[7:0]
</td>
<td >
......@@ -4707,19 +3762,19 @@ ACQ_STOP_TAG_COARSE[7:0]
</table>
<ul>
<li><b>
ACQ_STOP_TAG_COARSE
</b>[<i>read-only</i>]: Acquisition stop time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition stop event
ACQ_STOP_TAG_SECONDS_UPPER
</b>[<i>read-only</i>]: Acquisition stop time-tag seconds
<br>Holds time-tag seconds of the last acquisition stop event
</ul>
<a name="ACQ_STOP_TAG_FINE"></a>
<h3><a name="sect_3_14">3.14. Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)</a></h3>
<a name="ACQ_STOP_TAG_SECONDS_LOWER"></a>
<h3><a name="sect_3_11">3.11. Acquisition stop time-tag seconds register (lower)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_acq_stop_tag_fine
timetag_core_acq_stop_tag_seconds_lower
</td>
</tr>
<tr>
......@@ -4727,7 +3782,7 @@ timetag_core_acq_stop_tag_fine
<b>HW address: </b>
</td>
<td class="td_code">
0xd
0xa
</td>
</tr>
<tr>
......@@ -4735,7 +3790,7 @@ timetag_core_acq_stop_tag_fine
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_STOP_TAG_FINE
ACQ_STOP_TAG_SECONDS_LOWER
</td>
</tr>
<tr>
......@@ -4743,7 +3798,7 @@ ACQ_STOP_TAG_FINE
<b>C offset: </b>
</td>
<td class="td_code">
0x34
0x28
</td>
</tr>
</table>
......@@ -4776,7 +3831,7 @@ ACQ_STOP_TAG_FINE
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_FINE[31:24]
ACQ_STOP_TAG_SECONDS_LOWER[31:24]
</td>
<td >
......@@ -4830,7 +3885,7 @@ ACQ_STOP_TAG_FINE[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_FINE[23:16]
ACQ_STOP_TAG_SECONDS_LOWER[23:16]
</td>
<td >
......@@ -4884,7 +3939,7 @@ ACQ_STOP_TAG_FINE[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_FINE[15:8]
ACQ_STOP_TAG_SECONDS_LOWER[15:8]
</td>
<td >
......@@ -4938,7 +3993,7 @@ ACQ_STOP_TAG_FINE[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_FINE[7:0]
ACQ_STOP_TAG_SECONDS_LOWER[7:0]
</td>
<td >
......@@ -4965,19 +4020,19 @@ ACQ_STOP_TAG_FINE[7:0]
</table>
<ul>
<li><b>
ACQ_STOP_TAG_FINE
</b>[<i>read-only</i>]: Acquisition stop time-tag fine time
<br>Holds time-tag fine time of the last acquisition stop event
ACQ_STOP_TAG_SECONDS_LOWER
</b>[<i>read-only</i>]: Acquisition stop time-tag seconds
<br>Holds time-tag seconds of the last acquisition stop event
</ul>
<a name="ACQ_END_TAG_META"></a>
<h3><a name="sect_3_15">3.15. Acquisition end time-tag metadata register</a></h3>
<a name="ACQ_STOP_TAG_COARSE"></a>
<h3><a name="sect_3_12">3.12. Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_acq_end_tag_meta
timetag_core_acq_stop_tag_coarse
</td>
</tr>
<tr>
......@@ -4985,7 +4040,7 @@ timetag_core_acq_end_tag_meta
<b>HW address: </b>
</td>
<td class="td_code">
0xe
0xb
</td>
</tr>
<tr>
......@@ -4993,7 +4048,7 @@ timetag_core_acq_end_tag_meta
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_END_TAG_META
ACQ_STOP_TAG_COARSE
</td>
</tr>
<tr>
......@@ -5001,7 +4056,7 @@ ACQ_END_TAG_META
<b>C offset: </b>
</td>
<td class="td_code">
0x38
0x2c
</td>
</tr>
</table>
......@@ -5033,20 +4088,20 @@ ACQ_END_TAG_META
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_META[31:24]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td style="border: solid 1px black;" colspan=4 class="td_field">
ACQ_STOP_TAG_COARSE[27:24]
</td>
<td >
......@@ -5088,7 +4143,7 @@ ACQ_END_TAG_META[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_META[23:16]
ACQ_STOP_TAG_COARSE[23:16]
</td>
<td >
......@@ -5142,7 +4197,7 @@ ACQ_END_TAG_META[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_META[15:8]
ACQ_STOP_TAG_COARSE[15:8]
</td>
<td >
......@@ -5196,7 +4251,7 @@ ACQ_END_TAG_META[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_META[7:0]
ACQ_STOP_TAG_COARSE[7:0]
</td>
<td >
......@@ -5223,19 +4278,19 @@ ACQ_END_TAG_META[7:0]
</table>
<ul>
<li><b>
ACQ_END_TAG_META
</b>[<i>read-only</i>]: Acquisition end time-tag metadata
<br>Holds time-tag metadata of the last acquisition end event
ACQ_STOP_TAG_COARSE
</b>[<i>read-only</i>]: Acquisition stop time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition stop event
</ul>
<a name="ACQ_END_TAG_SECONDS"></a>
<h3><a name="sect_3_16">3.16. Acquisition end time-tag seconds register</a></h3>
<a name="ACQ_END_TAG_SECONDS_UPPER"></a>
<h3><a name="sect_3_13">3.13. Acquisition end time-tag seconds register (upper)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_acq_end_tag_seconds
timetag_core_acq_end_tag_seconds_upper
</td>
</tr>
<tr>
......@@ -5243,7 +4298,7 @@ timetag_core_acq_end_tag_seconds
<b>HW address: </b>
</td>
<td class="td_code">
0xf
0xc
</td>
</tr>
<tr>
......@@ -5251,7 +4306,7 @@ timetag_core_acq_end_tag_seconds
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_END_TAG_SECONDS
ACQ_END_TAG_SECONDS_UPPER
</td>
</tr>
<tr>
......@@ -5259,7 +4314,7 @@ ACQ_END_TAG_SECONDS
<b>C offset: </b>
</td>
<td class="td_code">
0x3c
0x30
</td>
</tr>
</table>
......@@ -5291,29 +4346,29 @@ ACQ_END_TAG_SECONDS
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_SECONDS[31:24]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -5345,29 +4400,29 @@ ACQ_END_TAG_SECONDS[31:24]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_SECONDS[23:16]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -5399,29 +4454,29 @@ ACQ_END_TAG_SECONDS[23:16]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_SECONDS[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -5454,7 +4509,7 @@ ACQ_END_TAG_SECONDS[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_SECONDS[7:0]
ACQ_END_TAG_SECONDS_UPPER[7:0]
</td>
<td >
......@@ -5481,19 +4536,19 @@ ACQ_END_TAG_SECONDS[7:0]
</table>
<ul>
<li><b>
ACQ_END_TAG_SECONDS
ACQ_END_TAG_SECONDS_UPPER
</b>[<i>read-only</i>]: Acquisition end time-tag seconds
<br>Holds time-tag seconds of the last acquisition end event
</ul>
<a name="ACQ_END_TAG_COARSE"></a>
<h3><a name="sect_3_17">3.17. Acquisition end time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<a name="ACQ_END_TAG_SECONDS_LOWER"></a>
<h3><a name="sect_3_14">3.14. Acquisition end time-tag seconds register (lower)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_acq_end_tag_coarse
timetag_core_acq_end_tag_seconds_lower
</td>
</tr>
<tr>
......@@ -5501,7 +4556,7 @@ timetag_core_acq_end_tag_coarse
<b>HW address: </b>
</td>
<td class="td_code">
0x10
0xd
</td>
</tr>
<tr>
......@@ -5509,7 +4564,7 @@ timetag_core_acq_end_tag_coarse
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_END_TAG_COARSE
ACQ_END_TAG_SECONDS_LOWER
</td>
</tr>
<tr>
......@@ -5517,7 +4572,7 @@ ACQ_END_TAG_COARSE
<b>C offset: </b>
</td>
<td class="td_code">
0x40
0x34
</td>
</tr>
</table>
......@@ -5550,7 +4605,7 @@ ACQ_END_TAG_COARSE
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_COARSE[31:24]
ACQ_END_TAG_SECONDS_LOWER[31:24]
</td>
<td >
......@@ -5604,7 +4659,7 @@ ACQ_END_TAG_COARSE[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_COARSE[23:16]
ACQ_END_TAG_SECONDS_LOWER[23:16]
</td>
<td >
......@@ -5658,7 +4713,7 @@ ACQ_END_TAG_COARSE[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_COARSE[15:8]
ACQ_END_TAG_SECONDS_LOWER[15:8]
</td>
<td >
......@@ -5712,7 +4767,7 @@ ACQ_END_TAG_COARSE[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_COARSE[7:0]
ACQ_END_TAG_SECONDS_LOWER[7:0]
</td>
<td >
......@@ -5739,19 +4794,19 @@ ACQ_END_TAG_COARSE[7:0]
</table>
<ul>
<li><b>
ACQ_END_TAG_COARSE
</b>[<i>read-only</i>]: Acquisition end time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition end event
ACQ_END_TAG_SECONDS_LOWER
</b>[<i>read-only</i>]: Acquisition end time-tag seconds
<br>Holds time-tag seconds of the last acquisition end event
</ul>
<a name="ACQ_END_TAG_FINE"></a>
<h3><a name="sect_3_18">3.18. Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility)</a></h3>
<a name="ACQ_END_TAG_COARSE"></a>
<h3><a name="sect_3_15">3.15. Acquisition end time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_acq_end_tag_fine
timetag_core_acq_end_tag_coarse
</td>
</tr>
<tr>
......@@ -5759,7 +4814,7 @@ timetag_core_acq_end_tag_fine
<b>HW address: </b>
</td>
<td class="td_code">
0x11
0xe
</td>
</tr>
<tr>
......@@ -5767,7 +4822,7 @@ timetag_core_acq_end_tag_fine
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_END_TAG_FINE
ACQ_END_TAG_COARSE
</td>
</tr>
<tr>
......@@ -5775,7 +4830,7 @@ ACQ_END_TAG_FINE
<b>C offset: </b>
</td>
<td class="td_code">
0x44
0x38
</td>
</tr>
</table>
......@@ -5807,20 +4862,20 @@ ACQ_END_TAG_FINE
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_FINE[31:24]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td style="border: solid 1px black;" colspan=4 class="td_field">
ACQ_END_TAG_COARSE[27:24]
</td>
<td >
......@@ -5862,7 +4917,7 @@ ACQ_END_TAG_FINE[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_FINE[23:16]
ACQ_END_TAG_COARSE[23:16]
</td>
<td >
......@@ -5916,7 +4971,7 @@ ACQ_END_TAG_FINE[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_FINE[15:8]
ACQ_END_TAG_COARSE[15:8]
</td>
<td >
......@@ -5970,7 +5025,7 @@ ACQ_END_TAG_FINE[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_FINE[7:0]
ACQ_END_TAG_COARSE[7:0]
</td>
<td >
......@@ -5997,9 +5052,9 @@ ACQ_END_TAG_FINE[7:0]
</table>
<ul>
<li><b>
ACQ_END_TAG_FINE
</b>[<i>read-only</i>]: Acquisition end time-tag fine time
<br>Holds time-tag fine time of the last acquisition end event
ACQ_END_TAG_COARSE
</b>[<i>read-only</i>]: Acquisition end time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition end event
</ul>
......
hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.wb
View file @ 14262933
......@@ -6,9 +6,24 @@ peripheral {
prefix = "timetag_core";
reg {
name = "Timetag seconds register";
description = "Seconds counter. Incremented everytime the coarse counter overflows.";
prefix = "seconds";
name = "Timetag seconds register (upper)";
description = "8 upper bits of seconds counter. Incremented everytime the coarse counter overflows.";
prefix = "seconds_upper";
field {
name = "Timetag seconds";
type = SLV;
load = LOAD_EXT;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Timetag seconds register (lower)";
description = "32 lower bits of seconds counter. Incremented everytime the coarse counter overflows.";
prefix = "seconds_lower";
field {
name = "Timetag seconds";
......@@ -29,29 +44,29 @@ peripheral {
name = "Timetag coarse time";
type = SLV;
load = LOAD_EXT;
size = 32;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Trigger time-tag metadata register";
prefix = "trig_tag_meta";
name = "Trigger time-tag seconds register (upper)";
prefix = "trig_tag_seconds_upper";
field {
name = "Trigger time-tag metadata";
description = "Holds time-tag metadata of the last trigger event";
name = "Trigger time-tag seconds";
description = "Holds time-tag seconds of the last trigger event";
type = SLV;
size = 32;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger time-tag seconds register";
prefix = "trig_tag_seconds";
reg {
name = "Trigger time-tag seconds register (lower)";
prefix = "trig_tag_seconds_lower";
field {
name = "Trigger time-tag seconds";
......@@ -71,43 +86,29 @@ peripheral {
name = "Trigger time-tag coarse time";
description = "Holds time-tag coarse time of the last trigger event";
type = SLV;
size = 32;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)";
prefix = "trig_tag_fine";
name = "Acquisition start time-tag seconds register (upper)";
prefix = "acq_start_tag_seconds_upper";
field {
name = "Trigger time-tag fine time";
description = "Holds time-tag fine time of the last trigger event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag metadata register";
prefix = "acq_start_tag_meta";
field {
name = "Acquisition start time-tag metadata";
description = "Holds time-tag metadata of the last acquisition start event";
name = "Acquisition start time-tag seconds";
description = "Holds time-tag seconds of the last acquisition start event";
type = SLV;
size = 32;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag seconds register";
prefix = "acq_start_tag_seconds";
reg {
name = "Acquisition start time-tag seconds register (lower)";
prefix = "acq_start_tag_seconds_lower";
field {
name = "Acquisition start time-tag seconds";
......@@ -127,43 +128,29 @@ peripheral {
name = "Acquisition start time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition start event";
type = SLV;
size = 32;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)";
prefix = "acq_start_tag_fine";
name = "Acquisition stop time-tag seconds register (upper)";
prefix = "acq_stop_tag_seconds_upper";
field {
name = "Acquisition start time-tag fine time";
description = "Holds time-tag fine time of the last acquisition start event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag metadata register";
prefix = "acq_stop_tag_meta";
field {
name = "Acquisition stop time-tag metadata";
description = "Holds time-tag metadata of the last acquisition stop event";
name = "Acquisition stop time-tag seconds";
description = "Holds time-tag seconds of the last acquisition stop event";
type = SLV;
size = 32;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag seconds register";
prefix = "acq_stop_tag_seconds";
name = "Acquisition stop time-tag seconds register (lower)";
prefix = "acq_stop_tag_seconds_lower";
field {
name = "Acquisition stop time-tag seconds";
......@@ -183,43 +170,29 @@ peripheral {
name = "Acquisition stop time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition stop event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)";
prefix = "acq_stop_tag_fine";
field {
name = "Acquisition stop time-tag fine time";
description = "Holds time-tag fine time of the last acquisition stop event";
type = SLV;
size = 32;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag metadata register";
prefix = "acq_end_tag_meta";
name = "Acquisition end time-tag seconds register (upper)";
prefix = "acq_end_tag_seconds_upper";
field {
name = "Acquisition end time-tag metadata";
description = "Holds time-tag metadata of the last acquisition end event";
name = "Acquisition end time-tag seconds";
description = "Holds time-tag seconds of the last acquisition end event";
type = SLV;
size = 32;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag seconds register";
prefix = "acq_end_tag_seconds";
name = "Acquisition end time-tag seconds register (lower)";
prefix = "acq_end_tag_seconds_lower";
field {
name = "Acquisition end time-tag seconds";
......@@ -239,21 +212,7 @@ peripheral {
name = "Acquisition end time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition end event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility)";
prefix = "acq_end_tag_fine";
field {
name = "Acquisition end time-tag fine time";
description = "Holds time-tag fine time of the last acquisition end event";
type = SLV;
size = 32;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......
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