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FMC ADC 100M 14b 4cha - Gateware
Commit 23fbb478 authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Remove "reserved" fields in fmc-adc core csr. 

It was creating a big multiplexer in the wishbone crossbar and violating timing constrains.
Those reserved fields are replaced by "don't care" -> better optimised during synthesis.
parent af30d2cb
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documentation/manuals/gateware/fmc_adc_100Ms_csr.tex
View file @ 23fbb478
......@@ -172,11 +172,6 @@ Manual TRIG LED
@code{ACQ_LED}
@tab @code{0} @tab
Manual ACQ LED
@item @code{31...8}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
......@@ -184,7 +179,6 @@ Reserved
@item @code{test_data_en} @tab Write the address counter value instead of ADC data to DDR
@item @code{trig_led} @tab Manual control of the front panel TRIG LED
@item @code{acq_led} @tab Manual control of the front panel ACQ LED
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{sta} - Status register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -209,11 +203,6 @@ SerDes synchronization status
@code{ACQ_CFG}
@tab @code{X} @tab
Acquisition configuration status
@item @code{31...6}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
......@@ -221,7 +210,6 @@ Reserved
@item @code{serdes_pll} @tab Sampling clock recovery PLL.@*0: not locked@*1: locked
@item @code{serdes_synced} @tab 0: bitslip in progress@*1: serdes synchronized
@item @code{acq_cfg} @tab 0: Unauthorised acquisition configuration (will prevent acquisition to start)@*1: Valid acquisition configuration@*@bullet{} Shot number > 0@*@bullet{} Post-trigger sample > 0
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{trig_cfg} - Trigger configuration
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -315,16 +303,10 @@ Software trigger (ignore on read)
@code{NB}
@tab @code{0} @tab
Number of shots
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{nb} @tab Number of shots required in multi-shot mode, set to one for single-shot mode.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{shots_cnt} - Remaining shots counter
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -334,16 +316,10 @@ Reserved
@code{VAL}
@tab @code{X} @tab
Remaining shots counter
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Counts the number of remaining shots to acquire.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{trig_pos} - Trigger address register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -431,16 +407,10 @@ Samples counter
@code{SSR}
@tab @code{0} @tab
Solid state relays control for channel 1
@item @code{31...7}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ssr} @tab Controls input voltage range, termination and DC offset error calibration@*0x23: 100mV range@*0x11: 1V range@*0x45: 10V range@*0x00: Open input@*0x42: 100mV range calibration@*0x40: 1V range calibration@*0x44: 10V range calibration@*Bit3 is indepandant of the others and enables the 50ohms termination.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch1_sta} - Channel 1 status register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -450,16 +420,10 @@ Reserved
@code{VAL}
@tab @code{X} @tab
Channel 1 current ADC value
@item @code{31...16}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Current ADC raw value. The format is binary two's complement.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch1_gain} - Channel 1 gain calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -469,16 +433,10 @@ Reserved
@code{VAL}
@tab @code{0} @tab
Gain calibration for channel 1
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Gain applied to all data coming from the ADC.@*Fixed point format:@*Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch1_offset} - Channel 1 offset calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -488,16 +446,10 @@ Reserved
@code{VAL}
@tab @code{0} @tab
Offset calibration for channel 1
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch1_sat} - Channel 1 saturation register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -507,16 +459,10 @@ Reserved
@code{VAL}
@tab @code{0} @tab
Saturation value for channel 1
@item @code{31...15}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch2_ctl} - Channel 2 control register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -526,16 +472,10 @@ Reserved
@code{SSR}
@tab @code{0} @tab
Solid state relays control for channel 2
@item @code{31...7}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ssr} @tab Controls input voltage range, termination and DC offset error calibration@*0x23: 100mV range@*0x11: 1V range@*0x45: 10V range@*0x00: Open input@*0x42: 100mV range calibration@*0x40: 1V range calibration@*0x44: 10V range calibration@*Bit3 is indepandant of the others and enables the 50ohms termination.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch2_sta} - Channel 2 status register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -545,16 +485,10 @@ Reserved
@code{VAL}
@tab @code{X} @tab
Channel 2 current ACD value
@item @code{31...16}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Current ADC raw value. The format is binary two's complement.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch2_gain} - Channel 2 gain calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -564,16 +498,10 @@ Reserved
@code{VAL}
@tab @code{0} @tab
Gain calibration for channel 2
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Gain applied to all data coming from the ADC.@*Fixed point format:@*Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch2_offset} - Channel 2 offset calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -583,16 +511,10 @@ Reserved
@code{VAL}
@tab @code{0} @tab
Offset calibration for channel 2
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch2_sat} - Channel 2 saturation register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -602,16 +524,10 @@ Reserved
@code{VAL}
@tab @code{0} @tab
Saturation value for channel 2
@item @code{31...15}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch3_ctl} - Channel 3 control register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -621,16 +537,10 @@ Reserved
@code{SSR}
@tab @code{0} @tab
Solid state relays control for channel 3
@item @code{31...7}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ssr} @tab Controls input voltage range, termination and DC offset error calibration@*0x23: 100mV range@*0x11: 1V range@*0x45: 10V range@*0x00: Open input@*0x42: 100mV range calibration@*0x40: 1V range calibration@*0x44: 10V range calibration@*Bit3 is indepandant of the others and enables the 50ohms termination.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch3_sta} - Channel 3 status register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -640,16 +550,10 @@ Reserved
@code{VAL}
@tab @code{X} @tab
Channel 3 current ADC value
@item @code{31...16}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Current ADC raw value. The format is binary two's complement.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch3_gain} - Channel 3 gain calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -659,16 +563,10 @@ Reserved
@code{VAL}
@tab @code{0} @tab
Gain calibration for channel 3
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Gain applied to all data coming from the ADC.@*Fixed point format:@*Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch3_offset} - Channel 3 offset calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -678,16 +576,10 @@ Reserved
@code{VAL}
@tab @code{0} @tab
Offset calibration for channel 3
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch3_sat} - Channel 3 saturation register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -697,16 +589,10 @@ Reserved
@code{VAL}
@tab @code{0} @tab
Saturation value for channel 3
@item @code{31...15}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch4_ctl} - Channel 4 control register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -716,16 +602,10 @@ Reserved
@code{SSR}
@tab @code{0} @tab
Solid state relays control for channel 4
@item @code{31...7}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ssr} @tab Controls input voltage range, termination and DC offset error calibration@*0x23: 100mV range@*0x11: 1V range@*0x45: 10V range@*0x00: Open input@*0x42: 100mV range calibration@*0x40: 1V range calibration@*0x44: 10V range calibration@*Bit3 is indepandant of the others and enables the 50ohms termination.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch4_sta} - Channel 4 status register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -735,16 +615,10 @@ Reserved
@code{VAL}
@tab @code{X} @tab
Channel 4 current ADC value
@item @code{31...16}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Current ADC raw value. The format is binary two's complement.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch4_gain} - Channel 4 gain calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -754,16 +628,10 @@ Reserved
@code{VAL}
@tab @code{0} @tab
Gain calibration for channel 4
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Gain applied to all data coming from the ADC.@*Fixed point format:@*Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch4_offset} - Channel 4 offset calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -773,16 +641,10 @@ Reserved
@code{VAL}
@tab @code{0} @tab
Offset calibration for channel 4
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{ch4_sat} - Channel 4 saturation register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -792,14 +654,8 @@ Reserved
@code{VAL}
@tab @code{0} @tab
Saturation value for channel 4
@item @code{31...15}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ 23fbb478
......@@ -168,12 +168,10 @@ architecture rtl of fmc_adc_100Ms_core is
fmc_adc_core_ctl_test_data_en_o : out std_logic;
fmc_adc_core_ctl_trig_led_o : out std_logic;
fmc_adc_core_ctl_acq_led_o : out std_logic;
fmc_adc_core_ctl_reserved_o : out std_logic_vector(23 downto 0);
fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0);
fmc_adc_core_sta_serdes_pll_i : in std_logic;
fmc_adc_core_sta_serdes_synced_i : in std_logic;
fmc_adc_core_sta_acq_cfg_i : in std_logic;
fmc_adc_core_sta_reserved_i : in std_logic_vector(25 downto 0);
fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic;
fmc_adc_core_trig_cfg_hw_trig_pol_o : out std_logic;
fmc_adc_core_trig_cfg_hw_trig_en_o : out std_logic;
......@@ -187,9 +185,7 @@ architecture rtl of fmc_adc_100Ms_core is
fmc_adc_core_sw_trig_o : out std_logic_vector(31 downto 0);
fmc_adc_core_sw_trig_wr_o : out std_logic;
fmc_adc_core_shots_nb_o : out std_logic_vector(15 downto 0);
fmc_adc_core_shots_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_shots_cnt_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_shots_cnt_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0);
fmc_adc_core_fs_freq_i : in std_logic_vector(31 downto 0);
fmc_adc_core_sr_deci_o : out std_logic_vector(31 downto 0);
......@@ -197,45 +193,25 @@ architecture rtl of fmc_adc_100Ms_core is
fmc_adc_core_post_samples_o : out std_logic_vector(31 downto 0);
fmc_adc_core_samples_cnt_i : in std_logic_vector(31 downto 0);
fmc_adc_core_ch1_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch1_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch1_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch1_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch1_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_offset_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_sat_val_o : out std_logic_vector(14 downto 0);
fmc_adc_core_ch1_sat_reserved_o : out std_logic_vector(16 downto 0);
fmc_adc_core_ch2_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch2_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch2_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch2_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch2_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_offset_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_sat_val_o : out std_logic_vector(14 downto 0);
fmc_adc_core_ch2_sat_reserved_o : out std_logic_vector(16 downto 0);
fmc_adc_core_ch3_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch3_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch3_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch3_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch3_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_offset_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_sat_val_o : out std_logic_vector(14 downto 0);
fmc_adc_core_ch3_sat_reserved_o : out std_logic_vector(16 downto 0);
fmc_adc_core_ch4_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch4_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch4_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch4_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch4_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_offset_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_sat_val_o : out std_logic_vector(14 downto 0);
fmc_adc_core_ch4_sat_reserved_o : out std_logic_vector(16 downto 0)
fmc_adc_core_ch4_sat_val_o : out std_logic_vector(14 downto 0)
);
end component fmc_adc_100Ms_csr;
......@@ -770,12 +746,10 @@ begin
fmc_adc_core_ctl_test_data_en_o => test_data_en,
fmc_adc_core_ctl_trig_led_o => trig_led_man,
fmc_adc_core_ctl_acq_led_o => acq_led_man,
fmc_adc_core_ctl_reserved_o => open,
fmc_adc_core_sta_fsm_i => acq_fsm_state,
fmc_adc_core_sta_serdes_pll_i => locked_out,
fmc_adc_core_sta_serdes_synced_i => serdes_synced,
fmc_adc_core_sta_acq_cfg_i => acq_config_ok,
fmc_adc_core_sta_reserved_i => (others => '0'),
fmc_adc_core_trig_cfg_hw_trig_sel_o => hw_trig_sel,
fmc_adc_core_trig_cfg_hw_trig_pol_o => hw_trig_pol,
fmc_adc_core_trig_cfg_hw_trig_en_o => hw_trig_en,
......@@ -789,9 +763,7 @@ begin
fmc_adc_core_sw_trig_o => open,
fmc_adc_core_sw_trig_wr_o => sw_trig_t,
fmc_adc_core_shots_nb_o => shots_value,
fmc_adc_core_shots_reserved_o => open,
fmc_adc_core_shots_cnt_val_i => remaining_shots,
fmc_adc_core_shots_cnt_reserved_o => open,
fmc_adc_core_trig_pos_i => trig_addr,
fmc_adc_core_fs_freq_i => fs_freq,
fmc_adc_core_sr_deci_o => decim_factor,
......@@ -799,45 +771,25 @@ begin
fmc_adc_core_post_samples_o => post_trig_value,
fmc_adc_core_samples_cnt_i => std_logic_vector(samples_cnt),
fmc_adc_core_ch1_ctl_ssr_o => gpio_ssr_ch1_o,
fmc_adc_core_ch1_ctl_reserved_o => open,
fmc_adc_core_ch1_sta_val_i => serdes_out_data(15 downto 0),
fmc_adc_core_ch1_sta_reserved_i => (others => '0'),
fmc_adc_core_ch1_gain_val_o => gain_calibr(15 downto 0),
fmc_adc_core_ch1_gain_reserved_o => open,
fmc_adc_core_ch1_offset_val_o => offset_calibr(15 downto 0),
fmc_adc_core_ch1_offset_reserved_o => open,
fmc_adc_core_ch1_sat_val_o => sat_val(14 downto 0),
fmc_adc_core_ch1_sat_reserved_o => open,
fmc_adc_core_ch2_ctl_ssr_o => gpio_ssr_ch2_o,
fmc_adc_core_ch2_ctl_reserved_o => open,
fmc_adc_core_ch2_sta_val_i => serdes_out_data(31 downto 16),
fmc_adc_core_ch2_sta_reserved_i => (others => '0'),
fmc_adc_core_ch2_gain_val_o => gain_calibr(31 downto 16),
fmc_adc_core_ch2_gain_reserved_o => open,
fmc_adc_core_ch2_offset_val_o => offset_calibr(31 downto 16),
fmc_adc_core_ch2_offset_reserved_o => open,
fmc_adc_core_ch2_sat_val_o => sat_val(29 downto 15),
fmc_adc_core_ch2_sat_reserved_o => open,
fmc_adc_core_ch3_ctl_ssr_o => gpio_ssr_ch3_o,
fmc_adc_core_ch3_ctl_reserved_o => open,
fmc_adc_core_ch3_sta_val_i => serdes_out_data(47 downto 32),
fmc_adc_core_ch3_sta_reserved_i => (others => '0'),
fmc_adc_core_ch3_gain_val_o => gain_calibr(47 downto 32),
fmc_adc_core_ch3_gain_reserved_o => open,
fmc_adc_core_ch3_offset_val_o => offset_calibr(47 downto 32),
fmc_adc_core_ch3_offset_reserved_o => open,
fmc_adc_core_ch3_sat_val_o => sat_val(44 downto 30),
fmc_adc_core_ch3_sat_reserved_o => open,
fmc_adc_core_ch4_ctl_ssr_o => gpio_ssr_ch4_o,
fmc_adc_core_ch4_ctl_reserved_o => open,
fmc_adc_core_ch4_sta_val_i => serdes_out_data(63 downto 48),
fmc_adc_core_ch4_sta_reserved_i => (others => '0'),
fmc_adc_core_ch4_gain_val_o => gain_calibr(63 downto 48),
fmc_adc_core_ch4_gain_reserved_o => open,
fmc_adc_core_ch4_offset_val_o => offset_calibr(63 downto 48),
fmc_adc_core_ch4_offset_reserved_o => open,
fmc_adc_core_ch4_sat_val_o => sat_val(59 downto 45),
fmc_adc_core_ch4_sat_reserved_o => open
fmc_adc_core_ch4_sat_val_o => sat_val(59 downto 45)
);
------------------------------------------------------------------------------
......
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @ 23fbb478
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Thu Mar 20 11:08:14 2014
-- Created : Fri Mar 21 08:14:07 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -43,8 +43,6 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_ctl_trig_led_o : out std_logic;
-- Port for BIT field: 'Manual ACQ LED' in reg: 'Control register'
fmc_adc_core_ctl_acq_led_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control register'
fmc_adc_core_ctl_reserved_o : out std_logic_vector(23 downto 0);
-- Port for std_logic_vector field: 'State machine status' in reg: 'Status register'
fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0);
-- Port for BIT field: 'SerDes PLL status' in reg: 'Status register'
......@@ -53,8 +51,6 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_sta_serdes_synced_i : in std_logic;
-- Port for BIT field: 'Acquisition configuration status' in reg: 'Status register'
fmc_adc_core_sta_acq_cfg_i : in std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status register'
fmc_adc_core_sta_reserved_i : in std_logic_vector(25 downto 0);
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger selection' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger polarity' in reg: 'Trigger configuration'
......@@ -80,12 +76,8 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_sw_trig_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Number of shots' in reg: 'Number of shots'
fmc_adc_core_shots_nb_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Number of shots'
fmc_adc_core_shots_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Remaining shots counter' in reg: 'Remaining shots counter'
fmc_adc_core_shots_cnt_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Remaining shots counter'
fmc_adc_core_shots_cnt_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Trigger address' in reg: 'Trigger address register'
fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Sampling clock frequency' in reg: 'Sampling clock frequency'
......@@ -100,84 +92,44 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_samples_cnt_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 1' in reg: 'Channel 1 control register'
fmc_adc_core_ch1_ctl_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 1 control register'
fmc_adc_core_ch1_ctl_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 1 current ADC value' in reg: 'Channel 1 status register'
fmc_adc_core_ch1_sta_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 1 status register'
fmc_adc_core_ch1_sta_reserved_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Gain calibration for channel 1' in reg: 'Channel 1 gain calibration register'
fmc_adc_core_ch1_gain_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 1 gain calibration register'
fmc_adc_core_ch1_gain_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Offset calibration for channel 1' in reg: 'Channel 1 offset calibration register'
fmc_adc_core_ch1_offset_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 1 offset calibration register'
fmc_adc_core_ch1_offset_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Saturation value for channel 1' in reg: 'Channel 1 saturation register'
fmc_adc_core_ch1_sat_val_o : out std_logic_vector(14 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 1 saturation register'
fmc_adc_core_ch1_sat_reserved_o : out std_logic_vector(16 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 2' in reg: 'Channel 2 control register'
fmc_adc_core_ch2_ctl_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 2 control register'
fmc_adc_core_ch2_ctl_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 2 current ACD value' in reg: 'Channel 2 status register'
fmc_adc_core_ch2_sta_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 2 status register'
fmc_adc_core_ch2_sta_reserved_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Gain calibration for channel 2' in reg: 'Channel 2 gain calibration register'
fmc_adc_core_ch2_gain_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 2 gain calibration register'
fmc_adc_core_ch2_gain_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Offset calibration for channel 2' in reg: 'Channel 2 offset calibration register'
fmc_adc_core_ch2_offset_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 2 offset calibration register'
fmc_adc_core_ch2_offset_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Saturation value for channel 2' in reg: 'Channel 2 saturation register'
fmc_adc_core_ch2_sat_val_o : out std_logic_vector(14 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 2 saturation register'
fmc_adc_core_ch2_sat_reserved_o : out std_logic_vector(16 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 3' in reg: 'Channel 3 control register'
fmc_adc_core_ch3_ctl_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 3 control register'
fmc_adc_core_ch3_ctl_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 3 current ADC value' in reg: 'Channel 3 status register'
fmc_adc_core_ch3_sta_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 3 status register'
fmc_adc_core_ch3_sta_reserved_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Gain calibration for channel 3' in reg: 'Channel 3 gain calibration register'
fmc_adc_core_ch3_gain_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 3 gain calibration register'
fmc_adc_core_ch3_gain_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Offset calibration for channel 3' in reg: 'Channel 3 offset calibration register'
fmc_adc_core_ch3_offset_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 3 offset calibration register'
fmc_adc_core_ch3_offset_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Saturation value for channel 3' in reg: 'Channel 3 saturation register'
fmc_adc_core_ch3_sat_val_o : out std_logic_vector(14 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 3 saturation register'
fmc_adc_core_ch3_sat_reserved_o : out std_logic_vector(16 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 4' in reg: 'Channel 4 control register'
fmc_adc_core_ch4_ctl_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 4 control register'
fmc_adc_core_ch4_ctl_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 4 current ADC value' in reg: 'Channel 4 status register'
fmc_adc_core_ch4_sta_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 4 status register'
fmc_adc_core_ch4_sta_reserved_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Gain calibration for channel 4' in reg: 'Channel 4 gain calibration register'
fmc_adc_core_ch4_gain_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 4 gain calibration register'
fmc_adc_core_ch4_gain_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Offset calibration for channel 4' in reg: 'Channel 4 offset calibration register'
fmc_adc_core_ch4_offset_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 4 offset calibration register'
fmc_adc_core_ch4_offset_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Saturation value for channel 4' in reg: 'Channel 4 saturation register'
fmc_adc_core_ch4_sat_val_o : out std_logic_vector(14 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 4 saturation register'
fmc_adc_core_ch4_sat_reserved_o : out std_logic_vector(16 downto 0)
fmc_adc_core_ch4_sat_val_o : out std_logic_vector(14 downto 0)
);
end fmc_adc_100Ms_csr;
......@@ -193,7 +145,6 @@ signal fmc_adc_core_ctl_man_bitslip_sync2 : std_logic ;
signal fmc_adc_core_ctl_test_data_en_int : std_logic ;
signal fmc_adc_core_ctl_trig_led_int : std_logic ;
signal fmc_adc_core_ctl_acq_led_int : std_logic ;
signal fmc_adc_core_ctl_reserved_int : std_logic_vector(23 downto 0);
signal fmc_adc_core_trig_cfg_hw_trig_sel_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync1 : std_logic ;
......@@ -235,8 +186,6 @@ signal fmc_adc_core_sw_trig_wr_sync0 : std_logic ;
signal fmc_adc_core_sw_trig_wr_sync1 : std_logic ;
signal fmc_adc_core_sw_trig_wr_sync2 : std_logic ;
signal fmc_adc_core_shots_nb_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_shots_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_shots_cnt_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_fs_freq_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_fs_freq_lwb : std_logic ;
signal fmc_adc_core_fs_freq_lwb_delay : std_logic ;
......@@ -253,7 +202,6 @@ signal fmc_adc_core_sr_deci_swb_s2 : std_logic ;
signal fmc_adc_core_pre_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_post_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_ch1_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch1_ctl_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch1_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_sta_val_lwb : std_logic ;
signal fmc_adc_core_ch1_sta_val_lwb_delay : std_logic ;
......@@ -262,13 +210,9 @@ signal fmc_adc_core_ch1_sta_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch1_sta_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch1_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch1_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_gain_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_offset_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_core_ch1_sat_reserved_int : std_logic_vector(16 downto 0);
signal fmc_adc_core_ch2_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch2_ctl_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch2_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_sta_val_lwb : std_logic ;
signal fmc_adc_core_ch2_sta_val_lwb_delay : std_logic ;
......@@ -277,13 +221,9 @@ signal fmc_adc_core_ch2_sta_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch2_sta_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch2_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch2_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_gain_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_offset_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_core_ch2_sat_reserved_int : std_logic_vector(16 downto 0);
signal fmc_adc_core_ch3_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch3_ctl_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch3_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_sta_val_lwb : std_logic ;
signal fmc_adc_core_ch3_sta_val_lwb_delay : std_logic ;
......@@ -292,13 +232,9 @@ signal fmc_adc_core_ch3_sta_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch3_sta_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch3_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch3_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_gain_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_offset_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_core_ch3_sat_reserved_int : std_logic_vector(16 downto 0);
signal fmc_adc_core_ch4_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch4_ctl_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch4_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_sta_val_lwb : std_logic ;
signal fmc_adc_core_ch4_sta_val_lwb_delay : std_logic ;
......@@ -307,11 +243,8 @@ signal fmc_adc_core_ch4_sta_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch4_sta_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch4_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch4_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_gain_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_offset_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_core_ch4_sat_reserved_int : std_logic_vector(16 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -347,7 +280,6 @@ begin
fmc_adc_core_ctl_test_data_en_int <= '0';
fmc_adc_core_ctl_trig_led_int <= '0';
fmc_adc_core_ctl_acq_led_int <= '0';
fmc_adc_core_ctl_reserved_int <= "000000000000000000000000";
fmc_adc_core_trig_cfg_hw_trig_sel_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_pol_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_en_int <= '0';
......@@ -367,8 +299,6 @@ begin
fmc_adc_core_sw_trig_wr_int <= '0';
fmc_adc_core_sw_trig_wr_int_delay <= '0';
fmc_adc_core_shots_nb_int <= "0000000000000000";
fmc_adc_core_shots_reserved_int <= "0000000000000000";
fmc_adc_core_shots_cnt_reserved_int <= "0000000000000000";
fmc_adc_core_fs_freq_lwb <= '0';
fmc_adc_core_fs_freq_lwb_delay <= '0';
fmc_adc_core_fs_freq_lwb_in_progress <= '0';
......@@ -378,49 +308,33 @@ begin
fmc_adc_core_pre_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_post_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_ch1_ctl_ssr_int <= "0000000";
fmc_adc_core_ch1_ctl_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch1_sta_val_lwb <= '0';
fmc_adc_core_ch1_sta_val_lwb_delay <= '0';
fmc_adc_core_ch1_sta_val_lwb_in_progress <= '0';
fmc_adc_core_ch1_gain_val_int <= "0000000000000000";
fmc_adc_core_ch1_gain_reserved_int <= "0000000000000000";
fmc_adc_core_ch1_offset_val_int <= "0000000000000000";
fmc_adc_core_ch1_offset_reserved_int <= "0000000000000000";
fmc_adc_core_ch1_sat_val_int <= "000000000000000";
fmc_adc_core_ch1_sat_reserved_int <= "00000000000000000";
fmc_adc_core_ch2_ctl_ssr_int <= "0000000";
fmc_adc_core_ch2_ctl_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch2_sta_val_lwb <= '0';
fmc_adc_core_ch2_sta_val_lwb_delay <= '0';
fmc_adc_core_ch2_sta_val_lwb_in_progress <= '0';
fmc_adc_core_ch2_gain_val_int <= "0000000000000000";
fmc_adc_core_ch2_gain_reserved_int <= "0000000000000000";
fmc_adc_core_ch2_offset_val_int <= "0000000000000000";
fmc_adc_core_ch2_offset_reserved_int <= "0000000000000000";
fmc_adc_core_ch2_sat_val_int <= "000000000000000";
fmc_adc_core_ch2_sat_reserved_int <= "00000000000000000";
fmc_adc_core_ch3_ctl_ssr_int <= "0000000";
fmc_adc_core_ch3_ctl_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch3_sta_val_lwb <= '0';
fmc_adc_core_ch3_sta_val_lwb_delay <= '0';
fmc_adc_core_ch3_sta_val_lwb_in_progress <= '0';
fmc_adc_core_ch3_gain_val_int <= "0000000000000000";
fmc_adc_core_ch3_gain_reserved_int <= "0000000000000000";
fmc_adc_core_ch3_offset_val_int <= "0000000000000000";
fmc_adc_core_ch3_offset_reserved_int <= "0000000000000000";
fmc_adc_core_ch3_sat_val_int <= "000000000000000";
fmc_adc_core_ch3_sat_reserved_int <= "00000000000000000";
fmc_adc_core_ch4_ctl_ssr_int <= "0000000";
fmc_adc_core_ch4_ctl_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch4_sta_val_lwb <= '0';
fmc_adc_core_ch4_sta_val_lwb_delay <= '0';
fmc_adc_core_ch4_sta_val_lwb_in_progress <= '0';
fmc_adc_core_ch4_gain_val_int <= "0000000000000000";
fmc_adc_core_ch4_gain_reserved_int <= "0000000000000000";
fmc_adc_core_ch4_offset_val_int <= "0000000000000000";
fmc_adc_core_ch4_offset_reserved_int <= "0000000000000000";
fmc_adc_core_ch4_sat_val_int <= "000000000000000";
fmc_adc_core_ch4_sat_reserved_int <= "00000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -487,7 +401,6 @@ begin
fmc_adc_core_ctl_test_data_en_int <= wrdata_reg(5);
fmc_adc_core_ctl_trig_led_int <= wrdata_reg(6);
fmc_adc_core_ctl_acq_led_int <= wrdata_reg(7);
fmc_adc_core_ctl_reserved_int <= wrdata_reg(31 downto 8);
end if;
rddata_reg(2) <= fmc_adc_core_ctl_fmc_clk_oe_int;
rddata_reg(3) <= fmc_adc_core_ctl_offset_dac_clr_n_int;
......@@ -495,9 +408,32 @@ begin
rddata_reg(5) <= fmc_adc_core_ctl_test_data_en_int;
rddata_reg(6) <= fmc_adc_core_ctl_trig_led_int;
rddata_reg(7) <= fmc_adc_core_ctl_acq_led_int;
rddata_reg(31 downto 8) <= fmc_adc_core_ctl_reserved_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "000001" =>
......@@ -507,7 +443,32 @@ begin
rddata_reg(3) <= fmc_adc_core_sta_serdes_pll_i;
rddata_reg(4) <= fmc_adc_core_sta_serdes_synced_i;
rddata_reg(5) <= fmc_adc_core_sta_acq_cfg_i;
rddata_reg(31 downto 6) <= fmc_adc_core_sta_reserved_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000010" =>
......@@ -588,18 +549,46 @@ begin
when "000101" =>
if (wb_we_i = '1') then
fmc_adc_core_shots_nb_int <= wrdata_reg(15 downto 0);
fmc_adc_core_shots_reserved_int <= wrdata_reg(31 downto 16);
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_shots_nb_int;
rddata_reg(31 downto 16) <= fmc_adc_core_shots_reserved_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000110" =>
if (wb_we_i = '1') then
fmc_adc_core_shots_cnt_reserved_int <= wrdata_reg(31 downto 16);
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_shots_cnt_val_i;
rddata_reg(31 downto 16) <= fmc_adc_core_shots_cnt_reserved_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000111" =>
......@@ -650,10 +639,33 @@ begin
when "001101" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch1_ctl_reserved_int <= wrdata_reg(31 downto 7);
end if;
rddata_reg(6 downto 0) <= fmc_adc_core_ch1_ctl_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch1_ctl_reserved_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001110" =>
......@@ -664,43 +676,124 @@ begin
fmc_adc_core_ch1_sta_val_lwb_delay <= '1';
fmc_adc_core_ch1_sta_val_lwb_in_progress <= '1';
end if;
rddata_reg(31 downto 16) <= fmc_adc_core_ch1_sta_reserved_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "001111" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch1_gain_reserved_int <= wrdata_reg(31 downto 16);
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch1_gain_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch1_gain_reserved_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010000" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_offset_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch1_offset_reserved_int <= wrdata_reg(31 downto 16);
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch1_offset_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch1_offset_reserved_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010001" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_sat_val_int <= wrdata_reg(14 downto 0);
fmc_adc_core_ch1_sat_reserved_int <= wrdata_reg(31 downto 15);
end if;
rddata_reg(14 downto 0) <= fmc_adc_core_ch1_sat_val_int;
rddata_reg(31 downto 15) <= fmc_adc_core_ch1_sat_reserved_int;
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010010" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch2_ctl_reserved_int <= wrdata_reg(31 downto 7);
end if;
rddata_reg(6 downto 0) <= fmc_adc_core_ch2_ctl_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch2_ctl_reserved_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010011" =>
......@@ -711,43 +804,124 @@ begin
fmc_adc_core_ch2_sta_val_lwb_delay <= '1';
fmc_adc_core_ch2_sta_val_lwb_in_progress <= '1';
end if;
rddata_reg(31 downto 16) <= fmc_adc_core_ch2_sta_reserved_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "010100" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch2_gain_reserved_int <= wrdata_reg(31 downto 16);
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch2_gain_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch2_gain_reserved_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010101" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_offset_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch2_offset_reserved_int <= wrdata_reg(31 downto 16);
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch2_offset_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch2_offset_reserved_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010110" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_sat_val_int <= wrdata_reg(14 downto 0);
fmc_adc_core_ch2_sat_reserved_int <= wrdata_reg(31 downto 15);
end if;
rddata_reg(14 downto 0) <= fmc_adc_core_ch2_sat_val_int;
rddata_reg(31 downto 15) <= fmc_adc_core_ch2_sat_reserved_int;
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010111" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch3_ctl_reserved_int <= wrdata_reg(31 downto 7);
end if;
rddata_reg(6 downto 0) <= fmc_adc_core_ch3_ctl_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch3_ctl_reserved_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011000" =>
......@@ -758,43 +932,124 @@ begin
fmc_adc_core_ch3_sta_val_lwb_delay <= '1';
fmc_adc_core_ch3_sta_val_lwb_in_progress <= '1';
end if;
rddata_reg(31 downto 16) <= fmc_adc_core_ch3_sta_reserved_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "011001" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch3_gain_reserved_int <= wrdata_reg(31 downto 16);
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch3_gain_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch3_gain_reserved_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011010" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_offset_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch3_offset_reserved_int <= wrdata_reg(31 downto 16);
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch3_offset_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch3_offset_reserved_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011011" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_sat_val_int <= wrdata_reg(14 downto 0);
fmc_adc_core_ch3_sat_reserved_int <= wrdata_reg(31 downto 15);
end if;
rddata_reg(14 downto 0) <= fmc_adc_core_ch3_sat_val_int;
rddata_reg(31 downto 15) <= fmc_adc_core_ch3_sat_reserved_int;
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011100" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch4_ctl_reserved_int <= wrdata_reg(31 downto 7);
end if;
rddata_reg(6 downto 0) <= fmc_adc_core_ch4_ctl_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch4_ctl_reserved_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011101" =>
......@@ -805,34 +1060,92 @@ begin
fmc_adc_core_ch4_sta_val_lwb_delay <= '1';
fmc_adc_core_ch4_sta_val_lwb_in_progress <= '1';
end if;
rddata_reg(31 downto 16) <= fmc_adc_core_ch4_sta_reserved_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "011110" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch4_gain_reserved_int <= wrdata_reg(31 downto 16);
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch4_gain_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch4_gain_reserved_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011111" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_offset_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch4_offset_reserved_int <= wrdata_reg(31 downto 16);
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch4_offset_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch4_offset_reserved_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100000" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_sat_val_int <= wrdata_reg(14 downto 0);
fmc_adc_core_ch4_sat_reserved_int <= wrdata_reg(31 downto 15);
end if;
rddata_reg(14 downto 0) <= fmc_adc_core_ch4_sat_val_int;
rddata_reg(31 downto 15) <= fmc_adc_core_ch4_sat_reserved_int;
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
......@@ -878,13 +1191,10 @@ begin
fmc_adc_core_ctl_trig_led_o <= fmc_adc_core_ctl_trig_led_int;
-- Manual ACQ LED
fmc_adc_core_ctl_acq_led_o <= fmc_adc_core_ctl_acq_led_int;
-- Reserved
fmc_adc_core_ctl_reserved_o <= fmc_adc_core_ctl_reserved_int;
-- State machine status
-- SerDes PLL status
-- SerDes synchronization status
-- Acquisition configuration status
-- Reserved
-- Hardware trigger selection
-- synchronizer chain for field : Hardware trigger selection (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
......@@ -1049,11 +1359,7 @@ begin
-- Number of shots
fmc_adc_core_shots_nb_o <= fmc_adc_core_shots_nb_int;
-- Reserved
fmc_adc_core_shots_reserved_o <= fmc_adc_core_shots_reserved_int;
-- Remaining shots counter
-- Reserved
fmc_adc_core_shots_cnt_reserved_o <= fmc_adc_core_shots_cnt_reserved_int;
-- Trigger address
-- Sampling clock frequency
-- asynchronous std_logic_vector register : Sampling clock frequency (type RO/WO, fs_clk_i <-> clk_sys_i)
......@@ -1102,8 +1408,6 @@ begin
-- Samples counter
-- Solid state relays control for channel 1
fmc_adc_core_ch1_ctl_ssr_o <= fmc_adc_core_ch1_ctl_ssr_int;
-- Reserved
fmc_adc_core_ch1_ctl_reserved_o <= fmc_adc_core_ch1_ctl_reserved_int;
-- Channel 1 current ADC value
-- asynchronous std_logic_vector register : Channel 1 current ADC value (type RO/WO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
......@@ -1124,23 +1428,14 @@ begin
end process;
-- Reserved
-- Gain calibration for channel 1
fmc_adc_core_ch1_gain_val_o <= fmc_adc_core_ch1_gain_val_int;
-- Reserved
fmc_adc_core_ch1_gain_reserved_o <= fmc_adc_core_ch1_gain_reserved_int;
-- Offset calibration for channel 1
fmc_adc_core_ch1_offset_val_o <= fmc_adc_core_ch1_offset_val_int;
-- Reserved
fmc_adc_core_ch1_offset_reserved_o <= fmc_adc_core_ch1_offset_reserved_int;
-- Saturation value for channel 1
fmc_adc_core_ch1_sat_val_o <= fmc_adc_core_ch1_sat_val_int;
-- Reserved
fmc_adc_core_ch1_sat_reserved_o <= fmc_adc_core_ch1_sat_reserved_int;
-- Solid state relays control for channel 2
fmc_adc_core_ch2_ctl_ssr_o <= fmc_adc_core_ch2_ctl_ssr_int;
-- Reserved
fmc_adc_core_ch2_ctl_reserved_o <= fmc_adc_core_ch2_ctl_reserved_int;
-- Channel 2 current ACD value
-- asynchronous std_logic_vector register : Channel 2 current ACD value (type RO/WO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
......@@ -1161,23 +1456,14 @@ begin
end process;
-- Reserved
-- Gain calibration for channel 2
fmc_adc_core_ch2_gain_val_o <= fmc_adc_core_ch2_gain_val_int;
-- Reserved
fmc_adc_core_ch2_gain_reserved_o <= fmc_adc_core_ch2_gain_reserved_int;
-- Offset calibration for channel 2
fmc_adc_core_ch2_offset_val_o <= fmc_adc_core_ch2_offset_val_int;
-- Reserved
fmc_adc_core_ch2_offset_reserved_o <= fmc_adc_core_ch2_offset_reserved_int;
-- Saturation value for channel 2
fmc_adc_core_ch2_sat_val_o <= fmc_adc_core_ch2_sat_val_int;
-- Reserved
fmc_adc_core_ch2_sat_reserved_o <= fmc_adc_core_ch2_sat_reserved_int;
-- Solid state relays control for channel 3
fmc_adc_core_ch3_ctl_ssr_o <= fmc_adc_core_ch3_ctl_ssr_int;
-- Reserved
fmc_adc_core_ch3_ctl_reserved_o <= fmc_adc_core_ch3_ctl_reserved_int;
-- Channel 3 current ADC value
-- asynchronous std_logic_vector register : Channel 3 current ADC value (type RO/WO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
......@@ -1198,23 +1484,14 @@ begin
end process;
-- Reserved
-- Gain calibration for channel 3
fmc_adc_core_ch3_gain_val_o <= fmc_adc_core_ch3_gain_val_int;
-- Reserved
fmc_adc_core_ch3_gain_reserved_o <= fmc_adc_core_ch3_gain_reserved_int;
-- Offset calibration for channel 3
fmc_adc_core_ch3_offset_val_o <= fmc_adc_core_ch3_offset_val_int;
-- Reserved
fmc_adc_core_ch3_offset_reserved_o <= fmc_adc_core_ch3_offset_reserved_int;
-- Saturation value for channel 3
fmc_adc_core_ch3_sat_val_o <= fmc_adc_core_ch3_sat_val_int;
-- Reserved
fmc_adc_core_ch3_sat_reserved_o <= fmc_adc_core_ch3_sat_reserved_int;
-- Solid state relays control for channel 4
fmc_adc_core_ch4_ctl_ssr_o <= fmc_adc_core_ch4_ctl_ssr_int;
-- Reserved
fmc_adc_core_ch4_ctl_reserved_o <= fmc_adc_core_ch4_ctl_reserved_int;
-- Channel 4 current ADC value
-- asynchronous std_logic_vector register : Channel 4 current ADC value (type RO/WO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
......@@ -1235,19 +1512,12 @@ begin
end process;
-- Reserved
-- Gain calibration for channel 4
fmc_adc_core_ch4_gain_val_o <= fmc_adc_core_ch4_gain_val_int;
-- Reserved
fmc_adc_core_ch4_gain_reserved_o <= fmc_adc_core_ch4_gain_reserved_int;
-- Offset calibration for channel 4
fmc_adc_core_ch4_offset_val_o <= fmc_adc_core_ch4_offset_val_int;
-- Reserved
fmc_adc_core_ch4_offset_reserved_o <= fmc_adc_core_ch4_offset_reserved_int;
-- Saturation value for channel 4
fmc_adc_core_ch4_sat_val_o <= fmc_adc_core_ch4_sat_val_int;
-- Reserved
fmc_adc_core_ch4_sat_reserved_o <= fmc_adc_core_ch4_sat_reserved_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @ 23fbb478
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Thu Mar 20 11:08:15 2014
* Created : Fri Mar 21 08:14:07 2014
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -57,12 +57,6 @@
/* definitions for field: Manual ACQ LED in reg: Control register */
#define FMC_ADC_CORE_CTL_ACQ_LED WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Reserved in reg: Control register */
#define FMC_ADC_CORE_CTL_RESERVED_MASK WBGEN2_GEN_MASK(8, 24)
#define FMC_ADC_CORE_CTL_RESERVED_SHIFT 8
#define FMC_ADC_CORE_CTL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 8, 24)
#define FMC_ADC_CORE_CTL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 8, 24)
/* definitions for register: Status register */
/* definitions for field: State machine status in reg: Status register */
......@@ -80,12 +74,6 @@
/* definitions for field: Acquisition configuration status in reg: Status register */
#define FMC_ADC_CORE_STA_ACQ_CFG WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Reserved in reg: Status register */
#define FMC_ADC_CORE_STA_RESERVED_MASK WBGEN2_GEN_MASK(6, 26)
#define FMC_ADC_CORE_STA_RESERVED_SHIFT 6
#define FMC_ADC_CORE_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 6, 26)
#define FMC_ADC_CORE_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 6, 26)
/* definitions for register: Trigger configuration */
/* definitions for field: Hardware trigger selection in reg: Trigger configuration */
......@@ -136,12 +124,6 @@
#define FMC_ADC_CORE_SHOTS_NB_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_SHOTS_NB_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Number of shots */
#define FMC_ADC_CORE_SHOTS_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_SHOTS_RESERVED_SHIFT 16
#define FMC_ADC_CORE_SHOTS_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_SHOTS_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Remaining shots counter */
/* definitions for field: Remaining shots counter in reg: Remaining shots counter */
......@@ -150,12 +132,6 @@
#define FMC_ADC_CORE_SHOTS_CNT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_SHOTS_CNT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Remaining shots counter */
#define FMC_ADC_CORE_SHOTS_CNT_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_SHOTS_CNT_RESERVED_SHIFT 16
#define FMC_ADC_CORE_SHOTS_CNT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_SHOTS_CNT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Trigger address register */
/* definitions for register: Sampling clock frequency */
......@@ -182,12 +158,6 @@
#define FMC_ADC_CORE_CH1_CTL_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH1_CTL_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Channel 1 control register */
#define FMC_ADC_CORE_CH1_CTL_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH1_CTL_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH1_CTL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH1_CTL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 1 status register */
/* definitions for field: Channel 1 current ADC value in reg: Channel 1 status register */
......@@ -196,12 +166,6 @@
#define FMC_ADC_CORE_CH1_STA_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH1_STA_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 1 status register */
#define FMC_ADC_CORE_CH1_STA_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH1_STA_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH1_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH1_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 1 gain calibration register */
/* definitions for field: Gain calibration for channel 1 in reg: Channel 1 gain calibration register */
......@@ -210,12 +174,6 @@
#define FMC_ADC_CORE_CH1_GAIN_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH1_GAIN_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 1 gain calibration register */
#define FMC_ADC_CORE_CH1_GAIN_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH1_GAIN_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH1_GAIN_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH1_GAIN_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 1 offset calibration register */
/* definitions for field: Offset calibration for channel 1 in reg: Channel 1 offset calibration register */
......@@ -224,12 +182,6 @@
#define FMC_ADC_CORE_CH1_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH1_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 1 offset calibration register */
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 1 saturation register */
/* definitions for field: Saturation value for channel 1 in reg: Channel 1 saturation register */
......@@ -238,12 +190,6 @@
#define FMC_ADC_CORE_CH1_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_CORE_CH1_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for field: Reserved in reg: Channel 1 saturation register */
#define FMC_ADC_CORE_CH1_SAT_RESERVED_MASK WBGEN2_GEN_MASK(15, 17)
#define FMC_ADC_CORE_CH1_SAT_RESERVED_SHIFT 15
#define FMC_ADC_CORE_CH1_SAT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 15, 17)
#define FMC_ADC_CORE_CH1_SAT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 15, 17)
/* definitions for register: Channel 2 control register */
/* definitions for field: Solid state relays control for channel 2 in reg: Channel 2 control register */
......@@ -252,12 +198,6 @@
#define FMC_ADC_CORE_CH2_CTL_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH2_CTL_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Channel 2 control register */
#define FMC_ADC_CORE_CH2_CTL_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH2_CTL_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH2_CTL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH2_CTL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 2 status register */
/* definitions for field: Channel 2 current ACD value in reg: Channel 2 status register */
......@@ -266,12 +206,6 @@
#define FMC_ADC_CORE_CH2_STA_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH2_STA_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 2 status register */
#define FMC_ADC_CORE_CH2_STA_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH2_STA_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH2_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH2_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 2 gain calibration register */
/* definitions for field: Gain calibration for channel 2 in reg: Channel 2 gain calibration register */
......@@ -280,12 +214,6 @@
#define FMC_ADC_CORE_CH2_GAIN_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH2_GAIN_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 2 gain calibration register */
#define FMC_ADC_CORE_CH2_GAIN_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH2_GAIN_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH2_GAIN_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH2_GAIN_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 2 offset calibration register */
/* definitions for field: Offset calibration for channel 2 in reg: Channel 2 offset calibration register */
......@@ -294,12 +222,6 @@
#define FMC_ADC_CORE_CH2_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH2_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 2 offset calibration register */
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 2 saturation register */
/* definitions for field: Saturation value for channel 2 in reg: Channel 2 saturation register */
......@@ -308,12 +230,6 @@
#define FMC_ADC_CORE_CH2_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_CORE_CH2_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for field: Reserved in reg: Channel 2 saturation register */
#define FMC_ADC_CORE_CH2_SAT_RESERVED_MASK WBGEN2_GEN_MASK(15, 17)
#define FMC_ADC_CORE_CH2_SAT_RESERVED_SHIFT 15
#define FMC_ADC_CORE_CH2_SAT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 15, 17)
#define FMC_ADC_CORE_CH2_SAT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 15, 17)
/* definitions for register: Channel 3 control register */
/* definitions for field: Solid state relays control for channel 3 in reg: Channel 3 control register */
......@@ -322,12 +238,6 @@
#define FMC_ADC_CORE_CH3_CTL_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH3_CTL_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Channel 3 control register */
#define FMC_ADC_CORE_CH3_CTL_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH3_CTL_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH3_CTL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH3_CTL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 3 status register */
/* definitions for field: Channel 3 current ADC value in reg: Channel 3 status register */
......@@ -336,12 +246,6 @@
#define FMC_ADC_CORE_CH3_STA_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH3_STA_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 3 status register */
#define FMC_ADC_CORE_CH3_STA_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH3_STA_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH3_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH3_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 3 gain calibration register */
/* definitions for field: Gain calibration for channel 3 in reg: Channel 3 gain calibration register */
......@@ -350,12 +254,6 @@
#define FMC_ADC_CORE_CH3_GAIN_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH3_GAIN_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 3 gain calibration register */
#define FMC_ADC_CORE_CH3_GAIN_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH3_GAIN_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH3_GAIN_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH3_GAIN_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 3 offset calibration register */
/* definitions for field: Offset calibration for channel 3 in reg: Channel 3 offset calibration register */
......@@ -364,12 +262,6 @@
#define FMC_ADC_CORE_CH3_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH3_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 3 offset calibration register */
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 3 saturation register */
/* definitions for field: Saturation value for channel 3 in reg: Channel 3 saturation register */
......@@ -378,12 +270,6 @@
#define FMC_ADC_CORE_CH3_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_CORE_CH3_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for field: Reserved in reg: Channel 3 saturation register */
#define FMC_ADC_CORE_CH3_SAT_RESERVED_MASK WBGEN2_GEN_MASK(15, 17)
#define FMC_ADC_CORE_CH3_SAT_RESERVED_SHIFT 15
#define FMC_ADC_CORE_CH3_SAT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 15, 17)
#define FMC_ADC_CORE_CH3_SAT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 15, 17)
/* definitions for register: Channel 4 control register */
/* definitions for field: Solid state relays control for channel 4 in reg: Channel 4 control register */
......@@ -392,12 +278,6 @@
#define FMC_ADC_CORE_CH4_CTL_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH4_CTL_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Channel 4 control register */
#define FMC_ADC_CORE_CH4_CTL_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH4_CTL_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH4_CTL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH4_CTL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 4 status register */
/* definitions for field: Channel 4 current ADC value in reg: Channel 4 status register */
......@@ -406,12 +286,6 @@
#define FMC_ADC_CORE_CH4_STA_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH4_STA_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 4 status register */
#define FMC_ADC_CORE_CH4_STA_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH4_STA_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH4_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH4_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 4 gain calibration register */
/* definitions for field: Gain calibration for channel 4 in reg: Channel 4 gain calibration register */
......@@ -420,12 +294,6 @@
#define FMC_ADC_CORE_CH4_GAIN_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH4_GAIN_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 4 gain calibration register */
#define FMC_ADC_CORE_CH4_GAIN_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH4_GAIN_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH4_GAIN_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH4_GAIN_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 4 offset calibration register */
/* definitions for field: Offset calibration for channel 4 in reg: Channel 4 offset calibration register */
......@@ -434,12 +302,6 @@
#define FMC_ADC_CORE_CH4_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH4_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 4 offset calibration register */
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 4 saturation register */
/* definitions for field: Saturation value for channel 4 in reg: Channel 4 saturation register */
......@@ -448,12 +310,6 @@
#define FMC_ADC_CORE_CH4_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_CORE_CH4_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for field: Reserved in reg: Channel 4 saturation register */
#define FMC_ADC_CORE_CH4_SAT_RESERVED_MASK WBGEN2_GEN_MASK(15, 17)
#define FMC_ADC_CORE_CH4_SAT_RESERVED_SHIFT 15
#define FMC_ADC_CORE_CH4_SAT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 15, 17)
#define FMC_ADC_CORE_CH4_SAT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 15, 17)
PACKED struct FMC_ADC_CORE_WB {
/* [0x0]: REG Control register */
uint32_t CTL;
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
View file @ 23fbb478
......@@ -812,23 +812,6 @@ fmc_adc_core_ctl_acq_led_o
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ctl_reserved_o[23:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
......@@ -840,10 +823,10 @@ wb_stall_o
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
......@@ -929,23 +912,6 @@ fmc_adc_core_sta_acq_cfg_i
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_sta_reserved_i[25:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1303,23 +1269,6 @@ fmc_adc_core_shots_nb_o[15:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_shots_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1371,23 +1320,6 @@ fmc_adc_core_shots_cnt_val_i[15:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_shots_cnt_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1745,23 +1677,6 @@ fmc_adc_core_ch1_ctl_ssr_o[6:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_ctl_reserved_o[24:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1815,13 +1730,13 @@ fmc_adc_core_ch1_sta_val_i[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_sta_reserved_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
......@@ -1832,10 +1747,10 @@ fmc_adc_core_ch1_sta_reserved_i[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
<b>Channel 1 gain calibration register:</b>
</td>
<td class="td_arrow_right">
......@@ -1852,10 +1767,10 @@ fmc_adc_core_ch1_sta_reserved_i[15:0]
</td>
<td class="td_pblock_right">
<b>Channel 1 gain calibration register:</b>
fmc_adc_core_ch1_gain_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -1866,13 +1781,13 @@ fmc_adc_core_ch1_sta_reserved_i[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_gain_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -1886,10 +1801,10 @@ fmc_adc_core_ch1_gain_val_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_gain_reserved_o[15:0]
<b>Channel 1 offset calibration register:</b>
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -1900,13 +1815,13 @@ fmc_adc_core_ch1_gain_reserved_o[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_offset_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -1917,10 +1832,10 @@ fmc_adc_core_ch1_gain_reserved_o[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
<b>Channel 1 offset calibration register:</b>
</td>
<td class="td_arrow_right">
......@@ -1937,10 +1852,10 @@ fmc_adc_core_ch1_gain_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_offset_val_o[15:0]
<b>Channel 1 saturation register:</b>
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -1954,7 +1869,7 @@ fmc_adc_core_ch1_offset_val_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_offset_reserved_o[15:0]
fmc_adc_core_ch1_sat_val_o[14:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1988,7 +1903,7 @@ fmc_adc_core_ch1_offset_reserved_o[15:0]
</td>
<td class="td_pblock_right">
<b>Channel 1 saturation register:</b>
<b>Channel 2 control register:</b>
</td>
<td class="td_arrow_right">
......@@ -2005,7 +1920,7 @@ fmc_adc_core_ch1_offset_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_sat_val_o[14:0]
fmc_adc_core_ch2_ctl_ssr_o[6:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2019,13 +1934,13 @@ fmc_adc_core_ch1_sat_val_o[14:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_sat_reserved_o[16:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -2036,10 +1951,10 @@ fmc_adc_core_ch1_sat_reserved_o[16:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
<b>Channel 2 status register:</b>
</td>
<td class="td_arrow_right">
......@@ -2056,10 +1971,10 @@ fmc_adc_core_ch1_sat_reserved_o[16:0]
</td>
<td class="td_pblock_right">
<b>Channel 2 control register:</b>
fmc_adc_core_ch2_sta_val_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
......@@ -2070,13 +1985,13 @@ fmc_adc_core_ch1_sat_reserved_o[16:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_ctl_ssr_o[6:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -2090,10 +2005,10 @@ fmc_adc_core_ch2_ctl_ssr_o[6:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_ctl_reserved_o[24:0]
<b>Channel 2 gain calibration register:</b>
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -2104,13 +2019,13 @@ fmc_adc_core_ch2_ctl_reserved_o[24:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_gain_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -2121,10 +2036,10 @@ fmc_adc_core_ch2_ctl_reserved_o[24:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
<b>Channel 2 status register:</b>
</td>
<td class="td_arrow_right">
......@@ -2141,10 +2056,10 @@ fmc_adc_core_ch2_ctl_reserved_o[24:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_sta_val_i[15:0]
<b>Channel 2 offset calibration register:</b>
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
......@@ -2158,10 +2073,10 @@ fmc_adc_core_ch2_sta_val_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_sta_reserved_i[15:0]
fmc_adc_core_ch2_offset_val_o[15:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
<tr>
......@@ -2192,7 +2107,7 @@ fmc_adc_core_ch2_sta_reserved_i[15:0]
</td>
<td class="td_pblock_right">
<b>Channel 2 gain calibration register:</b>
<b>Channel 2 saturation register:</b>
</td>
<td class="td_arrow_right">
......@@ -2209,7 +2124,7 @@ fmc_adc_core_ch2_sta_reserved_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_gain_val_o[15:0]
fmc_adc_core_ch2_sat_val_o[14:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2223,13 +2138,13 @@ fmc_adc_core_ch2_gain_val_o[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_gain_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -2240,10 +2155,10 @@ fmc_adc_core_ch2_gain_reserved_o[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
<b>Channel 3 control register:</b>
</td>
<td class="td_arrow_right">
......@@ -2260,10 +2175,10 @@ fmc_adc_core_ch2_gain_reserved_o[15:0]
</td>
<td class="td_pblock_right">
<b>Channel 2 offset calibration register:</b>
fmc_adc_core_ch3_ctl_ssr_o[6:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -2274,13 +2189,13 @@ fmc_adc_core_ch2_gain_reserved_o[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_offset_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -2294,10 +2209,10 @@ fmc_adc_core_ch2_offset_val_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_offset_reserved_o[15:0]
<b>Channel 3 status register:</b>
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -2308,13 +2223,13 @@ fmc_adc_core_ch2_offset_reserved_o[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_sta_val_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
......@@ -2325,10 +2240,10 @@ fmc_adc_core_ch2_offset_reserved_o[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
<b>Channel 2 saturation register:</b>
</td>
<td class="td_arrow_right">
......@@ -2345,10 +2260,10 @@ fmc_adc_core_ch2_offset_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_sat_val_o[14:0]
<b>Channel 3 gain calibration register:</b>
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -2362,7 +2277,7 @@ fmc_adc_core_ch2_sat_val_o[14:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_sat_reserved_o[16:0]
fmc_adc_core_ch3_gain_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2396,7 +2311,7 @@ fmc_adc_core_ch2_sat_reserved_o[16:0]
</td>
<td class="td_pblock_right">
<b>Channel 3 control register:</b>
<b>Channel 3 offset calibration register:</b>
</td>
<td class="td_arrow_right">
......@@ -2413,7 +2328,7 @@ fmc_adc_core_ch2_sat_reserved_o[16:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_ctl_ssr_o[6:0]
fmc_adc_core_ch3_offset_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2427,13 +2342,13 @@ fmc_adc_core_ch3_ctl_ssr_o[6:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_ctl_reserved_o[24:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -2444,10 +2359,10 @@ fmc_adc_core_ch3_ctl_reserved_o[24:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
<b>Channel 3 saturation register:</b>
</td>
<td class="td_arrow_right">
......@@ -2464,10 +2379,10 @@ fmc_adc_core_ch3_ctl_reserved_o[24:0]
</td>
<td class="td_pblock_right">
<b>Channel 3 status register:</b>
fmc_adc_core_ch3_sat_val_o[14:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -2478,13 +2393,13 @@ fmc_adc_core_ch3_ctl_reserved_o[24:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_sta_val_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
......@@ -2498,10 +2413,10 @@ fmc_adc_core_ch3_sta_val_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_sta_reserved_i[15:0]
<b>Channel 4 control register:</b>
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
......@@ -2512,13 +2427,13 @@ fmc_adc_core_ch3_sta_reserved_i[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_ctl_ssr_o[6:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -2529,10 +2444,10 @@ fmc_adc_core_ch3_sta_reserved_i[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
<b>Channel 3 gain calibration register:</b>
</td>
<td class="td_arrow_right">
......@@ -2549,10 +2464,10 @@ fmc_adc_core_ch3_sta_reserved_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_gain_val_o[15:0]
<b>Channel 4 status register:</b>
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -2566,10 +2481,10 @@ fmc_adc_core_ch3_gain_val_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_gain_reserved_o[15:0]
fmc_adc_core_ch4_sta_val_i[15:0]
</td>
<td class="td_arrow_right">
&rArr;
&lArr;
</td>
</tr>
<tr>
......@@ -2600,7 +2515,7 @@ fmc_adc_core_ch3_gain_reserved_o[15:0]
</td>
<td class="td_pblock_right">
<b>Channel 3 offset calibration register:</b>
<b>Channel 4 gain calibration register:</b>
</td>
<td class="td_arrow_right">
......@@ -2617,7 +2532,7 @@ fmc_adc_core_ch3_gain_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_offset_val_o[15:0]
fmc_adc_core_ch4_gain_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2631,299 +2546,10 @@ fmc_adc_core_ch3_offset_val_o[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_offset_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 3 saturation register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_sat_val_o[14:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_sat_reserved_o[16:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 4 control register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_ctl_ssr_o[6:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_ctl_reserved_o[24:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 4 status register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_sta_val_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_sta_reserved_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 4 gain calibration register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_gain_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_gain_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
......@@ -2969,23 +2595,6 @@ fmc_adc_core_ch4_offset_val_o[15:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_offset_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -3031,23 +2640,6 @@ fmc_adc_core_ch4_sat_val_o[14:0]
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_sat_reserved_o[16:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
......@@ -3115,29 +2707,29 @@ CTL
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[23:16]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -3169,29 +2761,29 @@ RESERVED[23:16]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -3223,29 +2815,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -3329,10 +2921,6 @@ TRIG_LED
ACQ_LED
</b>[<i>read/write</i>]: Manual ACQ LED
<br>Manual control of the front panel ACQ LED
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="STA"></a>
<h3><a name="sect_3_2">3.2. Status register</a></h3>
......@@ -3398,29 +2986,29 @@ STA
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[25:18]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -3452,29 +3040,29 @@ RESERVED[25:18]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[17:10]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -3506,29 +3094,29 @@ RESERVED[17:10]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[9:2]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -3560,8 +3148,11 @@ RESERVED[9:2]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=2 class="td_field">
RESERVED[1:0]
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ACQ_CFG
......@@ -3580,9 +3171,6 @@ FSM[2:0]
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
......@@ -3603,10 +3191,6 @@ SERDES_SYNCED
ACQ_CFG
</b>[<i>read-only</i>]: Acquisition configuration status
<br>0: Unauthorised acquisition configuration (will prevent acquisition to start)<br>1: Valid acquisition configuration<br>- Shot number > 0<br>- Post-trigger sample > 0
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="TRIG_CFG"></a>
<h3><a name="sect_3_3">3.3. Trigger configuration</a></h3>
......@@ -4480,29 +4064,29 @@ SHOTS
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -4534,29 +4118,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -4673,10 +4257,6 @@ NB[7:0]
NB
</b>[<i>read/write</i>]: Number of shots
<br>Number of shots required in multi-shot mode, set to one for single-shot mode.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="SHOTS_CNT"></a>
<h3><a name="sect_3_7">3.7. Remaining shots counter</a></h3>
......@@ -4742,29 +4322,29 @@ SHOTS_CNT
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -4796,29 +4376,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -4935,10 +4515,6 @@ VAL[7:0]
VAL
</b>[<i>read-only</i>]: Remaining shots counter
<br>Counts the number of remaining shots to acquire.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="TRIG_POS"></a>
<h3><a name="sect_3_8">3.8. Trigger address register</a></h3>
......@@ -6552,29 +6128,29 @@ CH1_CTL
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[24:17]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -6606,29 +6182,29 @@ RESERVED[24:17]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -6660,29 +6236,29 @@ RESERVED[16:9]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -6714,8 +6290,8 @@ RESERVED[8:1]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
......@@ -6745,10 +6321,6 @@ SSR[6:0]
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 1
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH1_STA"></a>
<h3><a name="sect_3_15">3.15. Channel 1 status register</a></h3>
......@@ -6814,29 +6386,29 @@ CH1_STA
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -6868,29 +6440,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -7007,10 +6579,6 @@ VAL[7:0]
VAL
</b>[<i>read-only</i>]: Channel 1 current ADC value
<br>Current ADC raw value. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH1_GAIN"></a>
<h3><a name="sect_3_16">3.16. Channel 1 gain calibration register</a></h3>
......@@ -7076,29 +6644,29 @@ CH1_GAIN
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -7130,29 +6698,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -7269,10 +6837,6 @@ VAL[7:0]
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 1
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH1_OFFSET"></a>
<h3><a name="sect_3_17">3.17. Channel 1 offset calibration register</a></h3>
......@@ -7338,29 +6902,29 @@ CH1_OFFSET
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -7392,29 +6956,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -7531,10 +7095,6 @@ VAL[7:0]
VAL
</b>[<i>read/write</i>]: Offset calibration for channel 1
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH1_SAT"></a>
<h3><a name="sect_3_18">3.18. Channel 1 saturation register</a></h3>
......@@ -7600,29 +7160,29 @@ CH1_SAT
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -7654,29 +7214,29 @@ RESERVED[16:9]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -7708,8 +7268,8 @@ RESERVED[8:1]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
VAL[14:8]
......@@ -7793,10 +7353,6 @@ VAL[7:0]
VAL
</b>[<i>read/write</i>]: Saturation value for channel 1
<br>Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH2_CTL"></a>
<h3><a name="sect_3_19">3.19. Channel 2 control register</a></h3>
......@@ -7862,29 +7418,29 @@ CH2_CTL
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[24:17]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -7916,29 +7472,29 @@ RESERVED[24:17]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -7970,29 +7526,29 @@ RESERVED[16:9]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -8024,8 +7580,8 @@ RESERVED[8:1]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
......@@ -8053,12 +7609,8 @@ SSR[6:0]
<ul>
<li><b>
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 2
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</b>[<i>read/write</i>]: Solid state relays control for channel 2
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
</ul>
<a name="CH2_STA"></a>
<h3><a name="sect_3_20">3.20. Channel 2 status register</a></h3>
......@@ -8124,29 +7676,29 @@ CH2_STA
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -8178,29 +7730,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -8317,10 +7869,6 @@ VAL[7:0]
VAL
</b>[<i>read-only</i>]: Channel 2 current ACD value
<br>Current ADC raw value. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH2_GAIN"></a>
<h3><a name="sect_3_21">3.21. Channel 2 gain calibration register</a></h3>
......@@ -8386,29 +7934,29 @@ CH2_GAIN
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -8440,29 +7988,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -8579,10 +8127,6 @@ VAL[7:0]
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 2
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH2_OFFSET"></a>
<h3><a name="sect_3_22">3.22. Channel 2 offset calibration register</a></h3>
......@@ -8648,29 +8192,29 @@ CH2_OFFSET
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -8702,29 +8246,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -8841,10 +8385,6 @@ VAL[7:0]
VAL
</b>[<i>read/write</i>]: Offset calibration for channel 2
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH2_SAT"></a>
<h3><a name="sect_3_23">3.23. Channel 2 saturation register</a></h3>
......@@ -8910,29 +8450,29 @@ CH2_SAT
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -8964,29 +8504,29 @@ RESERVED[16:9]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -9018,8 +8558,8 @@ RESERVED[8:1]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
VAL[14:8]
......@@ -9103,10 +8643,6 @@ VAL[7:0]
VAL
</b>[<i>read/write</i>]: Saturation value for channel 2
<br>Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH3_CTL"></a>
<h3><a name="sect_3_24">3.24. Channel 3 control register</a></h3>
......@@ -9172,29 +8708,29 @@ CH3_CTL
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[24:17]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -9226,29 +8762,29 @@ RESERVED[24:17]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -9280,29 +8816,29 @@ RESERVED[16:9]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -9334,8 +8870,8 @@ RESERVED[8:1]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
......@@ -9365,10 +8901,6 @@ SSR[6:0]
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 3
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH3_STA"></a>
<h3><a name="sect_3_25">3.25. Channel 3 status register</a></h3>
......@@ -9434,29 +8966,29 @@ CH3_STA
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -9488,29 +9020,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -9627,10 +9159,6 @@ VAL[7:0]
VAL
</b>[<i>read-only</i>]: Channel 3 current ADC value
<br>Current ADC raw value. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH3_GAIN"></a>
<h3><a name="sect_3_26">3.26. Channel 3 gain calibration register</a></h3>
......@@ -9696,29 +9224,29 @@ CH3_GAIN
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -9750,29 +9278,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -9888,11 +9416,7 @@ VAL[7:0]
<li><b>
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 3
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
</ul>
<a name="CH3_OFFSET"></a>
<h3><a name="sect_3_27">3.27. Channel 3 offset calibration register</a></h3>
......@@ -9958,29 +9482,29 @@ CH3_OFFSET
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -10012,29 +9536,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -10151,10 +9675,6 @@ VAL[7:0]
VAL
</b>[<i>read/write</i>]: Offset calibration for channel 3
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH3_SAT"></a>
<h3><a name="sect_3_28">3.28. Channel 3 saturation register</a></h3>
......@@ -10220,29 +9740,29 @@ CH3_SAT
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -10274,29 +9794,29 @@ RESERVED[16:9]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -10328,8 +9848,8 @@ RESERVED[8:1]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
VAL[14:8]
......@@ -10413,10 +9933,6 @@ VAL[7:0]
VAL
</b>[<i>read/write</i>]: Saturation value for channel 3
<br>Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH4_CTL"></a>
<h3><a name="sect_3_29">3.29. Channel 4 control register</a></h3>
......@@ -10482,29 +9998,29 @@ CH4_CTL
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[24:17]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -10536,29 +10052,29 @@ RESERVED[24:17]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -10590,29 +10106,29 @@ RESERVED[16:9]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -10644,8 +10160,8 @@ RESERVED[8:1]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
......@@ -10675,10 +10191,6 @@ SSR[6:0]
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 4
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH4_STA"></a>
<h3><a name="sect_3_30">3.30. Channel 4 status register</a></h3>
......@@ -10744,29 +10256,29 @@ CH4_STA
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -10798,29 +10310,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -10937,10 +10449,6 @@ VAL[7:0]
VAL
</b>[<i>read-only</i>]: Channel 4 current ADC value
<br>Current ADC raw value. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH4_GAIN"></a>
<h3><a name="sect_3_31">3.31. Channel 4 gain calibration register</a></h3>
......@@ -11006,29 +10514,29 @@ CH4_GAIN
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -11060,29 +10568,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -11199,10 +10707,6 @@ VAL[7:0]
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 4
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH4_OFFSET"></a>
<h3><a name="sect_3_32">3.32. Channel 4 offset calibration register</a></h3>
......@@ -11268,29 +10772,29 @@ CH4_OFFSET
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -11322,29 +10826,29 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -11461,10 +10965,6 @@ VAL[7:0]
VAL
</b>[<i>read/write</i>]: Offset calibration for channel 4
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH4_SAT"></a>
<h3><a name="sect_3_33">3.33. Channel 4 saturation register</a></h3>
......@@ -11530,29 +11030,29 @@ CH4_SAT
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -11584,29 +11084,29 @@ RESERVED[16:9]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -11638,8 +11138,8 @@ RESERVED[8:1]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
VAL[14:8]
......@@ -11723,10 +11223,6 @@ VAL[7:0]
VAL
</b>[<i>read/write</i>]: Saturation value for channel 4
<br>Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
View file @ 23fbb478
......@@ -69,6 +69,7 @@ peripheral {
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -78,6 +79,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -120,7 +122,7 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -130,6 +132,7 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
]]
};
reg {
......@@ -269,7 +272,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -279,6 +282,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -294,7 +298,7 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -304,6 +308,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -406,7 +411,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -416,6 +421,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -432,7 +438,7 @@ peripheral {
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -442,6 +448,7 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
]]
};
reg {
......@@ -457,7 +464,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -467,6 +474,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -482,7 +490,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -492,6 +500,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -507,7 +516,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -517,6 +526,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -532,7 +542,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -542,6 +552,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -558,7 +569,7 @@ peripheral {
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -568,6 +579,7 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
]]
};
reg {
......@@ -583,7 +595,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -593,6 +605,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -608,7 +621,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -618,6 +631,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -633,7 +647,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -643,6 +657,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -658,7 +673,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -668,6 +683,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -684,7 +700,7 @@ peripheral {
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -694,6 +710,7 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
]]
};
reg {
......@@ -709,7 +726,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -719,6 +736,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -734,7 +752,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -744,6 +762,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -759,7 +778,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -769,6 +788,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -784,7 +804,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -794,6 +814,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -810,7 +831,7 @@ peripheral {
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -820,6 +841,7 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
]]
};
reg {
......@@ -835,7 +857,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -845,6 +867,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -860,7 +883,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -870,6 +893,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -885,7 +909,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
......@@ -895,6 +919,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
};
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