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FMC ADC 100M 14b 4cha - Gateware
Commit 3cc58f1f authored by Matthieu Cattin's avatar Matthieu Cattin
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syn: Firmware release 1.1 

- Reports after synthesis and place+route.
- sdb meta-info update in (sdb_meta_pkg.vhd).
parent 9c86f458
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Showing with 1764 additions and 1736 deletions
hdl/spec/rtl/sdb_meta_pkg.vhd
View file @ 3cc58f1f
......@@ -53,14 +53,14 @@ package sdb_meta_pkg is
-- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-32
syn_commit_id => "baa41197a02acc5cbdfbc5c893849b40",
-- git log -1 --format="%H" | cut -c1-320
syn_commit_id => "d8644900e0d9b8544a5e20da9d0567dd",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20130312",
syn_date => x"20130328",
-- Synthesised by (string, 15 char)
syn_username => "mcattin ");
......@@ -69,8 +69,8 @@ package sdb_meta_pkg is
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00010000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20130312", -- yyyymmdd
version => x"00010001", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20130328", -- yyyymmdd
name => "spec_fmcadc100m14b "));
......
hdl/spec/syn/spec_fmc_adc_100Ms.xise
View file @ 3cc58f1f
......@@ -351,478 +351,478 @@
<file xil_pn:name="../ip_cores/wb_ddr_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../ip_cores/adc_serdes.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/monostable/monostable_rtl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/utils/utils_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../rtl/spec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../rtl/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../rtl/utc_core_regs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../rtl/utc_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../rtl/irq_controller_regs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../rtl/irq_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../rtl/sdb_meta_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
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......@@ -881,10 +881,10 @@
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......@@ -896,7 +896,7 @@
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......@@ -968,13 +968,13 @@
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......@@ -1001,7 +1001,7 @@
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
......@@ -1010,13 +1010,13 @@
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd" xil_pn:type="FILE_VHDL">
......@@ -1067,7 +1067,7 @@
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/spec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.par
View file @ 3cc58f1f
Release 13.3 par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
pcbe15575:: Tue Mar 12 08:42:06 2013
pcbe15575:: Thu Mar 28 12:27:09 2013
par -w -intstyle ise -ol high -mt off spec_top_fmc_adc_100Ms_map.ncd
spec_top_fmc_adc_100Ms.ncd spec_top_fmc_adc_100Ms.pcf
......@@ -27,11 +27,11 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,481 out of 27,288 20%
Number used as logic: 5,116 out of 27,288 18%
Number of Slice LUTs: 5,552 out of 27,288 20%
Number used as logic: 5,118 out of 27,288 18%
Number using O6 output only: 3,207
Number using O5 output only: 278
Number using O5 and O6: 1,631
Number using O5 output only: 279
Number using O5 and O6: 1,632
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -40,18 +40,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 363
Number with same-slice register load: 351
Number used exclusively as route-thrus: 432
Number with same-slice register load: 420
Number with same-slice carry load: 12
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,465 out of 6,822 36%
Number of occupied Slices: 2,433 out of 6,822 35%
Nummber of MUXCYs used: 1,456 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,735
Number with an unused Flip Flop: 1,738 out of 7,735 22%
Number with an unused LUT: 2,254 out of 7,735 29%
Number of fully used LUT-FF pairs: 3,743 out of 7,735 48%
Number of LUT Flip Flop pairs used: 7,634
Number with an unused Flip Flop: 1,720 out of 7,634 22%
Number with an unused LUT: 2,082 out of 7,634 27%
Number of fully used LUT-FF pairs: 3,832 out of 7,634 50%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -121,29 +121,29 @@ WARNING:Par:288 - The signal P_WR_REQ<1>_IBUF has no load. PAR will not attempt
Starting Router
Phase 1 : 38958 unrouted; REAL time: 19 secs
Phase 1 : 38908 unrouted; REAL time: 19 secs
Phase 2 : 32852 unrouted; REAL time: 23 secs
Phase 2 : 32826 unrouted; REAL time: 23 secs
Phase 3 : 13212 unrouted; REAL time: 46 secs
Phase 3 : 13028 unrouted; REAL time: 46 secs
Phase 4 : 13215 unrouted; (Setup:0, Hold:7664, Component Switching Limit:0) REAL time: 50 secs
Phase 4 : 13031 unrouted; (Setup:0, Hold:9391, Component Switching Limit:0) REAL time: 50 secs
Updating file: spec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:7546, Component Switching Limit:0) REAL time: 1 mins 16 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:8861, Component Switching Limit:0) REAL time: 1 mins 17 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:7546, Component Switching Limit:0) REAL time: 1 mins 16 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:8861, Component Switching Limit:0) REAL time: 1 mins 17 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:7546, Component Switching Limit:0) REAL time: 1 mins 16 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:8861, Component Switching Limit:0) REAL time: 1 mins 17 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:7546, Component Switching Limit:0) REAL time: 1 mins 16 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:8861, Component Switching Limit:0) REAL time: 1 mins 17 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 17 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 20 secs
Total REAL time to Router completion: 1 mins 20 secs
Total CPU time to Router completion: 1 mins 19 secs
Total CPU time to Router completion: 1 mins 20 secs
Partition Implementation Status
-------------------------------
......@@ -161,19 +161,19 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_125 | BUFGMUX_X2Y2| No | 1200 | 0.069 | 1.280 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X2Y12| No | 665 | 0.186 | 1.398 |
| clk | BUFGMUX_X2Y12| No | 661 | 0.185 | 1.398 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_125 | BUFGMUX_X2Y2| No | 1187 | 0.068 | 1.279 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_100Ms_co | | | | | |
| re/fs_clk | BUFGMUX_X2Y4| No | 160 | 0.247 | 1.473 |
| re/fs_clk | BUFGMUX_X2Y4| No | 153 | 0.248 | 1.473 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/c3_mcb_d | | | | | |
| rp_clk | BUFGMUX_X3Y13| No | 82 | 0.052 | 1.285 |
| rp_clk | BUFGMUX_X3Y13| No | 79 | 0.052 | 1.285 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/io_c | | | | | |
| lk | Local| | 41 | 0.064 | 1.562 |
......@@ -289,18 +289,23 @@ Asterisk (*) preceding a constraint indicates it was not met.
k_2x_180" TS_SYS_CLK5 / 2 PHASE 0 | | | | |
.75 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.030ns| 4.970ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.076ns| | 0| 0
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.066ns| 4.934ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.070ns| | 0| 0
core_cmp_clk_in_rx_pllout_x1_0" T | | | | |
S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | | | | |
PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.042ns| 7.958ns| 0| 0
clk_125_buf" TS_clk20_vcxo_i / 6.25 | HOLD | 0.244ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_adc_dco_n_i = PERIOD TIMEGRP "adc_dco_ | MINLOWPULSE | 0.364ns| 1.636ns| 0| 0
n_i" 2 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.148ns| 7.852ns| 0| 0
clk_125_buf" TS_clk20_vcxo_i / 6.25 | HOLD | 0.252ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_100Ms_core_fs_clk_buf = PE | SETUP | 0.340ns| 7.660ns| 0| 0
RIOD TIMEGRP "cmp_fmc_adc_100Ms_c | HOLD | 0.370ns| | 0| 0
ore_fs_clk_buf" TS_adc_dco_n_i / 0.25 HIG | | | | |
H 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_ddr_clk_buf = PERIOD TIMEGRP "ddr_clk_ | MINLOWPULSE | 0.428ns| 2.572ns| 0| 0
buf" TS_clk20_vcxo_i / 16.6666667 | | | | |
......@@ -308,11 +313,6 @@ Asterisk (*) preceding a constraint indicates it was not met.
----------------------------------------------------------------------------------------------------------
TS_SYS_CLK5 = PERIOD TIMEGRP "SYS_CLK5" 3 | MINLOWPULSE | 0.428ns| 2.572ns| 0| 0
ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_100Ms_core_fs_clk_buf = PE | SETUP | 0.707ns| 7.293ns| 0| 0
RIOD TIMEGRP "cmp_fmc_adc_100Ms_c | HOLD | 0.381ns| | 0| 0
ore_fs_clk_buf" TS_adc_dco_n_i / 0.25 HIG | | | | |
H 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
= PERIOD TIMEGRP "cmp_gn4124_cor | | | | |
......@@ -339,8 +339,8 @@ Asterisk (*) preceding a constraint indicates it was not met.
TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | SETUP | 4.717ns| 7.282ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | HOLD | 0.430ns| | 0| 0
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | SETUP | 5.004ns| 6.995ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | HOLD | 0.388ns| | 0| 0
nfrastructure_inst_mcb_drp_clk_bufg_in_0 | | | | |
= PERIOD TIMEGRP "cmp_ddr | | | | |
_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank | | | | |
......@@ -401,12 +401,12 @@ Derived Constraints for TS_p2l_clkn
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clkn | 5.000ns| 0.925ns| 4.970ns| 0| 0| 0| 29035|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.970ns| 0| 0| 0| 29035|
|TS_p2l_clkn | 5.000ns| 0.925ns| 4.934ns| 0| 0| 0| 29035|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.934ns| 0| 0| 0| 29035|
| buf_P_clk_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.970ns| N/A| 0| 0| 29035| 0|
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.934ns| N/A| 0| 0| 29035| 0|
| _rx_pllout_x1_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -416,10 +416,10 @@ Derived Constraints for TS_clk20_vcxo_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk20_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 402801|
| TS_sys_clk_125_buf | 8.000ns| 7.958ns| N/A| 0| 0| 392401| 0|
|TS_clk20_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 402829|
| TS_sys_clk_125_buf | 8.000ns| 7.852ns| N/A| 0| 0| 392429| 0|
| TS_ddr_clk_buf | 3.000ns| 2.572ns| 2.998ns| 0| 0| 0| 10400|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 12.000ns| 7.282ns| N/A| 0| 0| 10400| 0|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 12.000ns| 6.995ns| N/A| 0| 0| 10400| 0|
| _wrapper_gen_spec_bank3_64b_3| | | | | | | |
| 2b_cmp_ddr3_ctrl_memc3_infras| | | | | | | |
| tructure_inst_mcb_drp_clk_buf| | | | | | | |
......@@ -461,8 +461,8 @@ Derived Constraints for TS_adc_dco_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc_dco_n_i | 2.000ns| 1.636ns| 1.823ns| 0| 0| 0| 18367|
| TS_cmp_fmc_adc_100Ms_core_fs_c| 8.000ns| 7.293ns| N/A| 0| 0| 18367| 0|
|TS_adc_dco_n_i | 2.000ns| 1.636ns| 1.915ns| 0| 0| 0| 18367|
| TS_cmp_fmc_adc_100Ms_core_fs_c| 8.000ns| 7.660ns| N/A| 0| 0| 18367| 0|
| lk_buf | | | | | | | |
| TS_cmp_fmc_adc_100Ms_core_serd| 1.000ns| N/A| N/A| 0| 0| 0| 0|
| es_clk | | | | | | | |
......@@ -482,10 +482,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 23 secs
Total CPU time to PAR completion: 1 mins 22 secs
Total REAL time to PAR completion: 1 mins 24 secs
Total CPU time to PAR completion: 1 mins 23 secs
Peak Memory Usage: 333 MB
Peak Memory Usage: 332 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
View file @ 3cc58f1f
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
View file @ 3cc58f1f
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
View file @ 3cc58f1f
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Mar 12 08:37:23 2013
Mapped Date : Thu Mar 28 12:22:38 2013
Design Summary
--------------
......@@ -23,11 +23,11 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,481 out of 27,288 20%
Number used as logic: 5,116 out of 27,288 18%
Number of Slice LUTs: 5,552 out of 27,288 20%
Number used as logic: 5,118 out of 27,288 18%
Number using O6 output only: 3,207
Number using O5 output only: 278
Number using O5 and O6: 1,631
Number using O5 output only: 279
Number using O5 and O6: 1,632
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -36,18 +36,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 363
Number with same-slice register load: 351
Number used exclusively as route-thrus: 432
Number with same-slice register load: 420
Number with same-slice carry load: 12
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,465 out of 6,822 36%
Number of occupied Slices: 2,433 out of 6,822 35%
Nummber of MUXCYs used: 1,456 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,735
Number with an unused Flip Flop: 1,738 out of 7,735 22%
Number with an unused LUT: 2,254 out of 7,735 29%
Number of fully used LUT-FF pairs: 3,743 out of 7,735 48%
Number of LUT Flip Flop pairs used: 7,634
Number with an unused Flip Flop: 1,720 out of 7,634 22%
Number with an unused LUT: 2,082 out of 7,634 27%
Number of fully used LUT-FF pairs: 3,832 out of 7,634 50%
Number of unique control sets: 261
Number of slice register sites lost
to control set restrictions: 678 out of 54,576 1%
......@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.78
Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 409 MB
Total REAL time to MAP completion: 4 mins 37 secs
Total CPU time to MAP completion (all processors): 4 mins 37 secs
Total REAL time to MAP completion: 4 mins 25 secs
Total CPU time to MAP completion (all processors): 4 mins 24 secs
Table of Contents
-----------------
......@@ -164,8 +164,8 @@ INFO:LIT:243 - Logical network
_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 8 more times for the following
(max. 5 shown):
N786,
N788,
N794,
N796,
aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF
......
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